drivers/edac/skx_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *
   4  * Shared code by both skx_edac and i10nm_edac. Originally split out
   5  * from the skx_edac driver.
   6  *
   7  * This file is linked into both skx_edac and i10nm_edac drivers. In
   8  * order to avoid link errors, this file must be like a pure library
   9  * without including symbols and defines which would otherwise conflict,
  10  * when linked once into a module and into a built-in object, at the
  11  * same time. For example, __this_module symbol references when that
  12  * file is being linked into a built-in object.
  13  *
  14  * Copyright (c) 2018, Intel Corporation.
  15  */
  16
  17 #include <linux/acpi.h>
  18 #include <linux/dmi.h>
  19 #include <linux/adxl.h>
  20 #include <acpi/nfit.h>
  21 #include <asm/mce.h>
  22 #include "edac_module.h"
  23 #include "skx_common.h"
  24
  25 static const char * const component_names[] = {
  26         [INDEX_SOCKET]  = "ProcessorSocketId",
  27         [INDEX_MEMCTRL] = "MemoryControllerId",
  28         [INDEX_CHANNEL] = "ChannelId",
  29         [INDEX_DIMM]    = "DimmSlotId",
  30 };
  31
  32 static int component_indices[ARRAY_SIZE(component_names)];
  33 static int adxl_component_count;
  34 static const char * const *adxl_component_names;
  35 static u64 *adxl_values;
  36 static char *adxl_msg;
  37
  38 static char skx_msg[MSG_SIZE];
  39 static skx_decode_f skx_decode;
  40 static skx_show_retry_log_f skx_show_retry_rd_err_log;
  41 static u64 skx_tolm, skx_tohm;
  42 static LIST_HEAD(dev_edac_list);
  43
  44 int __init skx_adxl_get(void)
  45 {
  46         const char * const *names;
  47         int i, j;
  48
  49         names = adxl_get_component_names();
  50         if (!names) {
  51                 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
  52                 return -ENODEV;
  53         }
  54
  55         for (i = 0; i < INDEX_MAX; i++) {
  56                 for (j = 0; names[j]; j++) {
  57                         if (!strcmp(component_names[i], names[j])) {
  58                                 component_indices[i] = j;
  59                                 break;
  60                         }
  61                 }
  62
  63                 if (!names[j])
  64                         goto err;
  65         }
  66
  67         adxl_component_names = names;
  68         while (*names++)
  69                 adxl_component_count++;
  70
  71         adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
  72                               GFP_KERNEL);
  73         if (!adxl_values) {
  74                 adxl_component_count = 0;
  75                 return -ENOMEM;
  76         }
  77
  78         adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
  79         if (!adxl_msg) {
  80                 adxl_component_count = 0;
  81                 kfree(adxl_values);
  82                 return -ENOMEM;
  83         }
  84
  85         return 0;
  86 err:
  87         skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
  88                    component_names[i]);
  89         for (j = 0; names[j]; j++)
  90                 skx_printk(KERN_CONT, "%s ", names[j]);
  91         skx_printk(KERN_CONT, "\n");
  92
  93         return -ENODEV;
  94 }
  95
  96 void __exit skx_adxl_put(void)
  97 {
  98         kfree(adxl_values);
  99         kfree(adxl_msg);
 100 }
 101
 102 static bool skx_adxl_decode(struct decoded_addr *res)
 103 {
 104         struct skx_dev *d;
 105         int i, len = 0;
 106
 107         if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
 108                                       res->addr < BIT_ULL(32))) {
 109                 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
 110                 return false;
 111         }
 112
 113         if (adxl_decode(res->addr, adxl_values)) {
 114                 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
 115                 return false;
 116         }
 117
 118         res->socket  = (int)adxl_values[component_indices[INDEX_SOCKET]];
 119         res->imc     = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
 120         res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
 121         res->dimm    = (int)adxl_values[component_indices[INDEX_DIMM]];
 122
 123         if (res->imc > NUM_IMC - 1) {
 124                 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
 125                 return false;
 126         }
 127
 128         list_for_each_entry(d, &dev_edac_list, list) {
 129                 if (d->imc[0].src_id == res->socket) {
 130                         res->dev = d;
 131                         break;
 132                 }
 133         }
 134
 135         if (!res->dev) {
 136                 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
 137                            res->socket, res->imc);
 138                 return false;
 139         }
 140
 141         for (i = 0; i < adxl_component_count; i++) {
 142                 if (adxl_values[i] == ~0x0ull)
 143                         continue;
 144
 145                 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
 146                                 adxl_component_names[i], adxl_values[i]);
 147                 if (MSG_SIZE - len <= 0)
 148                         break;
 149         }
 150
 151         return true;
 152 }
 153
 154 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
 155 {
 156         skx_decode = decode;
 157         skx_show_retry_rd_err_log = show_retry_log;
 158 }
 159
 160 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
 161 {
 162         u32 reg;
 163
 164         if (pci_read_config_dword(d->util_all, off, &reg)) {
 165                 skx_printk(KERN_ERR, "Failed to read src id\n");
 166                 return -ENODEV;
 167         }
 168
 169         *id = GET_BITFIELD(reg, 12, 14);
 170         return 0;
 171 }
 172
 173 int skx_get_node_id(struct skx_dev *d, u8 *id)
 174 {
 175         u32 reg;
 176
 177         if (pci_read_config_dword(d->util_all, 0xf4, &reg)) {
 178                 skx_printk(KERN_ERR, "Failed to read node id\n");
 179                 return -ENODEV;
 180         }
 181
 182         *id = GET_BITFIELD(reg, 0, 2);
 183         return 0;
 184 }
 185
 186 static int get_width(u32 mtr)
 187 {
 188         switch (GET_BITFIELD(mtr, 8, 9)) {
 189         case 0:
 190                 return DEV_X4;
 191         case 1:
 192                 return DEV_X8;
 193         case 2:
 194                 return DEV_X16;
 195         }
 196         return DEV_UNKNOWN;
 197 }
 198
 199 /*
 200  * We use the per-socket device @did to count how many sockets are present,
 201  * and to detemine which PCI buses are associated with each socket. Allocate
 202  * and build the full list of all the skx_dev structures that we need here.
 203  */
 204 int skx_get_all_bus_mappings(unsigned int did, int off, enum type type,
 205                              struct list_head **list)
 206 {
 207         struct pci_dev *pdev, *prev;
 208         struct skx_dev *d;
 209         u32 reg;
 210         int ndev = 0;
 211
 212         prev = NULL;
 213         for (;;) {
 214                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, prev);
 215                 if (!pdev)
 216                         break;
 217                 ndev++;
 218                 d = kzalloc(sizeof(*d), GFP_KERNEL);
 219                 if (!d) {
 220                         pci_dev_put(pdev);
 221                         return -ENOMEM;
 222                 }
 223
 224                 if (pci_read_config_dword(pdev, off, &reg)) {
 225                         kfree(d);
 226                         pci_dev_put(pdev);
 227                         skx_printk(KERN_ERR, "Failed to read bus idx\n");
 228                         return -ENODEV;
 229                 }
 230
 231                 d->bus[0] = GET_BITFIELD(reg, 0, 7);
 232                 d->bus[1] = GET_BITFIELD(reg, 8, 15);
 233                 if (type == SKX) {
 234                         d->seg = pci_domain_nr(pdev->bus);
 235                         d->bus[2] = GET_BITFIELD(reg, 16, 23);
 236                         d->bus[3] = GET_BITFIELD(reg, 24, 31);
 237                 } else {
 238                         d->seg = GET_BITFIELD(reg, 16, 23);
 239                 }
 240
 241                 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
 242                          d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
 243                 list_add_tail(&d->list, &dev_edac_list);
 244                 prev = pdev;
 245         }
 246
 247         if (list)
 248                 *list = &dev_edac_list;
 249         return ndev;
 250 }
 251
 252 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
 253 {
 254         struct pci_dev *pdev;
 255         u32 reg;
 256
 257         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
 258         if (!pdev) {
 259                 skx_printk(KERN_ERR, "Can't get tolm/tohm\n");
 260                 return -ENODEV;
 261         }
 262
 263         if (pci_read_config_dword(pdev, off[0], &reg)) {
 264                 skx_printk(KERN_ERR, "Failed to read tolm\n");
 265                 goto fail;
 266         }
 267         skx_tolm = reg;
 268
 269         if (pci_read_config_dword(pdev, off[1], &reg)) {
 270                 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
 271                 goto fail;
 272         }
 273         skx_tohm = reg;
 274
 275         if (pci_read_config_dword(pdev, off[2], &reg)) {
 276                 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
 277                 goto fail;
 278         }
 279         skx_tohm |= (u64)reg << 32;
 280
 281         pci_dev_put(pdev);
 282         *tolm = skx_tolm;
 283         *tohm = skx_tohm;
 284         edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
 285         return 0;
 286 fail:
 287         pci_dev_put(pdev);
 288         return -ENODEV;
 289 }
 290
 291 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
 292                              int minval, int maxval, const char *name)
 293 {
 294         u32 val = GET_BITFIELD(reg, lobit, hibit);
 295
 296         if (val < minval || val > maxval) {
 297                 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
 298                 return -EINVAL;
 299         }
 300         return val + add;
 301 }
 302
 303 #define numrank(reg)    skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
 304 #define numrow(reg)     skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
 305 #define numcol(reg)     skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
 306
 307 int skx_get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
 308                       struct skx_imc *imc, int chan, int dimmno)
 309 {
 310         int  banks = 16, ranks, rows, cols, npages;
 311         u64 size;
 312
 313         ranks = numrank(mtr);
 314         rows = numrow(mtr);
 315         cols = numcol(mtr);
 316
 317         /*
 318          * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
 319          */
 320         size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
 321         npages = MiB_TO_PAGES(size);
 322
 323         edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
 324                  imc->mc, chan, dimmno, size, npages,
 325                  banks, 1 << ranks, rows, cols);
 326
 327         imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
 328         imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
 329         imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
 330         imc->chan[chan].dimms[dimmno].rowbits = rows;
 331         imc->chan[chan].dimms[dimmno].colbits = cols;
 332
 333         dimm->nr_pages = npages;
 334         dimm->grain = 32;
 335         dimm->dtype = get_width(mtr);
 336         dimm->mtype = MEM_DDR4;
 337         dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 338         snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 339                  imc->src_id, imc->lmc, chan, dimmno);
 340
 341         return 1;
 342 }
 343
 344 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
 345                         int chan, int dimmno, const char *mod_str)
 346 {
 347         int smbios_handle;
 348         u32 dev_handle;
 349         u16 flags;
 350         u64 size = 0;
 351
 352         dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
 353                                                    imc->src_id, 0);
 354
 355         smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
 356         if (smbios_handle == -EOPNOTSUPP) {
 357                 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
 358                 goto unknown_size;
 359         }
 360
 361         if (smbios_handle < 0) {
 362                 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
 363                 goto unknown_size;
 364         }
 365
 366         if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
 367                 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
 368                 goto unknown_size;
 369         }
 370
 371         size = dmi_memdev_size(smbios_handle);
 372         if (size == ~0ull)
 373                 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
 374                            dev_handle, smbios_handle);
 375
 376 unknown_size:
 377         dimm->nr_pages = size >> PAGE_SHIFT;
 378         dimm->grain = 32;
 379         dimm->dtype = DEV_UNKNOWN;
 380         dimm->mtype = MEM_NVDIMM;
 381         dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 382
 383         edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
 384                  imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
 385
 386         snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 387                  imc->src_id, imc->lmc, chan, dimmno);
 388
 389         return (size == 0 || size == ~0ull) ? 0 : 1;
 390 }
 391
 392 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
 393                      const char *ctl_name, const char *mod_str,
 394                      get_dimm_config_f get_dimm_config)
 395 {
 396         struct mem_ctl_info *mci;
 397         struct edac_mc_layer layers[2];
 398         struct skx_pvt *pvt;
 399         int rc;
 400
 401         /* Allocate a new MC control structure */
 402         layers[0].type = EDAC_MC_LAYER_CHANNEL;
 403         layers[0].size = NUM_CHANNELS;
 404         layers[0].is_virt_csrow = false;
 405         layers[1].type = EDAC_MC_LAYER_SLOT;
 406         layers[1].size = NUM_DIMMS;
 407         layers[1].is_virt_csrow = true;
 408         mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
 409                             sizeof(struct skx_pvt));
 410
 411         if (unlikely(!mci))
 412                 return -ENOMEM;
 413
 414         edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
 415
 416         /* Associate skx_dev and mci for future usage */
 417         imc->mci = mci;
 418         pvt = mci->pvt_info;
 419         pvt->imc = imc;
 420
 421         mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
 422                                   imc->node_id, imc->lmc);
 423         if (!mci->ctl_name) {
 424                 rc = -ENOMEM;
 425                 goto fail0;
 426         }
 427
 428         mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
 429         mci->edac_ctl_cap = EDAC_FLAG_NONE;
 430         mci->edac_cap = EDAC_FLAG_NONE;
 431         mci->mod_name = mod_str;
 432         mci->dev_name = pci_name(pdev);
 433         mci->ctl_page_to_phys = NULL;
 434
 435         rc = get_dimm_config(mci);
 436         if (rc < 0)
 437                 goto fail;
 438
 439         /* Record ptr to the generic device */
 440         mci->pdev = &pdev->dev;
 441
 442         /* Add this new MC control structure to EDAC's list of MCs */
 443         if (unlikely(edac_mc_add_mc(mci))) {
 444                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
 445                 rc = -EINVAL;
 446                 goto fail;
 447         }
 448
 449         return 0;
 450
 451 fail:
 452         kfree(mci->ctl_name);
 453 fail0:
 454         edac_mc_free(mci);
 455         imc->mci = NULL;
 456         return rc;
 457 }
 458
 459 static void skx_unregister_mci(struct skx_imc *imc)
 460 {
 461         struct mem_ctl_info *mci = imc->mci;
 462
 463         if (!mci)
 464                 return;
 465
 466         edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
 467
 468         /* Remove MC sysfs nodes */
 469         edac_mc_del_mc(mci->pdev);
 470
 471         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
 472         kfree(mci->ctl_name);
 473         edac_mc_free(mci);
 474 }
 475
 476 static void skx_mce_output_error(struct mem_ctl_info *mci,
 477                                  const struct mce *m,
 478                                  struct decoded_addr *res)
 479 {
 480         enum hw_event_mc_err_type tp_event;
 481         char *optype;
 482         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
 483         bool overflow = GET_BITFIELD(m->status, 62, 62);
 484         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
 485         bool recoverable;
 486         int len;
 487         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
 488         u32 mscod = GET_BITFIELD(m->status, 16, 31);
 489         u32 errcode = GET_BITFIELD(m->status, 0, 15);
 490         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
 491
 492         recoverable = GET_BITFIELD(m->status, 56, 56);
 493
 494         if (uncorrected_error) {
 495                 core_err_cnt = 1;
 496                 if (ripv) {
 497                         tp_event = HW_EVENT_ERR_FATAL;
 498                 } else {
 499                         tp_event = HW_EVENT_ERR_UNCORRECTED;
 500                 }
 501         } else {
 502                 tp_event = HW_EVENT_ERR_CORRECTED;
 503         }
 504
 505         /*
 506          * According to Intel Architecture spec vol 3B,
 507          * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
 508          * memory errors should fit one of these masks:
 509          *      000f 0000 1mmm cccc (binary)
 510          *      000f 0010 1mmm cccc (binary)    [RAM used as cache]
 511          * where:
 512          *      f = Correction Report Filtering Bit. If 1, subsequent errors
 513          *          won't be shown
 514          *      mmm = error type
 515          *      cccc = channel
 516          * If the mask doesn't match, report an error to the parsing logic
 517          */
 518         if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
 519                 optype = "Can't parse: it is not a mem";
 520         } else {
 521                 switch (optypenum) {
 522                 case 0:
 523                         optype = "generic undef request error";
 524                         break;
 525                 case 1:
 526                         optype = "memory read error";
 527                         break;
 528                 case 2:
 529                         optype = "memory write error";
 530                         break;
 531                 case 3:
 532                         optype = "addr/cmd error";
 533                         break;
 534                 case 4:
 535                         optype = "memory scrubbing error";
 536                         break;
 537                 default:
 538                         optype = "reserved";
 539                         break;
 540                 }
 541         }
 542         if (adxl_component_count) {
 543                 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
 544                          overflow ? " OVERFLOW" : "",
 545                          (uncorrected_error && recoverable) ? " recoverable" : "",
 546                          mscod, errcode, adxl_msg);
 547         } else {
 548                 len = snprintf(skx_msg, MSG_SIZE,
 549                          "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
 550                          overflow ? " OVERFLOW" : "",
 551                          (uncorrected_error && recoverable) ? " recoverable" : "",
 552                          mscod, errcode,
 553                          res->socket, res->imc, res->rank,
 554                          res->bank_group, res->bank_address, res->row, res->column);
 555         }
 556
 557         if (skx_show_retry_rd_err_log)
 558                 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len);
 559
 560         edac_dbg(0, "%s\n", skx_msg);
 561
 562         /* Call the helper to output message */
 563         edac_mc_handle_error(tp_event, mci, core_err_cnt,
 564                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
 565                              res->channel, res->dimm, -1,
 566                              optype, skx_msg);
 567 }
 568
 569 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
 570                         void *data)
 571 {
 572         struct mce *mce = (struct mce *)data;
 573         struct decoded_addr res;
 574         struct mem_ctl_info *mci;
 575         char *type;
 576
 577         if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
 578                 return NOTIFY_DONE;
 579
 580         /* ignore unless this is memory related with an address */
 581         if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
 582                 return NOTIFY_DONE;
 583
 584         memset(&res, 0, sizeof(res));
 585         res.addr = mce->addr;
 586
 587         if (adxl_component_count) {
 588                 if (!skx_adxl_decode(&res))
 589                         return NOTIFY_DONE;
 590         } else if (!skx_decode || !skx_decode(&res)) {
 591                 return NOTIFY_DONE;
 592         }
 593
 594         mci = res.dev->imc[res.imc].mci;
 595
 596         if (!mci)
 597                 return NOTIFY_DONE;
 598
 599         if (mce->mcgstatus & MCG_STATUS_MCIP)
 600                 type = "Exception";
 601         else
 602                 type = "Event";
 603
 604         skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
 605
 606         skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
 607                            "Bank %d: 0x%llx\n", mce->extcpu, type,
 608                            mce->mcgstatus, mce->bank, mce->status);
 609         skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
 610         skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
 611         skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
 612
 613         skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
 614                            "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
 615                            mce->time, mce->socketid, mce->apicid);
 616
 617         skx_mce_output_error(mci, mce, &res);
 618
 619         return NOTIFY_DONE;
 620 }
 621
 622 void skx_remove(void)
 623 {
 624         int i, j;
 625         struct skx_dev *d, *tmp;
 626
 627         edac_dbg(0, "\n");
 628
 629         list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
 630                 list_del(&d->list);
 631                 for (i = 0; i < NUM_IMC; i++) {
 632                         if (d->imc[i].mci)
 633                                 skx_unregister_mci(&d->imc[i]);
 634
 635                         if (d->imc[i].mdev)
 636                                 pci_dev_put(d->imc[i].mdev);
 637
 638                         if (d->imc[i].mbase)
 639                                 iounmap(d->imc[i].mbase);
 640
 641                         for (j = 0; j < NUM_CHANNELS; j++) {
 642                                 if (d->imc[i].chan[j].cdev)
 643                                         pci_dev_put(d->imc[i].chan[j].cdev);
 644                         }
 645                 }
 646                 if (d->util_all)
 647                         pci_dev_put(d->util_all);
 648                 if (d->sad_all)
 649                         pci_dev_put(d->sad_all);
 650                 if (d->uracu)
 651                         pci_dev_put(d->uracu);
 652
 653                 kfree(d);
 654         }
 655 }