drivers/serial/21285.c

   1 /*
   2  * linux/drivers/serial/21285.c
   3  *
   4  * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
   5  *
   6  * Based on drivers/char/serial.c
   7  */
   8 #include <linux/module.h>
   9 #include <linux/tty.h>
  10 #include <linux/ioport.h>
  11 #include <linux/init.h>
  12 #include <linux/console.h>
  13 #include <linux/device.h>
  14 #include <linux/tty_flip.h>
  15 #include <linux/serial_core.h>
  16 #include <linux/serial.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/irq.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/hardware/dec21285.h>
  22 #include <mach/hardware.h>
  23
  24 #define BAUD_BASE               (mem_fclk_21285/64)
  25
  26 #define SERIAL_21285_NAME       "ttyFB"
  27 #define SERIAL_21285_MAJOR      204
  28 #define SERIAL_21285_MINOR      4
  29
  30 #define RXSTAT_DUMMY_READ       0x80000000
  31 #define RXSTAT_FRAME            (1 << 0)
  32 #define RXSTAT_PARITY           (1 << 1)
  33 #define RXSTAT_OVERRUN          (1 << 2)
  34 #define RXSTAT_ANYERR           (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
  35
  36 #define H_UBRLCR_BREAK          (1 << 0)
  37 #define H_UBRLCR_PARENB         (1 << 1)
  38 #define H_UBRLCR_PAREVN         (1 << 2)
  39 #define H_UBRLCR_STOPB          (1 << 3)
  40 #define H_UBRLCR_FIFO           (1 << 4)
  41
  42 static const char serial21285_name[] = "Footbridge UART";
  43
  44 #define tx_enabled(port)        ((port)->unused[0])
  45 #define rx_enabled(port)        ((port)->unused[1])
  46
  47 /*
  48  * The documented expression for selecting the divisor is:
  49  *  BAUD_BASE / baud - 1
  50  * However, typically BAUD_BASE is not divisible by baud, so
  51  * we want to select the divisor that gives us the minimum
  52  * error.  Therefore, we want:
  53  *  int(BAUD_BASE / baud - 0.5) ->
  54  *  int(BAUD_BASE / baud - (baud >> 1) / baud) ->
  55  *  int((BAUD_BASE - (baud >> 1)) / baud)
  56  */
  57
  58 static void serial21285_stop_tx(struct uart_port *port)
  59 {
  60         if (tx_enabled(port)) {
  61                 disable_irq_nosync(IRQ_CONTX);
  62                 tx_enabled(port) = 0;
  63         }
  64 }
  65
  66 static void serial21285_start_tx(struct uart_port *port)
  67 {
  68         if (!tx_enabled(port)) {
  69                 enable_irq(IRQ_CONTX);
  70                 tx_enabled(port) = 1;
  71         }
  72 }
  73
  74 static void serial21285_stop_rx(struct uart_port *port)
  75 {
  76         if (rx_enabled(port)) {
  77                 disable_irq_nosync(IRQ_CONRX);
  78                 rx_enabled(port) = 0;
  79         }
  80 }
  81
  82 static void serial21285_enable_ms(struct uart_port *port)
  83 {
  84 }
  85
  86 static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
  87 {
  88         struct uart_port *port = dev_id;
  89         struct tty_struct *tty = port->state->port.tty;
  90         unsigned int status, ch, flag, rxs, max_count = 256;
  91
  92         status = *CSR_UARTFLG;
  93         while (!(status & 0x10) && max_count--) {
  94                 ch = *CSR_UARTDR;
  95                 flag = TTY_NORMAL;
  96                 port->icount.rx++;
  97
  98                 rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
  99                 if (unlikely(rxs & RXSTAT_ANYERR)) {
 100                         if (rxs & RXSTAT_PARITY)
 101                                 port->icount.parity++;
 102                         else if (rxs & RXSTAT_FRAME)
 103                                 port->icount.frame++;
 104                         if (rxs & RXSTAT_OVERRUN)
 105                                 port->icount.overrun++;
 106
 107                         rxs &= port->read_status_mask;
 108
 109                         if (rxs & RXSTAT_PARITY)
 110                                 flag = TTY_PARITY;
 111                         else if (rxs & RXSTAT_FRAME)
 112                                 flag = TTY_FRAME;
 113                 }
 114
 115                 uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
 116
 117                 status = *CSR_UARTFLG;
 118         }
 119         tty_flip_buffer_push(tty);
 120
 121         return IRQ_HANDLED;
 122 }
 123
 124 static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
 125 {
 126         struct uart_port *port = dev_id;
 127         struct circ_buf *xmit = &port->state->xmit;
 128         int count = 256;
 129
 130         if (port->x_char) {
 131                 *CSR_UARTDR = port->x_char;
 132                 port->icount.tx++;
 133                 port->x_char = 0;
 134                 goto out;
 135         }
 136         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 137                 serial21285_stop_tx(port);
 138                 goto out;
 139         }
 140
 141         do {
 142                 *CSR_UARTDR = xmit->buf[xmit->tail];
 143                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 144                 port->icount.tx++;
 145                 if (uart_circ_empty(xmit))
 146                         break;
 147         } while (--count > 0 && !(*CSR_UARTFLG & 0x20));
 148
 149         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 150                 uart_write_wakeup(port);
 151
 152         if (uart_circ_empty(xmit))
 153                 serial21285_stop_tx(port);
 154
 155  out:
 156         return IRQ_HANDLED;
 157 }
 158
 159 static unsigned int serial21285_tx_empty(struct uart_port *port)
 160 {
 161         return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
 162 }
 163
 164 /* no modem control lines */
 165 static unsigned int serial21285_get_mctrl(struct uart_port *port)
 166 {
 167         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 168 }
 169
 170 static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
 171 {
 172 }
 173
 174 static void serial21285_break_ctl(struct uart_port *port, int break_state)
 175 {
 176         unsigned long flags;
 177         unsigned int h_lcr;
 178
 179         spin_lock_irqsave(&port->lock, flags);
 180         h_lcr = *CSR_H_UBRLCR;
 181         if (break_state)
 182                 h_lcr |= H_UBRLCR_BREAK;
 183         else
 184                 h_lcr &= ~H_UBRLCR_BREAK;
 185         *CSR_H_UBRLCR = h_lcr;
 186         spin_unlock_irqrestore(&port->lock, flags);
 187 }
 188
 189 static int serial21285_startup(struct uart_port *port)
 190 {
 191         int ret;
 192
 193         tx_enabled(port) = 1;
 194         rx_enabled(port) = 1;
 195
 196         ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
 197                           serial21285_name, port);
 198         if (ret == 0) {
 199                 ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
 200                                   serial21285_name, port);
 201                 if (ret)
 202                         free_irq(IRQ_CONRX, port);
 203         }
 204
 205         return ret;
 206 }
 207
 208 static void serial21285_shutdown(struct uart_port *port)
 209 {
 210         free_irq(IRQ_CONTX, port);
 211         free_irq(IRQ_CONRX, port);
 212 }
 213
 214 static void
 215 serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
 216                         struct ktermios *old)
 217 {
 218         unsigned long flags;
 219         unsigned int baud, quot, h_lcr;
 220
 221         /*
 222          * We don't support modem control lines.
 223          */
 224         termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
 225         termios->c_cflag |= CLOCAL;
 226
 227         /*
 228          * We don't support BREAK character recognition.
 229          */
 230         termios->c_iflag &= ~(IGNBRK | BRKINT);
 231
 232         /*
 233          * Ask the core to calculate the divisor for us.
 234          */
 235         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 236         quot = uart_get_divisor(port, baud);
 237
 238         if (port->state && port->state->port.tty) {
 239                 struct tty_struct *tty = port->state->port.tty;
 240                 unsigned int b = port->uartclk / (16 * quot);
 241                 tty_encode_baud_rate(tty, b, b);
 242         }
 243
 244         switch (termios->c_cflag & CSIZE) {
 245         case CS5:
 246                 h_lcr = 0x00;
 247                 break;
 248         case CS6:
 249                 h_lcr = 0x20;
 250                 break;
 251         case CS7:
 252                 h_lcr = 0x40;
 253                 break;
 254         default: /* CS8 */
 255                 h_lcr = 0x60;
 256                 break;
 257         }
 258
 259         if (termios->c_cflag & CSTOPB)
 260                 h_lcr |= H_UBRLCR_STOPB;
 261         if (termios->c_cflag & PARENB) {
 262                 h_lcr |= H_UBRLCR_PARENB;
 263                 if (!(termios->c_cflag & PARODD))
 264                         h_lcr |= H_UBRLCR_PAREVN;
 265         }
 266
 267         if (port->fifosize)
 268                 h_lcr |= H_UBRLCR_FIFO;
 269
 270         spin_lock_irqsave(&port->lock, flags);
 271
 272         /*
 273          * Update the per-port timeout.
 274          */
 275         uart_update_timeout(port, termios->c_cflag, baud);
 276
 277         /*
 278          * Which character status flags are we interested in?
 279          */
 280         port->read_status_mask = RXSTAT_OVERRUN;
 281         if (termios->c_iflag & INPCK)
 282                 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 283
 284         /*
 285          * Which character status flags should we ignore?
 286          */
 287         port->ignore_status_mask = 0;
 288         if (termios->c_iflag & IGNPAR)
 289                 port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 290         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
 291                 port->ignore_status_mask |= RXSTAT_OVERRUN;
 292
 293         /*
 294          * Ignore all characters if CREAD is not set.
 295          */
 296         if ((termios->c_cflag & CREAD) == 0)
 297                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
 298
 299         quot -= 1;
 300
 301         *CSR_UARTCON = 0;
 302         *CSR_L_UBRLCR = quot & 0xff;
 303         *CSR_M_UBRLCR = (quot >> 8) & 0x0f;
 304         *CSR_H_UBRLCR = h_lcr;
 305         *CSR_UARTCON = 1;
 306
 307         spin_unlock_irqrestore(&port->lock, flags);
 308 }
 309
 310 static const char *serial21285_type(struct uart_port *port)
 311 {
 312         return port->type == PORT_21285 ? "DC21285" : NULL;
 313 }
 314
 315 static void serial21285_release_port(struct uart_port *port)
 316 {
 317         release_mem_region(port->mapbase, 32);
 318 }
 319
 320 static int serial21285_request_port(struct uart_port *port)
 321 {
 322         return request_mem_region(port->mapbase, 32, serial21285_name)
 323                          != NULL ? 0 : -EBUSY;
 324 }
 325
 326 static void serial21285_config_port(struct uart_port *port, int flags)
 327 {
 328         if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
 329                 port->type = PORT_21285;
 330 }
 331
 332 /*
 333  * verify the new serial_struct (for TIOCSSERIAL).
 334  */
 335 static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
 336 {
 337         int ret = 0;
 338         if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
 339                 ret = -EINVAL;
 340         if (ser->irq != NO_IRQ)
 341                 ret = -EINVAL;
 342         if (ser->baud_base != port->uartclk / 16)
 343                 ret = -EINVAL;
 344         return ret;
 345 }
 346
 347 static struct uart_ops serial21285_ops = {
 348         .tx_empty       = serial21285_tx_empty,
 349         .get_mctrl      = serial21285_get_mctrl,
 350         .set_mctrl      = serial21285_set_mctrl,
 351         .stop_tx        = serial21285_stop_tx,
 352         .start_tx       = serial21285_start_tx,
 353         .stop_rx        = serial21285_stop_rx,
 354         .enable_ms      = serial21285_enable_ms,
 355         .break_ctl      = serial21285_break_ctl,
 356         .startup        = serial21285_startup,
 357         .shutdown       = serial21285_shutdown,
 358         .set_termios    = serial21285_set_termios,
 359         .type           = serial21285_type,
 360         .release_port   = serial21285_release_port,
 361         .request_port   = serial21285_request_port,
 362         .config_port    = serial21285_config_port,
 363         .verify_port    = serial21285_verify_port,
 364 };
 365
 366 static struct uart_port serial21285_port = {
 367         .mapbase        = 0x42000160,
 368         .iotype         = UPIO_MEM,
 369         .irq            = NO_IRQ,
 370         .fifosize       = 16,
 371         .ops            = &serial21285_ops,
 372         .flags          = UPF_BOOT_AUTOCONF,
 373 };
 374
 375 static void serial21285_setup_ports(void)
 376 {
 377         serial21285_port.uartclk = mem_fclk_21285 / 4;
 378 }
 379
 380 #ifdef CONFIG_SERIAL_21285_CONSOLE
 381 static void serial21285_console_putchar(struct uart_port *port, int ch)
 382 {
 383         while (*CSR_UARTFLG & 0x20)
 384                 barrier();
 385         *CSR_UARTDR = ch;
 386 }
 387
 388 static void
 389 serial21285_console_write(struct console *co, const char *s,
 390                           unsigned int count)
 391 {
 392         uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
 393 }
 394
 395 static void __init
 396 serial21285_get_options(struct uart_port *port, int *baud,
 397                         int *parity, int *bits)
 398 {
 399         if (*CSR_UARTCON == 1) {
 400                 unsigned int tmp;
 401
 402                 tmp = *CSR_H_UBRLCR;
 403                 switch (tmp & 0x60) {
 404                 case 0x00:
 405                         *bits = 5;
 406                         break;
 407                 case 0x20:
 408                         *bits = 6;
 409                         break;
 410                 case 0x40:
 411                         *bits = 7;
 412                         break;
 413                 default:
 414                 case 0x60:
 415                         *bits = 8;
 416                         break;
 417                 }
 418
 419                 if (tmp & H_UBRLCR_PARENB) {
 420                         *parity = 'o';
 421                         if (tmp & H_UBRLCR_PAREVN)
 422                                 *parity = 'e';
 423                 }
 424
 425                 tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
 426
 427                 *baud = port->uartclk / (16 * (tmp + 1));
 428         }
 429 }
 430
 431 static int __init serial21285_console_setup(struct console *co, char *options)
 432 {
 433         struct uart_port *port = &serial21285_port;
 434         int baud = 9600;
 435         int bits = 8;
 436         int parity = 'n';
 437         int flow = 'n';
 438
 439         if (machine_is_personal_server())
 440                 baud = 57600;
 441
 442         /*
 443          * Check whether an invalid uart number has been specified, and
 444          * if so, search for the first available port that does have
 445          * console support.
 446          */
 447         if (options)
 448                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 449         else
 450                 serial21285_get_options(port, &baud, &parity, &bits);
 451
 452         return uart_set_options(port, co, baud, parity, bits, flow);
 453 }
 454
 455 static struct uart_driver serial21285_reg;
 456
 457 static struct console serial21285_console =
 458 {
 459         .name           = SERIAL_21285_NAME,
 460         .write          = serial21285_console_write,
 461         .device         = uart_console_device,
 462         .setup          = serial21285_console_setup,
 463         .flags          = CON_PRINTBUFFER,
 464         .index          = -1,
 465         .data           = &serial21285_reg,
 466 };
 467
 468 static int __init rs285_console_init(void)
 469 {
 470         serial21285_setup_ports();
 471         register_console(&serial21285_console);
 472         return 0;
 473 }
 474 console_initcall(rs285_console_init);
 475
 476 #define SERIAL_21285_CONSOLE    &serial21285_console
 477 #else
 478 #define SERIAL_21285_CONSOLE    NULL
 479 #endif
 480
 481 static struct uart_driver serial21285_reg = {
 482         .owner                  = THIS_MODULE,
 483         .driver_name            = "ttyFB",
 484         .dev_name               = "ttyFB",
 485         .major                  = SERIAL_21285_MAJOR,
 486         .minor                  = SERIAL_21285_MINOR,
 487         .nr                     = 1,
 488         .cons                   = SERIAL_21285_CONSOLE,
 489 };
 490
 491 static int __init serial21285_init(void)
 492 {
 493         int ret;
 494
 495         printk(KERN_INFO "Serial: 21285 driver\n");
 496
 497         serial21285_setup_ports();
 498
 499         ret = uart_register_driver(&serial21285_reg);
 500         if (ret == 0)
 501                 uart_add_one_port(&serial21285_reg, &serial21285_port);
 502
 503         return ret;
 504 }
 505
 506 static void __exit serial21285_exit(void)
 507 {
 508         uart_remove_one_port(&serial21285_reg, &serial21285_port);
 509         uart_unregister_driver(&serial21285_reg);
 510 }
 511
 512 module_init(serial21285_init);
 513 module_exit(serial21285_exit);
 514
 515 MODULE_LICENSE("GPL");
 516 MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
 517 MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);