arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7763 Setup
   4  *
   5  *  Copyright (C) 2006  Paul Mundt
   6  *  Copyright (C) 2007  Yoshihiro Shimoda
   7  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   8  */
   9 #include <linux/platform_device.h>
  10 #include <linux/init.h>
  11 #include <linux/serial.h>
  12 #include <linux/sh_timer.h>
  13 #include <linux/sh_intc.h>
  14 #include <linux/io.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/usb/ohci_pdriver.h>
  17
  18 static struct plat_sci_port scif0_platform_data = {
  19         .scscr          = SCSCR_REIE,
  20         .type           = PORT_SCIF,
  21         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  22 };
  23
  24 static struct resource scif0_resources[] = {
  25         DEFINE_RES_MEM(0xffe00000, 0x100),
  26         DEFINE_RES_IRQ(evt2irq(0x700)),
  27 };
  28
  29 static struct platform_device scif0_device = {
  30         .name           = "sh-sci",
  31         .id             = 0,
  32         .resource       = scif0_resources,
  33         .num_resources  = ARRAY_SIZE(scif0_resources),
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct plat_sci_port scif1_platform_data = {
  40         .scscr          = SCSCR_REIE,
  41         .type           = PORT_SCIF,
  42         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  43 };
  44
  45 static struct resource scif1_resources[] = {
  46         DEFINE_RES_MEM(0xffe08000, 0x100),
  47         DEFINE_RES_IRQ(evt2irq(0xb80)),
  48 };
  49
  50 static struct platform_device scif1_device = {
  51         .name           = "sh-sci",
  52         .id             = 1,
  53         .resource       = scif1_resources,
  54         .num_resources  = ARRAY_SIZE(scif1_resources),
  55         .dev            = {
  56                 .platform_data  = &scif1_platform_data,
  57         },
  58 };
  59
  60 static struct plat_sci_port scif2_platform_data = {
  61         .scscr          = SCSCR_REIE,
  62         .type           = PORT_SCIF,
  63         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  64 };
  65
  66 static struct resource scif2_resources[] = {
  67         DEFINE_RES_MEM(0xffe10000, 0x100),
  68         DEFINE_RES_IRQ(evt2irq(0xf00)),
  69 };
  70
  71 static struct platform_device scif2_device = {
  72         .name           = "sh-sci",
  73         .id             = 2,
  74         .resource       = scif2_resources,
  75         .num_resources  = ARRAY_SIZE(scif2_resources),
  76         .dev            = {
  77                 .platform_data  = &scif2_platform_data,
  78         },
  79 };
  80
  81 static struct resource rtc_resources[] = {
  82         [0] = {
  83                 .start  = 0xffe80000,
  84                 .end    = 0xffe80000 + 0x58 - 1,
  85                 .flags  = IORESOURCE_IO,
  86         },
  87         [1] = {
  88                 /* Shared Period/Carry/Alarm IRQ */
  89                 .start  = evt2irq(0x480),
  90                 .flags  = IORESOURCE_IRQ,
  91         },
  92 };
  93
  94 static struct platform_device rtc_device = {
  95         .name           = "sh-rtc",
  96         .id             = -1,
  97         .num_resources  = ARRAY_SIZE(rtc_resources),
  98         .resource       = rtc_resources,
  99 };
 100
 101 static struct resource usb_ohci_resources[] = {
 102         [0] = {
 103                 .start  = 0xffec8000,
 104                 .end    = 0xffec80ff,
 105                 .flags  = IORESOURCE_MEM,
 106         },
 107         [1] = {
 108                 .start  = evt2irq(0xc60),
 109                 .end    = evt2irq(0xc60),
 110                 .flags  = IORESOURCE_IRQ,
 111         },
 112 };
 113
 114 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 115
 116 static struct usb_ohci_pdata usb_ohci_pdata;
 117
 118 static struct platform_device usb_ohci_device = {
 119         .name           = "ohci-platform",
 120         .id             = -1,
 121         .dev = {
 122                 .dma_mask               = &usb_ohci_dma_mask,
 123                 .coherent_dma_mask      = 0xffffffff,
 124                 .platform_data          = &usb_ohci_pdata,
 125         },
 126         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 127         .resource       = usb_ohci_resources,
 128 };
 129
 130 static struct resource usbf_resources[] = {
 131         [0] = {
 132                 .start  = 0xffec0000,
 133                 .end    = 0xffec00ff,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .start  = evt2irq(0xc80),
 138                 .end    = evt2irq(0xc80),
 139                 .flags  = IORESOURCE_IRQ,
 140         },
 141 };
 142
 143 static struct platform_device usbf_device = {
 144         .name           = "sh_udc",
 145         .id             = -1,
 146         .dev = {
 147                 .dma_mask               = NULL,
 148                 .coherent_dma_mask      = 0xffffffff,
 149         },
 150         .num_resources  = ARRAY_SIZE(usbf_resources),
 151         .resource       = usbf_resources,
 152 };
 153
 154 static struct sh_timer_config tmu0_platform_data = {
 155         .channels_mask = 7,
 156 };
 157
 158 static struct resource tmu0_resources[] = {
 159         DEFINE_RES_MEM(0xffd80000, 0x30),
 160         DEFINE_RES_IRQ(evt2irq(0x580)),
 161         DEFINE_RES_IRQ(evt2irq(0x5a0)),
 162         DEFINE_RES_IRQ(evt2irq(0x5c0)),
 163 };
 164
 165 static struct platform_device tmu0_device = {
 166         .name           = "sh-tmu",
 167         .id             = 0,
 168         .dev = {
 169                 .platform_data  = &tmu0_platform_data,
 170         },
 171         .resource       = tmu0_resources,
 172         .num_resources  = ARRAY_SIZE(tmu0_resources),
 173 };
 174
 175 static struct sh_timer_config tmu1_platform_data = {
 176         .channels_mask = 7,
 177 };
 178
 179 static struct resource tmu1_resources[] = {
 180         DEFINE_RES_MEM(0xffd88000, 0x2c),
 181         DEFINE_RES_IRQ(evt2irq(0xe00)),
 182         DEFINE_RES_IRQ(evt2irq(0xe20)),
 183         DEFINE_RES_IRQ(evt2irq(0xe40)),
 184 };
 185
 186 static struct platform_device tmu1_device = {
 187         .name           = "sh-tmu",
 188         .id             = 1,
 189         .dev = {
 190                 .platform_data  = &tmu1_platform_data,
 191         },
 192         .resource       = tmu1_resources,
 193         .num_resources  = ARRAY_SIZE(tmu1_resources),
 194 };
 195
 196 static struct platform_device *sh7763_devices[] __initdata = {
 197         &scif0_device,
 198         &scif1_device,
 199         &scif2_device,
 200         &tmu0_device,
 201         &tmu1_device,
 202         &rtc_device,
 203         &usb_ohci_device,
 204         &usbf_device,
 205 };
 206
 207 static int __init sh7763_devices_setup(void)
 208 {
 209         return platform_add_devices(sh7763_devices,
 210                                     ARRAY_SIZE(sh7763_devices));
 211 }
 212 arch_initcall(sh7763_devices_setup);
 213
 214 static struct platform_device *sh7763_early_devices[] __initdata = {
 215         &scif0_device,
 216         &scif1_device,
 217         &scif2_device,
 218         &tmu0_device,
 219         &tmu1_device,
 220 };
 221
 222 void __init plat_early_device_setup(void)
 223 {
 224         early_platform_add_devices(sh7763_early_devices,
 225                                    ARRAY_SIZE(sh7763_early_devices));
 226 }
 227
 228 enum {
 229         UNUSED = 0,
 230
 231         /* interrupt sources */
 232
 233         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 234         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 235         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 236         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 237
 238         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 239         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 240         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 241         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 242         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 243         USBH, USBF, TPU, PCC, MMCIF, SIM,
 244         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 245         SCIF2, GPIO,
 246
 247         /* interrupt groups */
 248
 249         TMU012, TMU345,
 250 };
 251
 252 static struct intc_vect vectors[] __initdata = {
 253         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 254         INTC_VECT(RTC, 0x4c0),
 255         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 256         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 257         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 258         INTC_VECT(LCDC, 0x620),
 259         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 260         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 261         INTC_VECT(DMAC, 0x6c0),
 262         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 263         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 264         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 265         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 266         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 267         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 268         INTC_VECT(HAC, 0x980),
 269         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 270         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 271         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 272         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 273         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 274         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 275         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 276         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 277         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 278         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 279         INTC_VECT(USBF, 0xca0),
 280         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 281         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 282         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 283         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 284         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 285         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 286         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 287         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 288         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 289         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 290         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 291         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 292         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 293 };
 294
 295 static struct intc_group groups[] __initdata = {
 296         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 297         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 298 };
 299
 300 static struct intc_mask_reg mask_registers[] __initdata = {
 301         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 302           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 303             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 304             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 305             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 306         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 307           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 308             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 309             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 310             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 311 };
 312
 313 static struct intc_prio_reg prio_registers[] __initdata = {
 314         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 315                                                  TMU2, TMU2_TICPI } },
 316         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 317         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 318         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 319         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 320                                                  PCISERR, PCIINTA } },
 321         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 322                                                  PCIINTD, PCIC5 } },
 323         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 324         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 325         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 326         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 327         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 328         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 329         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 330         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 331 };
 332
 333 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 334                          mask_registers, prio_registers, NULL);
 335
 336 /* Support for external interrupt pins in IRQ mode */
 337 static struct intc_vect irq_vectors[] __initdata = {
 338         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 339         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 340         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 341         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 342 };
 343
 344 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 345         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 346           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 347 };
 348
 349 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 350         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 351                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 352 };
 353
 354 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 355         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 356                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 357 };
 358
 359 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 360         { 0xffd00024, 0, 32, /* INTREQ */
 361           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 362 };
 363
 364 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 365                              NULL, irq_mask_registers, irq_prio_registers,
 366                              irq_sense_registers, irq_ack_registers);
 367
 368
 369 /* External interrupt pins in IRL mode */
 370 static struct intc_vect irl_vectors[] __initdata = {
 371         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 372         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 373         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 374         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 375         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 376         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 377         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 378         INTC_VECT(IRL_HHHL, 0x3c0),
 379 };
 380
 381 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 382         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 383           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 384             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 385             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 386             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 387 };
 388
 389 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 390         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 391           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 392             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 393             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 394             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 395             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 396 };
 397
 398 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 399                         NULL, irl7654_mask_registers, NULL, NULL);
 400
 401 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 402                         NULL, irl3210_mask_registers, NULL, NULL);
 403
 404 #define INTC_ICR0       0xffd00000
 405 #define INTC_INTMSK0    0xffd00044
 406 #define INTC_INTMSK1    0xffd00048
 407 #define INTC_INTMSK2    0xffd40080
 408 #define INTC_INTMSKCLR1 0xffd00068
 409 #define INTC_INTMSKCLR2 0xffd40084
 410
 411 void __init plat_irq_setup(void)
 412 {
 413         /* disable IRQ7-0 */
 414         __raw_writel(0xff000000, INTC_INTMSK0);
 415
 416         /* disable IRL3-0 + IRL7-4 */
 417         __raw_writel(0xc0000000, INTC_INTMSK1);
 418         __raw_writel(0xfffefffe, INTC_INTMSK2);
 419
 420         register_intc_controller(&intc_desc);
 421 }
 422
 423 void __init plat_irq_setup_pins(int mode)
 424 {
 425         switch (mode) {
 426         case IRQ_MODE_IRQ:
 427                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 428                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 429                 register_intc_controller(&intc_irq_desc);
 430                 break;
 431         case IRQ_MODE_IRL7654:
 432                 /* enable IRL7-4 but don't provide any masking */
 433                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 434                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 435                 break;
 436         case IRQ_MODE_IRL3210:
 437                 /* enable IRL0-3 but don't provide any masking */
 438                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 439                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 440                 break;
 441         case IRQ_MODE_IRL7654_MASK:
 442                 /* enable IRL7-4 and mask using cpu intc controller */
 443                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 444                 register_intc_controller(&intc_irl7654_desc);
 445                 break;
 446         case IRQ_MODE_IRL3210_MASK:
 447                 /* enable IRL0-3 and mask using cpu intc controller */
 448                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 449                 register_intc_controller(&intc_irl3210_desc);
 450                 break;
 451         default:
 452                 BUG();
 453         }
 454 }