clk: samsung: Add bus clock for GPU/G3D on Exynos4412
[linux/fpc-iii.git] / arch / sh / lib64 / udivsi3.S
blobe4788fb4fe82492e6358aa794f4d446a70ff3c7d
1 /* SPDX-License-Identifier: GPL-2.0 */
2         .global __udivsi3
3         .section        .text..SHmedia32,"ax"
4         .align  2
6 /*
7    inputs: r4,r5
8    clobbered: r18,r19,r20,r21,r22,r25,tr0
9    result in r0.
10  */
11 __udivsi3:
12         addz.l r5,r63,r22
13         nsb r22,r0
14         shlld r22,r0,r25
15         shlri r25,48,r25
16         movi 0xffffffffffffbb0c,r20 /* shift count eqiv 76 */
17         sub r20,r25,r21
18         mmulfx.w r21,r21,r19
19         mshflo.w r21,r63,r21
20         ptabs r18,tr0
21         mmulfx.w r25,r19,r19
22         sub r20,r0,r0
23         /* bubble */
24         msub.w r21,r19,r19
26         /*
27          * It would be nice for scheduling to do this add to r21 before
28          * the msub.w, but we need a different value for r19 to keep
29          * errors under control.
30          */
31         addi r19,-2,r21
32         mulu.l r4,r21,r18
33         mmulfx.w r19,r19,r19
34         shlli r21,15,r21
35         shlrd r18,r0,r18
36         mulu.l r18,r22,r20
37         mmacnfx.wl r25,r19,r21
38         /* bubble */
39         sub r4,r20,r25
41         mulu.l r25,r21,r19
42         addi r0,14,r0
43         /* bubble */
44         shlrd r19,r0,r19
45         mulu.l r19,r22,r20
46         add r18,r19,r18
47         /* bubble */
48         sub.l r25,r20,r25
50         mulu.l r25,r21,r19
51         addz.l r25,r63,r25
52         sub r25,r22,r25
53         shlrd r19,r0,r19
54         mulu.l r19,r22,r20
55         addi r25,1,r25
56         add r18,r19,r18
58         cmpgt r25,r20,r25
59         add.l r18,r25,r0
60         blink tr0,r63