drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / amd / powerplay / hwmgr / vega12_pptable.h
blobbf4f5095b80dbbd4eb4e85c67c831d00125e5b2d
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef _VEGA12_PPTABLE_H_
24 #define _VEGA12_PPTABLE_H_
26 #pragma pack(push, 1)
28 #define ATOM_VEGA12_PP_THERMALCONTROLLER_NONE 0
29 #define ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12 25
31 #define ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY 0x1
32 #define ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
33 #define ATOM_VEGA12_PP_PLATFORM_CAP_HARDWAREDC 0x4
34 #define ATOM_VEGA12_PP_PLATFORM_CAP_BACO 0x8
35 #define ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO 0x10
36 #define ATOM_VEGA12_PP_PLATFORM_CAP_ENABLESHADOWPSTATE 0x20
38 #define ATOM_VEGA12_TABLE_REVISION_VEGA12 9
40 enum ATOM_VEGA12_ODSETTING_ID {
41 ATOM_VEGA12_ODSETTING_GFXCLKFMAX = 0,
42 ATOM_VEGA12_ODSETTING_GFXCLKFMIN,
43 ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P1,
44 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1,
45 ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P2,
46 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2,
47 ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P3,
48 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3,
49 ATOM_VEGA12_ODSETTING_UCLKFMAX,
50 ATOM_VEGA12_ODSETTING_POWERPERCENTAGE,
51 ATOM_VEGA12_ODSETTING_FANRPMMIN,
52 ATOM_VEGA12_ODSETTING_FANRPMACOUSTICLIMIT,
53 ATOM_VEGA12_ODSETTING_FANTARGETTEMPERATURE,
54 ATOM_VEGA12_ODSETTING_OPERATINGTEMPMAX,
55 ATOM_VEGA12_ODSETTING_COUNT,
57 typedef enum ATOM_VEGA12_ODSETTING_ID ATOM_VEGA12_ODSETTING_ID;
59 enum ATOM_VEGA12_PPCLOCK_ID {
60 ATOM_VEGA12_PPCLOCK_GFXCLK = 0,
61 ATOM_VEGA12_PPCLOCK_VCLK,
62 ATOM_VEGA12_PPCLOCK_DCLK,
63 ATOM_VEGA12_PPCLOCK_ECLK,
64 ATOM_VEGA12_PPCLOCK_SOCCLK,
65 ATOM_VEGA12_PPCLOCK_UCLK,
66 ATOM_VEGA12_PPCLOCK_DCEFCLK,
67 ATOM_VEGA12_PPCLOCK_DISPCLK,
68 ATOM_VEGA12_PPCLOCK_PIXCLK,
69 ATOM_VEGA12_PPCLOCK_PHYCLK,
70 ATOM_VEGA12_PPCLOCK_COUNT,
72 typedef enum ATOM_VEGA12_PPCLOCK_ID ATOM_VEGA12_PPCLOCK_ID;
75 typedef struct _ATOM_VEGA12_POWERPLAYTABLE
77 struct atom_common_table_header sHeader;
78 UCHAR ucTableRevision;
79 USHORT usTableSize;
80 ULONG ulGoldenPPID;
81 ULONG ulGoldenRevision;
82 USHORT usFormatID;
84 ULONG ulPlatformCaps;
86 UCHAR ucThermalControllerType;
88 USHORT usSmallPowerLimit1;
89 USHORT usSmallPowerLimit2;
90 USHORT usBoostPowerLimit;
91 USHORT usODTurboPowerLimit;
92 USHORT usODPowerSavePowerLimit;
93 USHORT usSoftwareShutdownTemp;
95 ULONG PowerSavingClockMax [ATOM_VEGA12_PPCLOCK_COUNT];
96 ULONG PowerSavingClockMin [ATOM_VEGA12_PPCLOCK_COUNT];
98 ULONG ODSettingsMax [ATOM_VEGA12_ODSETTING_COUNT];
99 ULONG ODSettingsMin [ATOM_VEGA12_ODSETTING_COUNT];
101 USHORT usReserve[5];
103 PPTable_t smcPPTable;
105 } ATOM_Vega12_POWERPLAYTABLE;
107 #pragma pack(pop)
109 #endif