2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Huang Rui <ray.huang@amd.com>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/gfp.h>
32 #include "iceland_smumgr.h"
36 #include "cgs_common.h"
38 #include "smu7_dyn_defaults.h"
39 #include "smu7_hwmgr.h"
40 #include "hardwaremanager.h"
41 #include "ppatomctrl.h"
43 #include "pppcielanes.h"
44 #include "pp_endian.h"
45 #include "processpptables.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
50 #include "smu71_discrete.h"
52 #include "smu_ucode_xfer_vi.h"
53 #include "gmc/gmc_8_1_d.h"
54 #include "gmc/gmc_8_1_sh_mask.h"
55 #include "bif/bif_5_0_d.h"
56 #include "bif/bif_5_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
61 #define ICELAND_SMC_SIZE 0x20000
63 #define POWERTUNE_DEFAULT_SET_MAX 1
64 #define MC_CG_ARB_FREQ_F1 0x0b
65 #define VDDC_VDDCI_DELTA 200
67 #define DEVICE_ID_VI_ICELAND_M_6900 0x6900
68 #define DEVICE_ID_VI_ICELAND_M_6901 0x6901
69 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902
70 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903
72 static const struct iceland_pt_defaults defaults_iceland
= {
74 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
75 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
77 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
78 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
79 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
83 static const struct iceland_pt_defaults defaults_icelandxt
= {
85 * sviLoadLIneEn, SviLoadLineVddC,
86 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
87 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
90 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
91 { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
92 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
96 static const struct iceland_pt_defaults defaults_icelandpro
= {
98 * sviLoadLIneEn, SviLoadLineVddC,
99 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
100 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
103 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
104 { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
105 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
108 static int iceland_start_smc(struct pp_hwmgr
*hwmgr
)
110 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
111 SMC_SYSCON_RESET_CNTL
, rst_reg
, 0);
116 static void iceland_reset_smc(struct pp_hwmgr
*hwmgr
)
118 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
119 SMC_SYSCON_RESET_CNTL
,
124 static void iceland_stop_smc_clock(struct pp_hwmgr
*hwmgr
)
126 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
127 SMC_SYSCON_CLOCK_CNTL_0
,
131 static void iceland_start_smc_clock(struct pp_hwmgr
*hwmgr
)
133 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
134 SMC_SYSCON_CLOCK_CNTL_0
,
138 static int iceland_smu_start_smc(struct pp_hwmgr
*hwmgr
)
140 /* set smc instruct start point at 0x0 */
141 smu7_program_jump_on_start(hwmgr
);
143 /* enable smc clock */
144 iceland_start_smc_clock(hwmgr
);
146 /* de-assert reset */
147 iceland_start_smc(hwmgr
);
149 PHM_WAIT_INDIRECT_FIELD(hwmgr
, SMC_IND
, FIRMWARE_FLAGS
,
150 INTERRUPTS_ENABLED
, 1);
156 static int iceland_upload_smc_firmware_data(struct pp_hwmgr
*hwmgr
,
157 uint32_t length
, const uint8_t *src
,
158 uint32_t limit
, uint32_t start_addr
)
160 uint32_t byte_count
= length
;
163 PP_ASSERT_WITH_CODE((limit
>= byte_count
), "SMC address is beyond the SMC RAM area.", return -EINVAL
);
165 cgs_write_register(hwmgr
->device
, mmSMC_IND_INDEX_0
, start_addr
);
166 PHM_WRITE_FIELD(hwmgr
->device
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 1);
168 while (byte_count
>= 4) {
169 data
= src
[0] * 0x1000000 + src
[1] * 0x10000 + src
[2] * 0x100 + src
[3];
170 cgs_write_register(hwmgr
->device
, mmSMC_IND_DATA_0
, data
);
175 PHM_WRITE_FIELD(hwmgr
->device
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 0);
177 PP_ASSERT_WITH_CODE((0 == byte_count
), "SMC size must be divisible by 4.", return -EINVAL
);
183 static int iceland_smu_upload_firmware_image(struct pp_hwmgr
*hwmgr
)
186 struct cgs_firmware_info info
= {0};
188 if (hwmgr
== NULL
|| hwmgr
->device
== NULL
)
191 /* load SMC firmware */
192 cgs_get_firmware_info(hwmgr
->device
,
193 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU
), &info
);
195 if (info
.image_size
& 3) {
196 pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
200 if (info
.image_size
> ICELAND_SMC_SIZE
) {
201 pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
204 hwmgr
->smu_version
= info
.version
;
205 /* wait for smc boot up */
206 PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr
, SMC_IND
,
207 RCU_UC_EVENTS
, boot_seq_done
, 0);
209 /* clear firmware interrupt enable flag */
210 val
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
211 ixSMC_SYSCON_MISC_CNTL
);
212 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
213 ixSMC_SYSCON_MISC_CNTL
, val
| 1);
216 iceland_stop_smc_clock(hwmgr
);
219 iceland_reset_smc(hwmgr
);
220 iceland_upload_smc_firmware_data(hwmgr
, info
.image_size
,
221 (uint8_t *)info
.kptr
, ICELAND_SMC_SIZE
,
222 info
.ucode_start_address
);
227 static int iceland_request_smu_load_specific_fw(struct pp_hwmgr
*hwmgr
,
228 uint32_t firmwareType
)
233 static int iceland_start_smu(struct pp_hwmgr
*hwmgr
)
237 result
= iceland_smu_upload_firmware_image(hwmgr
);
240 result
= iceland_smu_start_smc(hwmgr
);
244 if (!smu7_is_smc_ram_running(hwmgr
)) {
245 pr_info("smu not running, upload firmware again \n");
246 result
= iceland_smu_upload_firmware_image(hwmgr
);
250 result
= iceland_smu_start_smc(hwmgr
);
255 result
= smu7_request_smu_load_fw(hwmgr
);
260 static int iceland_smu_init(struct pp_hwmgr
*hwmgr
)
262 struct iceland_smumgr
*iceland_priv
= NULL
;
264 iceland_priv
= kzalloc(sizeof(struct iceland_smumgr
), GFP_KERNEL
);
266 if (iceland_priv
== NULL
)
269 hwmgr
->smu_backend
= iceland_priv
;
271 if (smu7_init(hwmgr
)) {
280 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr
*hwmgr
)
282 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
283 struct amdgpu_device
*adev
= hwmgr
->adev
;
286 dev_id
= adev
->pdev
->device
;
289 case DEVICE_ID_VI_ICELAND_M_6900
:
290 case DEVICE_ID_VI_ICELAND_M_6903
:
291 smu_data
->power_tune_defaults
= &defaults_icelandxt
;
294 case DEVICE_ID_VI_ICELAND_M_6901
:
295 case DEVICE_ID_VI_ICELAND_M_6902
:
296 smu_data
->power_tune_defaults
= &defaults_icelandpro
;
299 smu_data
->power_tune_defaults
= &defaults_iceland
;
300 pr_warn("Unknown V.I. Device ID.\n");
306 static int iceland_populate_svi_load_line(struct pp_hwmgr
*hwmgr
)
308 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
309 const struct iceland_pt_defaults
*defaults
= smu_data
->power_tune_defaults
;
311 smu_data
->power_tune_table
.SviLoadLineEn
= defaults
->svi_load_line_en
;
312 smu_data
->power_tune_table
.SviLoadLineVddC
= defaults
->svi_load_line_vddc
;
313 smu_data
->power_tune_table
.SviLoadLineTrimVddC
= 3;
314 smu_data
->power_tune_table
.SviLoadLineOffsetVddC
= 0;
319 static int iceland_populate_tdc_limit(struct pp_hwmgr
*hwmgr
)
322 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
323 const struct iceland_pt_defaults
*defaults
= smu_data
->power_tune_defaults
;
325 tdc_limit
= (uint16_t)(hwmgr
->dyn_state
.cac_dtp_table
->usTDC
* 256);
326 smu_data
->power_tune_table
.TDC_VDDC_PkgLimit
=
327 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit
);
328 smu_data
->power_tune_table
.TDC_VDDC_ThrottleReleaseLimitPerc
=
329 defaults
->tdc_vddc_throttle_release_limit_perc
;
330 smu_data
->power_tune_table
.TDC_MAWt
= defaults
->tdc_mawt
;
335 static int iceland_populate_dw8(struct pp_hwmgr
*hwmgr
, uint32_t fuse_table_offset
)
337 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
338 const struct iceland_pt_defaults
*defaults
= smu_data
->power_tune_defaults
;
341 if (smu7_read_smc_sram_dword(hwmgr
,
343 offsetof(SMU71_Discrete_PmFuses
, TdcWaterfallCtl
),
344 (uint32_t *)&temp
, SMC_RAM_END
))
345 PP_ASSERT_WITH_CODE(false,
346 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
349 smu_data
->power_tune_table
.TdcWaterfallCtl
= defaults
->tdc_waterfall_ctl
;
354 static int iceland_populate_temperature_scaler(struct pp_hwmgr
*hwmgr
)
359 static int iceland_populate_gnb_lpml(struct pp_hwmgr
*hwmgr
)
362 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
364 /* Currently not used. Set all to zero. */
365 for (i
= 0; i
< 8; i
++)
366 smu_data
->power_tune_table
.GnbLPML
[i
] = 0;
371 static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr
*hwmgr
)
373 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
374 uint16_t HiSidd
= smu_data
->power_tune_table
.BapmVddCBaseLeakageHiSidd
;
375 uint16_t LoSidd
= smu_data
->power_tune_table
.BapmVddCBaseLeakageLoSidd
;
376 struct phm_cac_tdp_table
*cac_table
= hwmgr
->dyn_state
.cac_dtp_table
;
378 HiSidd
= (uint16_t)(cac_table
->usHighCACLeakage
/ 100 * 256);
379 LoSidd
= (uint16_t)(cac_table
->usLowCACLeakage
/ 100 * 256);
381 smu_data
->power_tune_table
.BapmVddCBaseLeakageHiSidd
=
382 CONVERT_FROM_HOST_TO_SMC_US(HiSidd
);
383 smu_data
->power_tune_table
.BapmVddCBaseLeakageLoSidd
=
384 CONVERT_FROM_HOST_TO_SMC_US(LoSidd
);
389 static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr
*hwmgr
)
392 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
393 uint8_t *hi_vid
= smu_data
->power_tune_table
.BapmVddCVidHiSidd
;
394 uint8_t *lo_vid
= smu_data
->power_tune_table
.BapmVddCVidLoSidd
;
396 PP_ASSERT_WITH_CODE(NULL
!= hwmgr
->dyn_state
.cac_leakage_table
,
397 "The CAC Leakage table does not exist!", return -EINVAL
);
398 PP_ASSERT_WITH_CODE(hwmgr
->dyn_state
.cac_leakage_table
->count
<= 8,
399 "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL
);
400 PP_ASSERT_WITH_CODE(hwmgr
->dyn_state
.cac_leakage_table
->count
== hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
,
401 "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL
);
403 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_EVV
)) {
404 for (i
= 0; (uint32_t) i
< hwmgr
->dyn_state
.cac_leakage_table
->count
; i
++) {
405 lo_vid
[i
] = convert_to_vid(hwmgr
->dyn_state
.cac_leakage_table
->entries
[i
].Vddc1
);
406 hi_vid
[i
] = convert_to_vid(hwmgr
->dyn_state
.cac_leakage_table
->entries
[i
].Vddc2
);
409 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL
);
415 static int iceland_populate_vddc_vid(struct pp_hwmgr
*hwmgr
)
418 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
419 uint8_t *vid
= smu_data
->power_tune_table
.VddCVid
;
420 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
422 PP_ASSERT_WITH_CODE(data
->vddc_voltage_table
.count
<= 8,
423 "There should never be more than 8 entries for VddcVid!!!",
426 for (i
= 0; i
< (int)data
->vddc_voltage_table
.count
; i
++) {
427 vid
[i
] = convert_to_vid(data
->vddc_voltage_table
.entries
[i
].value
);
435 static int iceland_populate_pm_fuses(struct pp_hwmgr
*hwmgr
)
437 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
438 uint32_t pm_fuse_table_offset
;
440 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
441 PHM_PlatformCaps_PowerContainment
)) {
442 if (smu7_read_smc_sram_dword(hwmgr
,
443 SMU71_FIRMWARE_HEADER_LOCATION
+
444 offsetof(SMU71_Firmware_Header
, PmFuseTable
),
445 &pm_fuse_table_offset
, SMC_RAM_END
))
446 PP_ASSERT_WITH_CODE(false,
447 "Attempt to get pm_fuse_table_offset Failed!",
451 if (iceland_populate_bapm_vddc_vid_sidd(hwmgr
))
452 PP_ASSERT_WITH_CODE(false,
453 "Attempt to populate bapm vddc vid Failed!",
457 if (iceland_populate_vddc_vid(hwmgr
))
458 PP_ASSERT_WITH_CODE(false,
459 "Attempt to populate vddc vid Failed!",
463 if (iceland_populate_svi_load_line(hwmgr
))
464 PP_ASSERT_WITH_CODE(false,
465 "Attempt to populate SviLoadLine Failed!",
468 if (iceland_populate_tdc_limit(hwmgr
))
469 PP_ASSERT_WITH_CODE(false,
470 "Attempt to populate TDCLimit Failed!", return -EINVAL
);
472 if (iceland_populate_dw8(hwmgr
, pm_fuse_table_offset
))
473 PP_ASSERT_WITH_CODE(false,
474 "Attempt to populate TdcWaterfallCtl, "
475 "LPMLTemperature Min and Max Failed!",
479 if (0 != iceland_populate_temperature_scaler(hwmgr
))
480 PP_ASSERT_WITH_CODE(false,
481 "Attempt to populate LPMLTemperatureScaler Failed!",
485 if (iceland_populate_gnb_lpml(hwmgr
))
486 PP_ASSERT_WITH_CODE(false,
487 "Attempt to populate GnbLPML Failed!",
491 if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr
))
492 PP_ASSERT_WITH_CODE(false,
493 "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
496 if (smu7_copy_bytes_to_smc(hwmgr
, pm_fuse_table_offset
,
497 (uint8_t *)&smu_data
->power_tune_table
,
498 sizeof(struct SMU71_Discrete_PmFuses
), SMC_RAM_END
))
499 PP_ASSERT_WITH_CODE(false,
500 "Attempt to download PmFuseTable Failed!",
506 static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr
*hwmgr
,
507 struct phm_clock_voltage_dependency_table
*allowed_clock_voltage_table
,
508 uint32_t clock
, uint32_t *vol
)
512 /* clock - voltage dependency table is empty table */
513 if (allowed_clock_voltage_table
->count
== 0)
516 for (i
= 0; i
< allowed_clock_voltage_table
->count
; i
++) {
517 /* find first sclk bigger than request */
518 if (allowed_clock_voltage_table
->entries
[i
].clk
>= clock
) {
519 *vol
= allowed_clock_voltage_table
->entries
[i
].v
;
524 /* sclk is bigger than max sclk in the dependence table */
525 *vol
= allowed_clock_voltage_table
->entries
[i
- 1].v
;
530 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr
*hwmgr
,
531 pp_atomctrl_voltage_table_entry
*tab
, uint16_t *hi
,
535 bool vol_found
= false;
536 *hi
= tab
->value
* VOLTAGE_SCALE
;
537 *lo
= tab
->value
* VOLTAGE_SCALE
;
539 /* SCLK/VDDC Dependency Table has to exist. */
540 PP_ASSERT_WITH_CODE(NULL
!= hwmgr
->dyn_state
.vddc_dependency_on_sclk
,
541 "The SCLK/VDDC Dependency Table does not exist.",
544 if (NULL
== hwmgr
->dyn_state
.cac_leakage_table
) {
545 pr_warn("CAC Leakage Table does not exist, using vddc.\n");
550 * Since voltage in the sclk/vddc dependency table is not
551 * necessarily in ascending order because of ELB voltage
552 * patching, loop through entire list to find exact voltage.
554 for (v_index
= 0; (uint32_t)v_index
< hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
; v_index
++) {
555 if (tab
->value
== hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[v_index
].v
) {
557 if ((uint32_t)v_index
< hwmgr
->dyn_state
.cac_leakage_table
->count
) {
558 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Vddc
* VOLTAGE_SCALE
;
559 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Leakage
* VOLTAGE_SCALE
);
561 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
562 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Vddc
* VOLTAGE_SCALE
;
563 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Leakage
* VOLTAGE_SCALE
);
570 * If voltage is not found in the first pass, loop again to
571 * find the best match, equal or higher value.
574 for (v_index
= 0; (uint32_t)v_index
< hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
; v_index
++) {
575 if (tab
->value
<= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[v_index
].v
) {
577 if ((uint32_t)v_index
< hwmgr
->dyn_state
.cac_leakage_table
->count
) {
578 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Vddc
* VOLTAGE_SCALE
;
579 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Leakage
) * VOLTAGE_SCALE
;
581 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
582 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Vddc
* VOLTAGE_SCALE
;
583 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Leakage
* VOLTAGE_SCALE
);
590 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
596 static int iceland_populate_smc_voltage_table(struct pp_hwmgr
*hwmgr
,
597 pp_atomctrl_voltage_table_entry
*tab
,
598 SMU71_Discrete_VoltageLevel
*smc_voltage_tab
)
602 result
= iceland_get_std_voltage_value_sidd(hwmgr
, tab
,
603 &smc_voltage_tab
->StdVoltageHiSidd
,
604 &smc_voltage_tab
->StdVoltageLoSidd
);
606 smc_voltage_tab
->StdVoltageHiSidd
= tab
->value
* VOLTAGE_SCALE
;
607 smc_voltage_tab
->StdVoltageLoSidd
= tab
->value
* VOLTAGE_SCALE
;
610 smc_voltage_tab
->Voltage
= PP_HOST_TO_SMC_US(tab
->value
* VOLTAGE_SCALE
);
611 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab
->StdVoltageHiSidd
);
612 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab
->StdVoltageHiSidd
);
617 static int iceland_populate_smc_vddc_table(struct pp_hwmgr
*hwmgr
,
618 SMU71_Discrete_DpmTable
*table
)
622 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
624 table
->VddcLevelCount
= data
->vddc_voltage_table
.count
;
625 for (count
= 0; count
< table
->VddcLevelCount
; count
++) {
626 result
= iceland_populate_smc_voltage_table(hwmgr
,
627 &(data
->vddc_voltage_table
.entries
[count
]),
628 &(table
->VddcLevel
[count
]));
629 PP_ASSERT_WITH_CODE(0 == result
, "do not populate SMC VDDC voltage table", return -EINVAL
);
631 /* GPIO voltage control */
632 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->voltage_control
)
633 table
->VddcLevel
[count
].Smio
|= data
->vddc_voltage_table
.entries
[count
].smio_low
;
634 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
)
635 table
->VddcLevel
[count
].Smio
= 0;
638 CONVERT_FROM_HOST_TO_SMC_UL(table
->VddcLevelCount
);
643 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr
*hwmgr
,
644 SMU71_Discrete_DpmTable
*table
)
646 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
650 table
->VddciLevelCount
= data
->vddci_voltage_table
.count
;
652 for (count
= 0; count
< table
->VddciLevelCount
; count
++) {
653 result
= iceland_populate_smc_voltage_table(hwmgr
,
654 &(data
->vddci_voltage_table
.entries
[count
]),
655 &(table
->VddciLevel
[count
]));
656 PP_ASSERT_WITH_CODE(result
== 0, "do not populate SMC VDDCI voltage table", return -EINVAL
);
657 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
)
658 table
->VddciLevel
[count
].Smio
|= data
->vddci_voltage_table
.entries
[count
].smio_low
;
660 table
->VddciLevel
[count
].Smio
|= 0;
663 CONVERT_FROM_HOST_TO_SMC_UL(table
->VddciLevelCount
);
668 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr
*hwmgr
,
669 SMU71_Discrete_DpmTable
*table
)
671 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
675 table
->MvddLevelCount
= data
->mvdd_voltage_table
.count
;
677 for (count
= 0; count
< table
->VddciLevelCount
; count
++) {
678 result
= iceland_populate_smc_voltage_table(hwmgr
,
679 &(data
->mvdd_voltage_table
.entries
[count
]),
680 &table
->MvddLevel
[count
]);
681 PP_ASSERT_WITH_CODE(result
== 0, "do not populate SMC mvdd voltage table", return -EINVAL
);
682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
)
683 table
->MvddLevel
[count
].Smio
|= data
->mvdd_voltage_table
.entries
[count
].smio_low
;
685 table
->MvddLevel
[count
].Smio
|= 0;
688 CONVERT_FROM_HOST_TO_SMC_UL(table
->MvddLevelCount
);
694 static int iceland_populate_smc_voltage_tables(struct pp_hwmgr
*hwmgr
,
695 SMU71_Discrete_DpmTable
*table
)
699 result
= iceland_populate_smc_vddc_table(hwmgr
, table
);
700 PP_ASSERT_WITH_CODE(0 == result
,
701 "can not populate VDDC voltage table to SMC", return -EINVAL
);
703 result
= iceland_populate_smc_vdd_ci_table(hwmgr
, table
);
704 PP_ASSERT_WITH_CODE(0 == result
,
705 "can not populate VDDCI voltage table to SMC", return -EINVAL
);
707 result
= iceland_populate_smc_mvdd_table(hwmgr
, table
);
708 PP_ASSERT_WITH_CODE(0 == result
,
709 "can not populate MVDD voltage table to SMC", return -EINVAL
);
714 static int iceland_populate_ulv_level(struct pp_hwmgr
*hwmgr
,
715 struct SMU71_Discrete_Ulv
*state
)
717 uint32_t voltage_response_time
, ulv_voltage
;
719 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
721 state
->CcPwrDynRm
= 0;
722 state
->CcPwrDynRm1
= 0;
724 result
= pp_tables_get_response_times(hwmgr
, &voltage_response_time
, &ulv_voltage
);
725 PP_ASSERT_WITH_CODE((0 == result
), "can not get ULV voltage value", return result
;);
727 if (ulv_voltage
== 0) {
728 data
->ulv_supported
= false;
732 if (data
->voltage_control
!= SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
733 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
734 if (ulv_voltage
> hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
)
735 state
->VddcOffset
= 0;
737 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
738 state
->VddcOffset
= (uint16_t)(hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
- ulv_voltage
);
740 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
741 if (ulv_voltage
> hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
)
742 state
->VddcOffsetVid
= 0;
743 else /* used in SVI2 Mode */
744 state
->VddcOffsetVid
= (uint8_t)(
745 (hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
- ulv_voltage
)
746 * VOLTAGE_VID_OFFSET_SCALE2
747 / VOLTAGE_VID_OFFSET_SCALE1
);
749 state
->VddcPhase
= 1;
751 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm
);
752 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm1
);
753 CONVERT_FROM_HOST_TO_SMC_US(state
->VddcOffset
);
758 static int iceland_populate_ulv_state(struct pp_hwmgr
*hwmgr
,
759 SMU71_Discrete_Ulv
*ulv_level
)
761 return iceland_populate_ulv_level(hwmgr
, ulv_level
);
764 static int iceland_populate_smc_link_level(struct pp_hwmgr
*hwmgr
, SMU71_Discrete_DpmTable
*table
)
766 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
767 struct smu7_dpm_table
*dpm_table
= &data
->dpm_table
;
768 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
771 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
772 for (i
= 0; i
<= dpm_table
->pcie_speed_table
.count
; i
++) {
773 table
->LinkLevel
[i
].PcieGenSpeed
=
774 (uint8_t)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
775 table
->LinkLevel
[i
].PcieLaneCount
=
776 (uint8_t)encode_pcie_lane_width(dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
777 table
->LinkLevel
[i
].EnabledForActivity
=
779 table
->LinkLevel
[i
].SPC
=
780 (uint8_t)(data
->pcie_spc_cap
& 0xff);
781 table
->LinkLevel
[i
].DownThreshold
=
782 PP_HOST_TO_SMC_UL(5);
783 table
->LinkLevel
[i
].UpThreshold
=
784 PP_HOST_TO_SMC_UL(30);
787 smu_data
->smc_state_table
.LinkLevelCount
=
788 (uint8_t)dpm_table
->pcie_speed_table
.count
;
789 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
790 phm_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
795 static int iceland_calculate_sclk_params(struct pp_hwmgr
*hwmgr
,
796 uint32_t engine_clock
, SMU71_Discrete_GraphicsLevel
*sclk
)
798 const struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
799 pp_atomctrl_clock_dividers_vi dividers
;
800 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
801 uint32_t spll_func_cntl_3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
802 uint32_t spll_func_cntl_4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
803 uint32_t cg_spll_spread_spectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
804 uint32_t cg_spll_spread_spectrum_2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
805 uint32_t reference_clock
;
806 uint32_t reference_divider
;
810 /* get the engine clock dividers for this clock value*/
811 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
, engine_clock
, ÷rs
);
813 PP_ASSERT_WITH_CODE(result
== 0,
814 "Error retrieving Engine Clock dividers from VBIOS.", return result
);
816 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
817 reference_clock
= atomctrl_get_reference_clock(hwmgr
);
819 reference_divider
= 1 + dividers
.uc_pll_ref_div
;
821 /* low 14 bits is fraction and high 12 bits is divider*/
822 fbdiv
= dividers
.ul_fb_div
.ul_fb_divider
& 0x3FFFFFF;
824 /* SPLL_FUNC_CNTL setup*/
825 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
826 CG_SPLL_FUNC_CNTL
, SPLL_REF_DIV
, dividers
.uc_pll_ref_div
);
827 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
828 CG_SPLL_FUNC_CNTL
, SPLL_PDIV_A
, dividers
.uc_pll_post_div
);
830 /* SPLL_FUNC_CNTL_3 setup*/
831 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
,
832 CG_SPLL_FUNC_CNTL_3
, SPLL_FB_DIV
, fbdiv
);
834 /* set to use fractional accumulation*/
835 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
,
836 CG_SPLL_FUNC_CNTL_3
, SPLL_DITHEN
, 1);
838 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
839 PHM_PlatformCaps_EngineSpreadSpectrumSupport
)) {
840 pp_atomctrl_internal_ss_info ss_info
;
842 uint32_t vcoFreq
= engine_clock
* dividers
.uc_pll_post_div
;
843 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr
, vcoFreq
, &ss_info
)) {
845 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
846 * ss_info.speed_spectrum_rate -- in unit of khz
848 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
849 uint32_t clkS
= reference_clock
* 5 / (reference_divider
* ss_info
.speed_spectrum_rate
);
851 /* clkv = 2 * D * fbdiv / NS */
852 uint32_t clkV
= 4 * ss_info
.speed_spectrum_percentage
* fbdiv
/ (clkS
* 10000);
854 cg_spll_spread_spectrum
=
855 PHM_SET_FIELD(cg_spll_spread_spectrum
, CG_SPLL_SPREAD_SPECTRUM
, CLKS
, clkS
);
856 cg_spll_spread_spectrum
=
857 PHM_SET_FIELD(cg_spll_spread_spectrum
, CG_SPLL_SPREAD_SPECTRUM
, SSEN
, 1);
858 cg_spll_spread_spectrum_2
=
859 PHM_SET_FIELD(cg_spll_spread_spectrum_2
, CG_SPLL_SPREAD_SPECTRUM_2
, CLKV
, clkV
);
863 sclk
->SclkFrequency
= engine_clock
;
864 sclk
->CgSpllFuncCntl3
= spll_func_cntl_3
;
865 sclk
->CgSpllFuncCntl4
= spll_func_cntl_4
;
866 sclk
->SpllSpreadSpectrum
= cg_spll_spread_spectrum
;
867 sclk
->SpllSpreadSpectrum2
= cg_spll_spread_spectrum_2
;
868 sclk
->SclkDid
= (uint8_t)dividers
.pll_post_divider
;
873 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr
*hwmgr
,
874 const struct phm_phase_shedding_limits_table
*pl
,
875 uint32_t sclk
, uint32_t *p_shed
)
879 /* use the minimum phase shedding */
882 for (i
= 0; i
< pl
->count
; i
++) {
883 if (sclk
< pl
->entries
[i
].Sclk
) {
891 static int iceland_populate_single_graphic_level(struct pp_hwmgr
*hwmgr
,
892 uint32_t engine_clock
,
893 SMU71_Discrete_GraphicsLevel
*graphic_level
)
896 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
898 result
= iceland_calculate_sclk_params(hwmgr
, engine_clock
, graphic_level
);
900 /* populate graphics levels*/
901 result
= iceland_get_dependency_volt_by_clk(hwmgr
,
902 hwmgr
->dyn_state
.vddc_dependency_on_sclk
, engine_clock
,
903 &graphic_level
->MinVddc
);
904 PP_ASSERT_WITH_CODE((0 == result
),
905 "can not find VDDC voltage value for VDDC engine clock dependency table", return result
);
907 /* SCLK frequency in units of 10KHz*/
908 graphic_level
->SclkFrequency
= engine_clock
;
909 graphic_level
->MinVddcPhases
= 1;
911 if (data
->vddc_phase_shed_control
)
912 iceland_populate_phase_value_based_on_sclk(hwmgr
,
913 hwmgr
->dyn_state
.vddc_phase_shed_limits_table
,
915 &graphic_level
->MinVddcPhases
);
917 /* Indicates maximum activity level for this performance level. 50% for now*/
918 graphic_level
->ActivityLevel
= data
->current_profile_setting
.sclk_activity
;
920 graphic_level
->CcPwrDynRm
= 0;
921 graphic_level
->CcPwrDynRm1
= 0;
922 /* this level can be used if activity is high enough.*/
923 graphic_level
->EnabledForActivity
= 0;
924 /* this level can be used for throttling.*/
925 graphic_level
->EnabledForThrottle
= 1;
926 graphic_level
->UpHyst
= data
->current_profile_setting
.sclk_up_hyst
;
927 graphic_level
->DownHyst
= data
->current_profile_setting
.sclk_down_hyst
;
928 graphic_level
->VoltageDownHyst
= 0;
929 graphic_level
->PowerThrottle
= 0;
931 data
->display_timing
.min_clock_in_sr
=
932 hwmgr
->display_config
->min_core_set_clock_in_sr
;
934 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
935 PHM_PlatformCaps_SclkDeepSleep
))
936 graphic_level
->DeepSleepDivId
=
937 smu7_get_sleep_divider_id_from_clock(engine_clock
,
938 data
->display_timing
.min_clock_in_sr
);
940 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
941 graphic_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
944 graphic_level
->MinVddc
= PP_HOST_TO_SMC_UL(graphic_level
->MinVddc
* VOLTAGE_SCALE
);
945 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->MinVddcPhases
);
946 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SclkFrequency
);
947 CONVERT_FROM_HOST_TO_SMC_US(graphic_level
->ActivityLevel
);
948 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CgSpllFuncCntl3
);
949 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CgSpllFuncCntl4
);
950 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SpllSpreadSpectrum
);
951 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SpllSpreadSpectrum2
);
952 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CcPwrDynRm
);
953 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CcPwrDynRm1
);
959 static int iceland_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
961 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
962 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
963 struct smu7_dpm_table
*dpm_table
= &data
->dpm_table
;
964 uint32_t level_array_adress
= smu_data
->smu7_data
.dpm_table_start
+
965 offsetof(SMU71_Discrete_DpmTable
, GraphicsLevel
);
967 uint32_t level_array_size
= sizeof(SMU71_Discrete_GraphicsLevel
) *
968 SMU71_MAX_LEVELS_GRAPHICS
;
970 SMU71_Discrete_GraphicsLevel
*levels
= smu_data
->smc_state_table
.GraphicsLevel
;
973 uint8_t highest_pcie_level_enabled
= 0;
974 uint8_t lowest_pcie_level_enabled
= 0, mid_pcie_level_enabled
= 0;
978 memset(levels
, 0x00, level_array_size
);
980 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
981 result
= iceland_populate_single_graphic_level(hwmgr
,
982 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
983 &(smu_data
->smc_state_table
.GraphicsLevel
[i
]));
987 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
989 smu_data
->smc_state_table
.GraphicsLevel
[i
].DeepSleepDivId
= 0;
992 /* Only enable level 0 for now. */
993 smu_data
->smc_state_table
.GraphicsLevel
[0].EnabledForActivity
= 1;
995 /* set highest level watermark to high */
996 if (dpm_table
->sclk_table
.count
> 1)
997 smu_data
->smc_state_table
.GraphicsLevel
[dpm_table
->sclk_table
.count
-1].DisplayWatermark
=
998 PPSMC_DISPLAY_WATERMARK_HIGH
;
1000 smu_data
->smc_state_table
.GraphicsDpmLevelCount
=
1001 (uint8_t)dpm_table
->sclk_table
.count
;
1002 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
1003 phm_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
1005 while ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1006 (1 << (highest_pcie_level_enabled
+ 1))) != 0) {
1007 highest_pcie_level_enabled
++;
1010 while ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1011 (1 << lowest_pcie_level_enabled
)) == 0) {
1012 lowest_pcie_level_enabled
++;
1015 while ((count
< highest_pcie_level_enabled
) &&
1016 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1017 (1 << (lowest_pcie_level_enabled
+ 1 + count
))) == 0)) {
1021 mid_pcie_level_enabled
= (lowest_pcie_level_enabled
+1+count
) < highest_pcie_level_enabled
?
1022 (lowest_pcie_level_enabled
+1+count
) : highest_pcie_level_enabled
;
1025 /* set pcieDpmLevel to highest_pcie_level_enabled*/
1026 for (i
= 2; i
< dpm_table
->sclk_table
.count
; i
++) {
1027 smu_data
->smc_state_table
.GraphicsLevel
[i
].pcieDpmLevel
= highest_pcie_level_enabled
;
1030 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
1031 smu_data
->smc_state_table
.GraphicsLevel
[0].pcieDpmLevel
= lowest_pcie_level_enabled
;
1033 /* set pcieDpmLevel to mid_pcie_level_enabled*/
1034 smu_data
->smc_state_table
.GraphicsLevel
[1].pcieDpmLevel
= mid_pcie_level_enabled
;
1036 /* level count will send to smc once at init smc table and never change*/
1037 result
= smu7_copy_bytes_to_smc(hwmgr
, level_array_adress
,
1038 (uint8_t *)levels
, (uint32_t)level_array_size
,
1044 static int iceland_calculate_mclk_params(
1045 struct pp_hwmgr
*hwmgr
,
1046 uint32_t memory_clock
,
1047 SMU71_Discrete_MemoryLevel
*mclk
,
1052 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1054 uint32_t dll_cntl
= data
->clock_registers
.vDLL_CNTL
;
1055 uint32_t mclk_pwrmgt_cntl
= data
->clock_registers
.vMCLK_PWRMGT_CNTL
;
1056 uint32_t mpll_ad_func_cntl
= data
->clock_registers
.vMPLL_AD_FUNC_CNTL
;
1057 uint32_t mpll_dq_func_cntl
= data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
;
1058 uint32_t mpll_func_cntl
= data
->clock_registers
.vMPLL_FUNC_CNTL
;
1059 uint32_t mpll_func_cntl_1
= data
->clock_registers
.vMPLL_FUNC_CNTL_1
;
1060 uint32_t mpll_func_cntl_2
= data
->clock_registers
.vMPLL_FUNC_CNTL_2
;
1061 uint32_t mpll_ss1
= data
->clock_registers
.vMPLL_SS1
;
1062 uint32_t mpll_ss2
= data
->clock_registers
.vMPLL_SS2
;
1064 pp_atomctrl_memory_clock_param mpll_param
;
1067 result
= atomctrl_get_memory_pll_dividers_si(hwmgr
,
1068 memory_clock
, &mpll_param
, strobe_mode
);
1069 PP_ASSERT_WITH_CODE(0 == result
,
1070 "Error retrieving Memory Clock Parameters from VBIOS.", return result
);
1072 /* MPLL_FUNC_CNTL setup*/
1073 mpll_func_cntl
= PHM_SET_FIELD(mpll_func_cntl
, MPLL_FUNC_CNTL
, BWCTRL
, mpll_param
.bw_ctrl
);
1075 /* MPLL_FUNC_CNTL_1 setup*/
1076 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1077 MPLL_FUNC_CNTL_1
, CLKF
, mpll_param
.mpll_fb_divider
.cl_kf
);
1078 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1079 MPLL_FUNC_CNTL_1
, CLKFRAC
, mpll_param
.mpll_fb_divider
.clk_frac
);
1080 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1081 MPLL_FUNC_CNTL_1
, VCO_MODE
, mpll_param
.vco_mode
);
1083 /* MPLL_AD_FUNC_CNTL setup*/
1084 mpll_ad_func_cntl
= PHM_SET_FIELD(mpll_ad_func_cntl
,
1085 MPLL_AD_FUNC_CNTL
, YCLK_POST_DIV
, mpll_param
.mpll_post_divider
);
1087 if (data
->is_memory_gddr5
) {
1088 /* MPLL_DQ_FUNC_CNTL setup*/
1089 mpll_dq_func_cntl
= PHM_SET_FIELD(mpll_dq_func_cntl
,
1090 MPLL_DQ_FUNC_CNTL
, YCLK_SEL
, mpll_param
.yclk_sel
);
1091 mpll_dq_func_cntl
= PHM_SET_FIELD(mpll_dq_func_cntl
,
1092 MPLL_DQ_FUNC_CNTL
, YCLK_POST_DIV
, mpll_param
.mpll_post_divider
);
1095 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1096 PHM_PlatformCaps_MemorySpreadSpectrumSupport
)) {
1098 ************************************
1099 Fref = Reference Frequency
1100 NF = Feedback divider ratio
1101 NR = Reference divider ratio
1102 Fnom = Nominal VCO output frequency = Fref * NF / NR
1104 D = Percentage down-spread / 2
1105 Fint = Reference input frequency to PFD = Fref / NR
1106 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1107 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1108 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1109 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1110 *************************************
1112 pp_atomctrl_internal_ss_info ss_info
;
1115 uint32_t reference_clock
= atomctrl_get_mpll_reference_clock(hwmgr
);
1117 /* for GDDR5 for all modes and DDR3 */
1118 if (1 == mpll_param
.qdr
)
1119 freq_nom
= memory_clock
* 4 * (1 << mpll_param
.mpll_post_divider
);
1121 freq_nom
= memory_clock
* 2 * (1 << mpll_param
.mpll_post_divider
);
1123 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1124 tmp
= (freq_nom
/ reference_clock
);
1127 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr
, freq_nom
, &ss_info
)) {
1128 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1129 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1130 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1131 /* = reference_clock * 5 / speed_spectrum_rate */
1132 uint32_t clks
= reference_clock
* 5 / ss_info
.speed_spectrum_rate
;
1134 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1135 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1137 (uint32_t)((((131 * ss_info
.speed_spectrum_percentage
*
1138 ss_info
.speed_spectrum_rate
) / 100) * tmp
) / freq_nom
);
1140 mpll_ss1
= PHM_SET_FIELD(mpll_ss1
, MPLL_SS1
, CLKV
, clkv
);
1141 mpll_ss2
= PHM_SET_FIELD(mpll_ss2
, MPLL_SS2
, CLKS
, clks
);
1145 /* MCLK_PWRMGT_CNTL setup */
1146 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1147 MCLK_PWRMGT_CNTL
, DLL_SPEED
, mpll_param
.dll_speed
);
1148 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1149 MCLK_PWRMGT_CNTL
, MRDCK0_PDNB
, dllStateOn
);
1150 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1151 MCLK_PWRMGT_CNTL
, MRDCK1_PDNB
, dllStateOn
);
1154 /* Save the result data to outpupt memory level structure */
1155 mclk
->MclkFrequency
= memory_clock
;
1156 mclk
->MpllFuncCntl
= mpll_func_cntl
;
1157 mclk
->MpllFuncCntl_1
= mpll_func_cntl_1
;
1158 mclk
->MpllFuncCntl_2
= mpll_func_cntl_2
;
1159 mclk
->MpllAdFuncCntl
= mpll_ad_func_cntl
;
1160 mclk
->MpllDqFuncCntl
= mpll_dq_func_cntl
;
1161 mclk
->MclkPwrmgtCntl
= mclk_pwrmgt_cntl
;
1162 mclk
->DllCntl
= dll_cntl
;
1163 mclk
->MpllSs1
= mpll_ss1
;
1164 mclk
->MpllSs2
= mpll_ss2
;
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock
,
1172 uint8_t mc_para_index
;
1175 if (memory_clock
< 12500) {
1176 mc_para_index
= 0x00;
1177 } else if (memory_clock
> 47500) {
1178 mc_para_index
= 0x0f;
1180 mc_para_index
= (uint8_t)((memory_clock
- 10000) / 2500);
1183 if (memory_clock
< 65000) {
1184 mc_para_index
= 0x00;
1185 } else if (memory_clock
> 135000) {
1186 mc_para_index
= 0x0f;
1188 mc_para_index
= (uint8_t)((memory_clock
- 60000) / 5000);
1192 return mc_para_index
;
1195 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock
)
1197 uint8_t mc_para_index
;
1199 if (memory_clock
< 10000) {
1201 } else if (memory_clock
>= 80000) {
1202 mc_para_index
= 0x0f;
1204 mc_para_index
= (uint8_t)((memory_clock
- 10000) / 5000 + 1);
1207 return mc_para_index
;
1210 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr
*hwmgr
, const struct phm_phase_shedding_limits_table
*pl
,
1211 uint32_t memory_clock
, uint32_t *p_shed
)
1217 for (i
= 0; i
< pl
->count
; i
++) {
1218 if (memory_clock
< pl
->entries
[i
].Mclk
) {
1227 static int iceland_populate_single_memory_level(
1228 struct pp_hwmgr
*hwmgr
,
1229 uint32_t memory_clock
,
1230 SMU71_Discrete_MemoryLevel
*memory_level
1233 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1236 uint32_t mclk_edc_wr_enable_threshold
= 40000;
1237 uint32_t mclk_edc_enable_threshold
= 40000;
1238 uint32_t mclk_strobe_mode_threshold
= 40000;
1240 if (hwmgr
->dyn_state
.vddc_dependency_on_mclk
!= NULL
) {
1241 result
= iceland_get_dependency_volt_by_clk(hwmgr
,
1242 hwmgr
->dyn_state
.vddc_dependency_on_mclk
, memory_clock
, &memory_level
->MinVddc
);
1243 PP_ASSERT_WITH_CODE((0 == result
),
1244 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result
);
1247 if (data
->vddci_control
== SMU7_VOLTAGE_CONTROL_NONE
) {
1248 memory_level
->MinVddci
= memory_level
->MinVddc
;
1249 } else if (NULL
!= hwmgr
->dyn_state
.vddci_dependency_on_mclk
) {
1250 result
= iceland_get_dependency_volt_by_clk(hwmgr
,
1251 hwmgr
->dyn_state
.vddci_dependency_on_mclk
,
1253 &memory_level
->MinVddci
);
1254 PP_ASSERT_WITH_CODE((0 == result
),
1255 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result
);
1258 memory_level
->MinVddcPhases
= 1;
1260 if (data
->vddc_phase_shed_control
) {
1261 iceland_populate_phase_value_based_on_mclk(hwmgr
, hwmgr
->dyn_state
.vddc_phase_shed_limits_table
,
1262 memory_clock
, &memory_level
->MinVddcPhases
);
1265 memory_level
->EnabledForThrottle
= 1;
1266 memory_level
->EnabledForActivity
= 0;
1267 memory_level
->UpHyst
= data
->current_profile_setting
.mclk_up_hyst
;
1268 memory_level
->DownHyst
= data
->current_profile_setting
.mclk_down_hyst
;
1269 memory_level
->VoltageDownHyst
= 0;
1271 /* Indicates maximum activity level for this performance level.*/
1272 memory_level
->ActivityLevel
= data
->current_profile_setting
.mclk_activity
;
1273 memory_level
->StutterEnable
= 0;
1274 memory_level
->StrobeEnable
= 0;
1275 memory_level
->EdcReadEnable
= 0;
1276 memory_level
->EdcWriteEnable
= 0;
1277 memory_level
->RttEnable
= 0;
1279 /* default set to low watermark. Highest level will be set to high later.*/
1280 memory_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1282 data
->display_timing
.num_existing_displays
= hwmgr
->display_config
->num_display
;
1284 /* stutter mode not support on iceland */
1286 /* decide strobe mode*/
1287 memory_level
->StrobeEnable
= (mclk_strobe_mode_threshold
!= 0) &&
1288 (memory_clock
<= mclk_strobe_mode_threshold
);
1290 /* decide EDC mode and memory clock ratio*/
1291 if (data
->is_memory_gddr5
) {
1292 memory_level
->StrobeRatio
= iceland_get_mclk_frequency_ratio(memory_clock
,
1293 memory_level
->StrobeEnable
);
1295 if ((mclk_edc_enable_threshold
!= 0) &&
1296 (memory_clock
> mclk_edc_enable_threshold
)) {
1297 memory_level
->EdcReadEnable
= 1;
1300 if ((mclk_edc_wr_enable_threshold
!= 0) &&
1301 (memory_clock
> mclk_edc_wr_enable_threshold
)) {
1302 memory_level
->EdcWriteEnable
= 1;
1305 if (memory_level
->StrobeEnable
) {
1306 if (iceland_get_mclk_frequency_ratio(memory_clock
, 1) >=
1307 ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC7
) >> 16) & 0xf))
1308 dll_state_on
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC5
) >> 1) & 0x1) ? 1 : 0;
1310 dll_state_on
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC6
) >> 1) & 0x1) ? 1 : 0;
1312 dll_state_on
= data
->dll_default_on
;
1314 memory_level
->StrobeRatio
=
1315 iceland_get_ddr3_mclk_frequency_ratio(memory_clock
);
1316 dll_state_on
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC5
) >> 1) & 0x1) ? 1 : 0;
1319 result
= iceland_calculate_mclk_params(hwmgr
,
1320 memory_clock
, memory_level
, memory_level
->StrobeEnable
, dll_state_on
);
1323 memory_level
->MinVddc
= PP_HOST_TO_SMC_UL(memory_level
->MinVddc
* VOLTAGE_SCALE
);
1324 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MinVddcPhases
);
1325 memory_level
->MinVddci
= PP_HOST_TO_SMC_UL(memory_level
->MinVddci
* VOLTAGE_SCALE
);
1326 memory_level
->MinMvdd
= PP_HOST_TO_SMC_UL(memory_level
->MinMvdd
* VOLTAGE_SCALE
);
1327 /* MCLK frequency in units of 10KHz*/
1328 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MclkFrequency
);
1329 /* Indicates maximum activity level for this performance level.*/
1330 CONVERT_FROM_HOST_TO_SMC_US(memory_level
->ActivityLevel
);
1331 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl
);
1332 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl_1
);
1333 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl_2
);
1334 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllAdFuncCntl
);
1335 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllDqFuncCntl
);
1336 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MclkPwrmgtCntl
);
1337 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->DllCntl
);
1338 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllSs1
);
1339 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllSs2
);
1345 static int iceland_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
1347 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1348 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1349 struct smu7_dpm_table
*dpm_table
= &data
->dpm_table
;
1352 /* populate MCLK dpm table to SMU7 */
1353 uint32_t level_array_adress
= smu_data
->smu7_data
.dpm_table_start
+ offsetof(SMU71_Discrete_DpmTable
, MemoryLevel
);
1354 uint32_t level_array_size
= sizeof(SMU71_Discrete_MemoryLevel
) * SMU71_MAX_LEVELS_MEMORY
;
1355 SMU71_Discrete_MemoryLevel
*levels
= smu_data
->smc_state_table
.MemoryLevel
;
1358 memset(levels
, 0x00, level_array_size
);
1360 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
1361 PP_ASSERT_WITH_CODE((0 != dpm_table
->mclk_table
.dpm_levels
[i
].value
),
1362 "can not populate memory level as memory clock is zero", return -EINVAL
);
1363 result
= iceland_populate_single_memory_level(hwmgr
, dpm_table
->mclk_table
.dpm_levels
[i
].value
,
1364 &(smu_data
->smc_state_table
.MemoryLevel
[i
]));
1370 /* Only enable level 0 for now.*/
1371 smu_data
->smc_state_table
.MemoryLevel
[0].EnabledForActivity
= 1;
1374 * in order to prevent MC activity from stutter mode to push DPM up.
1375 * the UVD change complements this by putting the MCLK in a higher state
1376 * by default such that we are not effected by up threshold or and MCLK DPM latency.
1378 smu_data
->smc_state_table
.MemoryLevel
[0].ActivityLevel
= 0x1F;
1379 CONVERT_FROM_HOST_TO_SMC_US(smu_data
->smc_state_table
.MemoryLevel
[0].ActivityLevel
);
1381 smu_data
->smc_state_table
.MemoryDpmLevelCount
= (uint8_t)dpm_table
->mclk_table
.count
;
1382 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
= phm_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
1383 /* set highest level watermark to high*/
1384 smu_data
->smc_state_table
.MemoryLevel
[dpm_table
->mclk_table
.count
-1].DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_HIGH
;
1386 /* level count will send to smc once at init smc table and never change*/
1387 result
= smu7_copy_bytes_to_smc(hwmgr
,
1388 level_array_adress
, (uint8_t *)levels
, (uint32_t)level_array_size
,
1394 static int iceland_populate_mvdd_value(struct pp_hwmgr
*hwmgr
, uint32_t mclk
,
1395 SMU71_Discrete_VoltageLevel
*voltage
)
1397 const struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1401 if (SMU7_VOLTAGE_CONTROL_NONE
!= data
->mvdd_control
) {
1402 /* find mvdd value which clock is more than request */
1403 for (i
= 0; i
< hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->count
; i
++) {
1404 if (mclk
<= hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->entries
[i
].clk
) {
1405 /* Always round to higher voltage. */
1406 voltage
->Voltage
= data
->mvdd_voltage_table
.entries
[i
].value
;
1411 PP_ASSERT_WITH_CODE(i
< hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->count
,
1412 "MVDD Voltage is outside the supported range.", return -EINVAL
);
1421 static int iceland_populate_smc_acpi_level(struct pp_hwmgr
*hwmgr
,
1422 SMU71_Discrete_DpmTable
*table
)
1425 const struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1426 struct pp_atomctrl_clock_dividers_vi dividers
;
1427 uint32_t vddc_phase_shed_control
= 0;
1429 SMU71_Discrete_VoltageLevel voltage_level
;
1430 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
1431 uint32_t spll_func_cntl_2
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
;
1432 uint32_t dll_cntl
= data
->clock_registers
.vDLL_CNTL
;
1433 uint32_t mclk_pwrmgt_cntl
= data
->clock_registers
.vMCLK_PWRMGT_CNTL
;
1436 /* The ACPI state should not do DPM on DC (or ever).*/
1437 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
1439 if (data
->acpi_vddc
)
1440 table
->ACPILevel
.MinVddc
= PP_HOST_TO_SMC_UL(data
->acpi_vddc
* VOLTAGE_SCALE
);
1442 table
->ACPILevel
.MinVddc
= PP_HOST_TO_SMC_UL(data
->min_vddc_in_pptable
* VOLTAGE_SCALE
);
1444 table
->ACPILevel
.MinVddcPhases
= vddc_phase_shed_control
? 0 : 1;
1445 /* assign zero for now*/
1446 table
->ACPILevel
.SclkFrequency
= atomctrl_get_reference_clock(hwmgr
);
1448 /* get the engine clock dividers for this clock value*/
1449 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
,
1450 table
->ACPILevel
.SclkFrequency
, ÷rs
);
1452 PP_ASSERT_WITH_CODE(result
== 0,
1453 "Error retrieving Engine Clock dividers from VBIOS.", return result
);
1455 /* divider ID for required SCLK*/
1456 table
->ACPILevel
.SclkDid
= (uint8_t)dividers
.pll_post_divider
;
1457 table
->ACPILevel
.DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1458 table
->ACPILevel
.DeepSleepDivId
= 0;
1460 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
1461 CG_SPLL_FUNC_CNTL
, SPLL_PWRON
, 0);
1462 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
1463 CG_SPLL_FUNC_CNTL
, SPLL_RESET
, 1);
1464 spll_func_cntl_2
= PHM_SET_FIELD(spll_func_cntl_2
,
1465 CG_SPLL_FUNC_CNTL_2
, SCLK_MUX_SEL
, 4);
1467 table
->ACPILevel
.CgSpllFuncCntl
= spll_func_cntl
;
1468 table
->ACPILevel
.CgSpllFuncCntl2
= spll_func_cntl_2
;
1469 table
->ACPILevel
.CgSpllFuncCntl3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
1470 table
->ACPILevel
.CgSpllFuncCntl4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
1471 table
->ACPILevel
.SpllSpreadSpectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
1472 table
->ACPILevel
.SpllSpreadSpectrum2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
1473 table
->ACPILevel
.CcPwrDynRm
= 0;
1474 table
->ACPILevel
.CcPwrDynRm1
= 0;
1477 /* For various features to be enabled/disabled while this level is active.*/
1478 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.Flags
);
1479 /* SCLK frequency in units of 10KHz*/
1480 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SclkFrequency
);
1481 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl
);
1482 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl2
);
1483 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl3
);
1484 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl4
);
1485 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum
);
1486 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum2
);
1487 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm
);
1488 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm1
);
1490 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1491 table
->MemoryACPILevel
.MinVddc
= table
->ACPILevel
.MinVddc
;
1492 table
->MemoryACPILevel
.MinVddcPhases
= table
->ACPILevel
.MinVddcPhases
;
1494 if (SMU7_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1495 table
->MemoryACPILevel
.MinVddci
= table
->MemoryACPILevel
.MinVddc
;
1497 if (data
->acpi_vddci
!= 0)
1498 table
->MemoryACPILevel
.MinVddci
= PP_HOST_TO_SMC_UL(data
->acpi_vddci
* VOLTAGE_SCALE
);
1500 table
->MemoryACPILevel
.MinVddci
= PP_HOST_TO_SMC_UL(data
->min_vddci_in_pptable
* VOLTAGE_SCALE
);
1503 if (0 == iceland_populate_mvdd_value(hwmgr
, 0, &voltage_level
))
1504 table
->MemoryACPILevel
.MinMvdd
=
1505 PP_HOST_TO_SMC_UL(voltage_level
.Voltage
* VOLTAGE_SCALE
);
1507 table
->MemoryACPILevel
.MinMvdd
= 0;
1509 /* Force reset on DLL*/
1510 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1511 MCLK_PWRMGT_CNTL
, MRDCK0_RESET
, 0x1);
1512 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1513 MCLK_PWRMGT_CNTL
, MRDCK1_RESET
, 0x1);
1515 /* Disable DLL in ACPIState*/
1516 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1517 MCLK_PWRMGT_CNTL
, MRDCK0_PDNB
, 0);
1518 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1519 MCLK_PWRMGT_CNTL
, MRDCK1_PDNB
, 0);
1521 /* Enable DLL bypass signal*/
1522 dll_cntl
= PHM_SET_FIELD(dll_cntl
,
1523 DLL_CNTL
, MRDCK0_BYPASS
, 0);
1524 dll_cntl
= PHM_SET_FIELD(dll_cntl
,
1525 DLL_CNTL
, MRDCK1_BYPASS
, 0);
1527 table
->MemoryACPILevel
.DllCntl
=
1528 PP_HOST_TO_SMC_UL(dll_cntl
);
1529 table
->MemoryACPILevel
.MclkPwrmgtCntl
=
1530 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl
);
1531 table
->MemoryACPILevel
.MpllAdFuncCntl
=
1532 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_AD_FUNC_CNTL
);
1533 table
->MemoryACPILevel
.MpllDqFuncCntl
=
1534 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
);
1535 table
->MemoryACPILevel
.MpllFuncCntl
=
1536 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL
);
1537 table
->MemoryACPILevel
.MpllFuncCntl_1
=
1538 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL_1
);
1539 table
->MemoryACPILevel
.MpllFuncCntl_2
=
1540 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL_2
);
1541 table
->MemoryACPILevel
.MpllSs1
=
1542 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_SS1
);
1543 table
->MemoryACPILevel
.MpllSs2
=
1544 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_SS2
);
1546 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
1547 table
->MemoryACPILevel
.EnabledForActivity
= 0;
1548 table
->MemoryACPILevel
.UpHyst
= 0;
1549 table
->MemoryACPILevel
.DownHyst
= 100;
1550 table
->MemoryACPILevel
.VoltageDownHyst
= 0;
1551 /* Indicates maximum activity level for this performance level.*/
1552 table
->MemoryACPILevel
.ActivityLevel
= PP_HOST_TO_SMC_US(data
->current_profile_setting
.mclk_activity
);
1554 table
->MemoryACPILevel
.StutterEnable
= 0;
1555 table
->MemoryACPILevel
.StrobeEnable
= 0;
1556 table
->MemoryACPILevel
.EdcReadEnable
= 0;
1557 table
->MemoryACPILevel
.EdcWriteEnable
= 0;
1558 table
->MemoryACPILevel
.RttEnable
= 0;
1563 static int iceland_populate_smc_uvd_level(struct pp_hwmgr
*hwmgr
,
1564 SMU71_Discrete_DpmTable
*table
)
1569 static int iceland_populate_smc_vce_level(struct pp_hwmgr
*hwmgr
,
1570 SMU71_Discrete_DpmTable
*table
)
1575 static int iceland_populate_smc_acp_level(struct pp_hwmgr
*hwmgr
,
1576 SMU71_Discrete_DpmTable
*table
)
1581 static int iceland_populate_memory_timing_parameters(
1582 struct pp_hwmgr
*hwmgr
,
1583 uint32_t engine_clock
,
1584 uint32_t memory_clock
,
1585 struct SMU71_Discrete_MCArbDramTimingTableEntry
*arb_regs
1588 uint32_t dramTiming
;
1589 uint32_t dramTiming2
;
1593 result
= atomctrl_set_engine_dram_timings_rv770(hwmgr
,
1594 engine_clock
, memory_clock
);
1596 PP_ASSERT_WITH_CODE(result
== 0,
1597 "Error calling VBIOS to set DRAM_TIMING.", return result
);
1599 dramTiming
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
1600 dramTiming2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
1601 burstTime
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
1603 arb_regs
->McArbDramTiming
= PP_HOST_TO_SMC_UL(dramTiming
);
1604 arb_regs
->McArbDramTiming2
= PP_HOST_TO_SMC_UL(dramTiming2
);
1605 arb_regs
->McArbBurstTime
= (uint8_t)burstTime
;
1610 static int iceland_program_memory_timing_parameters(struct pp_hwmgr
*hwmgr
)
1612 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1613 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1615 SMU71_Discrete_MCArbDramTimingTable arb_regs
;
1618 memset(&arb_regs
, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable
));
1620 for (i
= 0; i
< data
->dpm_table
.sclk_table
.count
; i
++) {
1621 for (j
= 0; j
< data
->dpm_table
.mclk_table
.count
; j
++) {
1622 result
= iceland_populate_memory_timing_parameters
1623 (hwmgr
, data
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
1624 data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
1625 &arb_regs
.entries
[i
][j
]);
1634 result
= smu7_copy_bytes_to_smc(
1636 smu_data
->smu7_data
.arb_table_start
,
1637 (uint8_t *)&arb_regs
,
1638 sizeof(SMU71_Discrete_MCArbDramTimingTable
),
1646 static int iceland_populate_smc_boot_level(struct pp_hwmgr
*hwmgr
,
1647 SMU71_Discrete_DpmTable
*table
)
1650 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1651 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1652 table
->GraphicsBootLevel
= 0;
1653 table
->MemoryBootLevel
= 0;
1655 /* find boot level from dpm table*/
1656 result
= phm_find_boot_level(&(data
->dpm_table
.sclk_table
),
1657 data
->vbios_boot_state
.sclk_bootup_value
,
1658 (uint32_t *)&(smu_data
->smc_state_table
.GraphicsBootLevel
));
1661 smu_data
->smc_state_table
.GraphicsBootLevel
= 0;
1662 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1666 result
= phm_find_boot_level(&(data
->dpm_table
.mclk_table
),
1667 data
->vbios_boot_state
.mclk_bootup_value
,
1668 (uint32_t *)&(smu_data
->smc_state_table
.MemoryBootLevel
));
1671 smu_data
->smc_state_table
.MemoryBootLevel
= 0;
1672 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1676 table
->BootVddc
= data
->vbios_boot_state
.vddc_bootup_value
;
1677 if (SMU7_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1678 table
->BootVddci
= table
->BootVddc
;
1680 table
->BootVddci
= data
->vbios_boot_state
.vddci_bootup_value
;
1682 table
->BootMVdd
= data
->vbios_boot_state
.mvdd_bootup_value
;
1687 static int iceland_populate_mc_reg_address(struct pp_hwmgr
*hwmgr
,
1688 SMU71_Discrete_MCRegisters
*mc_reg_table
)
1690 const struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)hwmgr
->smu_backend
;
1694 for (i
= 0, j
= 0; j
< smu_data
->mc_reg_table
.last
; j
++) {
1695 if (smu_data
->mc_reg_table
.validflag
& 1<<j
) {
1696 PP_ASSERT_WITH_CODE(i
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
,
1697 "Index of mc_reg_table->address[] array out of boundary", return -EINVAL
);
1698 mc_reg_table
->address
[i
].s0
=
1699 PP_HOST_TO_SMC_US(smu_data
->mc_reg_table
.mc_reg_address
[j
].s0
);
1700 mc_reg_table
->address
[i
].s1
=
1701 PP_HOST_TO_SMC_US(smu_data
->mc_reg_table
.mc_reg_address
[j
].s1
);
1706 mc_reg_table
->last
= (uint8_t)i
;
1711 /*convert register values from driver to SMC format */
1712 static void iceland_convert_mc_registers(
1713 const struct iceland_mc_reg_entry
*entry
,
1714 SMU71_Discrete_MCRegisterSet
*data
,
1715 uint32_t num_entries
, uint32_t valid_flag
)
1719 for (i
= 0, j
= 0; j
< num_entries
; j
++) {
1720 if (valid_flag
& 1<<j
) {
1721 data
->value
[i
] = PP_HOST_TO_SMC_UL(entry
->mc_data
[j
]);
1727 static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr
*hwmgr
,
1728 const uint32_t memory_clock
,
1729 SMU71_Discrete_MCRegisterSet
*mc_reg_table_data
1732 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1735 for (i
= 0; i
< smu_data
->mc_reg_table
.num_entries
; i
++) {
1737 smu_data
->mc_reg_table
.mc_reg_table_entry
[i
].mclk_max
) {
1742 if ((i
== smu_data
->mc_reg_table
.num_entries
) && (i
> 0))
1745 iceland_convert_mc_registers(&smu_data
->mc_reg_table
.mc_reg_table_entry
[i
],
1746 mc_reg_table_data
, smu_data
->mc_reg_table
.last
,
1747 smu_data
->mc_reg_table
.validflag
);
1752 static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr
*hwmgr
,
1753 SMU71_Discrete_MCRegisters
*mc_regs
)
1756 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1760 for (i
= 0; i
< data
->dpm_table
.mclk_table
.count
; i
++) {
1761 res
= iceland_convert_mc_reg_table_entry_to_smc(
1763 data
->dpm_table
.mclk_table
.dpm_levels
[i
].value
,
1774 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr
*hwmgr
)
1776 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1777 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1781 if (0 == (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
))
1785 memset(&smu_data
->mc_regs
, 0, sizeof(SMU71_Discrete_MCRegisters
));
1787 result
= iceland_convert_mc_reg_table_to_smc(hwmgr
, &(smu_data
->mc_regs
));
1793 address
= smu_data
->smu7_data
.mc_reg_table_start
+ (uint32_t)offsetof(SMU71_Discrete_MCRegisters
, data
[0]);
1795 return smu7_copy_bytes_to_smc(hwmgr
, address
,
1796 (uint8_t *)&smu_data
->mc_regs
.data
[0],
1797 sizeof(SMU71_Discrete_MCRegisterSet
) * data
->dpm_table
.mclk_table
.count
,
1801 static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr
*hwmgr
)
1804 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1806 memset(&smu_data
->mc_regs
, 0x00, sizeof(SMU71_Discrete_MCRegisters
));
1807 result
= iceland_populate_mc_reg_address(hwmgr
, &(smu_data
->mc_regs
));
1808 PP_ASSERT_WITH_CODE(0 == result
,
1809 "Failed to initialize MCRegTable for the MC register addresses!", return result
;);
1811 result
= iceland_convert_mc_reg_table_to_smc(hwmgr
, &smu_data
->mc_regs
);
1812 PP_ASSERT_WITH_CODE(0 == result
,
1813 "Failed to initialize MCRegTable for driver state!", return result
;);
1815 return smu7_copy_bytes_to_smc(hwmgr
, smu_data
->smu7_data
.mc_reg_table_start
,
1816 (uint8_t *)&smu_data
->mc_regs
, sizeof(SMU71_Discrete_MCRegisters
), SMC_RAM_END
);
1819 static int iceland_populate_smc_initial_state(struct pp_hwmgr
*hwmgr
)
1821 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1822 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1823 uint8_t count
, level
;
1825 count
= (uint8_t)(hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
);
1827 for (level
= 0; level
< count
; level
++) {
1828 if (hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[level
].clk
1829 >= data
->vbios_boot_state
.sclk_bootup_value
) {
1830 smu_data
->smc_state_table
.GraphicsBootLevel
= level
;
1835 count
= (uint8_t)(hwmgr
->dyn_state
.vddc_dependency_on_mclk
->count
);
1837 for (level
= 0; level
< count
; level
++) {
1838 if (hwmgr
->dyn_state
.vddc_dependency_on_mclk
->entries
[level
].clk
1839 >= data
->vbios_boot_state
.mclk_bootup_value
) {
1840 smu_data
->smc_state_table
.MemoryBootLevel
= level
;
1848 static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr
*hwmgr
)
1850 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1851 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1852 const struct iceland_pt_defaults
*defaults
= smu_data
->power_tune_defaults
;
1853 SMU71_Discrete_DpmTable
*dpm_table
= &(smu_data
->smc_state_table
);
1854 struct phm_cac_tdp_table
*cac_dtp_table
= hwmgr
->dyn_state
.cac_dtp_table
;
1855 struct phm_ppm_table
*ppm
= hwmgr
->dyn_state
.ppm_parameter_table
;
1856 const uint16_t *def1
, *def2
;
1861 * TDP number of fraction bits are changed from 8 to 7 for Iceland
1862 * as requested by SMC team
1865 dpm_table
->DefaultTdp
= PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table
->usTDP
* 256));
1866 dpm_table
->TargetTdp
= PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table
->usConfigurableTDP
* 256));
1869 dpm_table
->DTETjOffset
= 0;
1871 dpm_table
->GpuTjMax
= (uint8_t)(data
->thermal_temp_setting
.temperature_high
/ PP_TEMPERATURE_UNITS_PER_CENTIGRADES
);
1872 dpm_table
->GpuTjHyst
= 8;
1874 dpm_table
->DTEAmbientTempBase
= defaults
->dte_ambient_temp_base
;
1876 /* The following are for new Iceland Multi-input fan/thermal control */
1878 dpm_table
->PPM_PkgPwrLimit
= (uint16_t)ppm
->dgpu_tdp
* 256 / 1000;
1879 dpm_table
->PPM_TemperatureLimit
= (uint16_t)ppm
->tj_max
* 256;
1881 dpm_table
->PPM_PkgPwrLimit
= 0;
1882 dpm_table
->PPM_TemperatureLimit
= 0;
1885 CONVERT_FROM_HOST_TO_SMC_US(dpm_table
->PPM_PkgPwrLimit
);
1886 CONVERT_FROM_HOST_TO_SMC_US(dpm_table
->PPM_TemperatureLimit
);
1888 dpm_table
->BAPM_TEMP_GRADIENT
= PP_HOST_TO_SMC_UL(defaults
->bapm_temp_gradient
);
1889 def1
= defaults
->bapmti_r
;
1890 def2
= defaults
->bapmti_rc
;
1892 for (i
= 0; i
< SMU71_DTE_ITERATIONS
; i
++) {
1893 for (j
= 0; j
< SMU71_DTE_SOURCES
; j
++) {
1894 for (k
= 0; k
< SMU71_DTE_SINKS
; k
++) {
1895 dpm_table
->BAPMTI_R
[i
][j
][k
] = PP_HOST_TO_SMC_US(*def1
);
1896 dpm_table
->BAPMTI_RC
[i
][j
][k
] = PP_HOST_TO_SMC_US(*def2
);
1906 static int iceland_populate_smc_svi2_config(struct pp_hwmgr
*hwmgr
,
1907 SMU71_Discrete_DpmTable
*tab
)
1909 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1911 if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
)
1912 tab
->SVI2Enable
|= VDDC_ON_SVI2
;
1914 if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
)
1915 tab
->SVI2Enable
|= VDDCI_ON_SVI2
;
1917 tab
->MergedVddci
= 1;
1919 if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
)
1920 tab
->SVI2Enable
|= MVDD_ON_SVI2
;
1922 PP_ASSERT_WITH_CODE(tab
->SVI2Enable
!= (VDDC_ON_SVI2
| VDDCI_ON_SVI2
| MVDD_ON_SVI2
) &&
1923 (tab
->SVI2Enable
& VDDC_ON_SVI2
), "SVI2 domain configuration is incorrect!", return -EINVAL
);
1928 static int iceland_init_smc_table(struct pp_hwmgr
*hwmgr
)
1931 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1932 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
1933 SMU71_Discrete_DpmTable
*table
= &(smu_data
->smc_state_table
);
1936 iceland_initialize_power_tune_defaults(hwmgr
);
1937 memset(&(smu_data
->smc_state_table
), 0x00, sizeof(smu_data
->smc_state_table
));
1939 if (SMU7_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
) {
1940 iceland_populate_smc_voltage_tables(hwmgr
, table
);
1943 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1944 PHM_PlatformCaps_AutomaticDCTransition
))
1945 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
1948 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1949 PHM_PlatformCaps_StepVddc
))
1950 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
1952 if (data
->is_memory_gddr5
)
1953 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
1956 if (data
->ulv_supported
) {
1957 result
= iceland_populate_ulv_state(hwmgr
, &(smu_data
->ulv_setting
));
1958 PP_ASSERT_WITH_CODE(0 == result
,
1959 "Failed to initialize ULV state!", return result
;);
1961 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1962 ixCG_ULV_PARAMETER
, 0x40035);
1965 result
= iceland_populate_smc_link_level(hwmgr
, table
);
1966 PP_ASSERT_WITH_CODE(0 == result
,
1967 "Failed to initialize Link Level!", return result
;);
1969 result
= iceland_populate_all_graphic_levels(hwmgr
);
1970 PP_ASSERT_WITH_CODE(0 == result
,
1971 "Failed to initialize Graphics Level!", return result
;);
1973 result
= iceland_populate_all_memory_levels(hwmgr
);
1974 PP_ASSERT_WITH_CODE(0 == result
,
1975 "Failed to initialize Memory Level!", return result
;);
1977 result
= iceland_populate_smc_acpi_level(hwmgr
, table
);
1978 PP_ASSERT_WITH_CODE(0 == result
,
1979 "Failed to initialize ACPI Level!", return result
;);
1981 result
= iceland_populate_smc_vce_level(hwmgr
, table
);
1982 PP_ASSERT_WITH_CODE(0 == result
,
1983 "Failed to initialize VCE Level!", return result
;);
1985 result
= iceland_populate_smc_acp_level(hwmgr
, table
);
1986 PP_ASSERT_WITH_CODE(0 == result
,
1987 "Failed to initialize ACP Level!", return result
;);
1989 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
1990 /* need to populate the ARB settings for the initial state. */
1991 result
= iceland_program_memory_timing_parameters(hwmgr
);
1992 PP_ASSERT_WITH_CODE(0 == result
,
1993 "Failed to Write ARB settings for the initial state.", return result
;);
1995 result
= iceland_populate_smc_uvd_level(hwmgr
, table
);
1996 PP_ASSERT_WITH_CODE(0 == result
,
1997 "Failed to initialize UVD Level!", return result
;);
1999 table
->GraphicsBootLevel
= 0;
2000 table
->MemoryBootLevel
= 0;
2002 result
= iceland_populate_smc_boot_level(hwmgr
, table
);
2003 PP_ASSERT_WITH_CODE(0 == result
,
2004 "Failed to initialize Boot Level!", return result
;);
2006 result
= iceland_populate_smc_initial_state(hwmgr
);
2007 PP_ASSERT_WITH_CODE(0 == result
, "Failed to initialize Boot State!", return result
);
2009 result
= iceland_populate_bapm_parameters_in_dpm_table(hwmgr
);
2010 PP_ASSERT_WITH_CODE(0 == result
, "Failed to populate BAPM Parameters!", return result
);
2012 table
->GraphicsVoltageChangeEnable
= 1;
2013 table
->GraphicsThermThrottleEnable
= 1;
2014 table
->GraphicsInterval
= 1;
2015 table
->VoltageInterval
= 1;
2016 table
->ThermalInterval
= 1;
2018 table
->TemperatureLimitHigh
=
2019 (data
->thermal_temp_setting
.temperature_high
*
2020 SMU7_Q88_FORMAT_CONVERSION_UNIT
) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES
;
2021 table
->TemperatureLimitLow
=
2022 (data
->thermal_temp_setting
.temperature_low
*
2023 SMU7_Q88_FORMAT_CONVERSION_UNIT
) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES
;
2025 table
->MemoryVoltageChangeEnable
= 1;
2026 table
->MemoryInterval
= 1;
2027 table
->VoltageResponseTime
= 0;
2028 table
->PhaseResponseTime
= 0;
2029 table
->MemoryThermThrottleEnable
= 1;
2030 table
->PCIeBootLinkLevel
= 0;
2031 table
->PCIeGenInterval
= 1;
2033 result
= iceland_populate_smc_svi2_config(hwmgr
, table
);
2034 PP_ASSERT_WITH_CODE(0 == result
,
2035 "Failed to populate SVI2 setting!", return result
);
2037 table
->ThermGpio
= 17;
2038 table
->SclkStepSize
= 0x4000;
2040 CONVERT_FROM_HOST_TO_SMC_UL(table
->SystemFlags
);
2041 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddcVid
);
2042 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddcPhase
);
2043 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddciVid
);
2044 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskMvddVid
);
2045 CONVERT_FROM_HOST_TO_SMC_UL(table
->SclkStepSize
);
2046 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitHigh
);
2047 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitLow
);
2048 CONVERT_FROM_HOST_TO_SMC_US(table
->VoltageResponseTime
);
2049 CONVERT_FROM_HOST_TO_SMC_US(table
->PhaseResponseTime
);
2051 table
->BootVddc
= PP_HOST_TO_SMC_US(table
->BootVddc
* VOLTAGE_SCALE
);
2052 table
->BootVddci
= PP_HOST_TO_SMC_US(table
->BootVddci
* VOLTAGE_SCALE
);
2053 table
->BootMVdd
= PP_HOST_TO_SMC_US(table
->BootMVdd
* VOLTAGE_SCALE
);
2055 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2056 result
= smu7_copy_bytes_to_smc(hwmgr
, smu_data
->smu7_data
.dpm_table_start
+
2057 offsetof(SMU71_Discrete_DpmTable
, SystemFlags
),
2058 (uint8_t *)&(table
->SystemFlags
),
2059 sizeof(SMU71_Discrete_DpmTable
)-3 * sizeof(SMU71_PIDController
),
2062 PP_ASSERT_WITH_CODE(0 == result
,
2063 "Failed to upload dpm data to SMC memory!", return result
;);
2065 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2066 result
= smu7_copy_bytes_to_smc(hwmgr
,
2067 smu_data
->smu7_data
.ulv_setting_starts
,
2068 (uint8_t *)&(smu_data
->ulv_setting
),
2069 sizeof(SMU71_Discrete_Ulv
),
2073 result
= iceland_populate_initial_mc_reg_table(hwmgr
);
2074 PP_ASSERT_WITH_CODE((0 == result
),
2075 "Failed to populate initialize MC Reg table!", return result
);
2077 result
= iceland_populate_pm_fuses(hwmgr
);
2078 PP_ASSERT_WITH_CODE(0 == result
,
2079 "Failed to populate PM fuses to SMC memory!", return result
);
2084 int iceland_thermal_setup_fan_table(struct pp_hwmgr
*hwmgr
)
2086 struct smu7_smumgr
*smu7_data
= (struct smu7_smumgr
*)(hwmgr
->smu_backend
);
2087 SMU71_Discrete_FanTable fan_table
= { FDO_MODE_HARDWARE
};
2089 uint32_t t_diff1
, t_diff2
, pwm_diff1
, pwm_diff2
;
2090 uint16_t fdo_min
, slope1
, slope2
;
2091 uint32_t reference_clock
;
2095 if (!phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_MicrocodeFanControl
))
2098 if (hwmgr
->thermal_controller
.fanInfo
.bNoFan
) {
2099 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2100 PHM_PlatformCaps_MicrocodeFanControl
);
2104 if (0 == smu7_data
->fan_table_start
) {
2105 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_MicrocodeFanControl
);
2109 duty100
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_FDO_CTRL1
, FMAX_DUTY100
);
2112 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_MicrocodeFanControl
);
2116 tmp64
= hwmgr
->thermal_controller
.advanceFanControlParameters
.usPWMMin
* duty100
;
2117 do_div(tmp64
, 10000);
2118 fdo_min
= (uint16_t)tmp64
;
2120 t_diff1
= hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMed
- hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMin
;
2121 t_diff2
= hwmgr
->thermal_controller
.advanceFanControlParameters
.usTHigh
- hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMed
;
2123 pwm_diff1
= hwmgr
->thermal_controller
.advanceFanControlParameters
.usPWMMed
- hwmgr
->thermal_controller
.advanceFanControlParameters
.usPWMMin
;
2124 pwm_diff2
= hwmgr
->thermal_controller
.advanceFanControlParameters
.usPWMHigh
- hwmgr
->thermal_controller
.advanceFanControlParameters
.usPWMMed
;
2126 slope1
= (uint16_t)((50 + ((16 * duty100
* pwm_diff1
) / t_diff1
)) / 100);
2127 slope2
= (uint16_t)((50 + ((16 * duty100
* pwm_diff2
) / t_diff2
)) / 100);
2129 fan_table
.TempMin
= cpu_to_be16((50 + hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMin
) / 100);
2130 fan_table
.TempMed
= cpu_to_be16((50 + hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMed
) / 100);
2131 fan_table
.TempMax
= cpu_to_be16((50 + hwmgr
->thermal_controller
.advanceFanControlParameters
.usTMax
) / 100);
2133 fan_table
.Slope1
= cpu_to_be16(slope1
);
2134 fan_table
.Slope2
= cpu_to_be16(slope2
);
2136 fan_table
.FdoMin
= cpu_to_be16(fdo_min
);
2138 fan_table
.HystDown
= cpu_to_be16(hwmgr
->thermal_controller
.advanceFanControlParameters
.ucTHyst
);
2140 fan_table
.HystUp
= cpu_to_be16(1);
2142 fan_table
.HystSlope
= cpu_to_be16(1);
2144 fan_table
.TempRespLim
= cpu_to_be16(5);
2146 reference_clock
= amdgpu_asic_get_xclk((struct amdgpu_device
*)hwmgr
->adev
);
2148 fan_table
.RefreshPeriod
= cpu_to_be32((hwmgr
->thermal_controller
.advanceFanControlParameters
.ulCycleDelay
* reference_clock
) / 1600);
2150 fan_table
.FdoMax
= cpu_to_be16((uint16_t)duty100
);
2152 fan_table
.TempSrc
= (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_MULT_THERMAL_CTRL
, TEMP_SEL
);
2154 /* fan_table.FanControl_GL_Flag = 1; */
2156 res
= smu7_copy_bytes_to_smc(hwmgr
, smu7_data
->fan_table_start
, (uint8_t *)&fan_table
, (uint32_t)sizeof(fan_table
), SMC_RAM_END
);
2162 static int iceland_program_mem_timing_parameters(struct pp_hwmgr
*hwmgr
)
2164 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2166 if (data
->need_update_smu7_dpm_table
&
2167 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_OD_UPDATE_MCLK
))
2168 return iceland_program_memory_timing_parameters(hwmgr
);
2173 static int iceland_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
2175 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2176 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
2179 uint32_t low_sclk_interrupt_threshold
= 0;
2181 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2182 PHM_PlatformCaps_SclkThrottleLowNotification
)
2183 && (data
->low_sclk_interrupt_threshold
!= 0)) {
2184 low_sclk_interrupt_threshold
=
2185 data
->low_sclk_interrupt_threshold
;
2187 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold
);
2189 result
= smu7_copy_bytes_to_smc(
2191 smu_data
->smu7_data
.dpm_table_start
+
2192 offsetof(SMU71_Discrete_DpmTable
,
2193 LowSclkInterruptThreshold
),
2194 (uint8_t *)&low_sclk_interrupt_threshold
,
2199 result
= iceland_update_and_upload_mc_reg_table(hwmgr
);
2201 PP_ASSERT_WITH_CODE((0 == result
), "Failed to upload MC reg table!", return result
);
2203 result
= iceland_program_mem_timing_parameters(hwmgr
);
2204 PP_ASSERT_WITH_CODE((result
== 0),
2205 "Failed to program memory timing parameters!",
2211 static uint32_t iceland_get_offsetof(uint32_t type
, uint32_t member
)
2214 case SMU_SoftRegisters
:
2216 case HandshakeDisables
:
2217 return offsetof(SMU71_SoftRegisters
, HandshakeDisables
);
2218 case VoltageChangeTimeout
:
2219 return offsetof(SMU71_SoftRegisters
, VoltageChangeTimeout
);
2220 case AverageGraphicsActivity
:
2221 return offsetof(SMU71_SoftRegisters
, AverageGraphicsActivity
);
2223 return offsetof(SMU71_SoftRegisters
, PreVBlankGap
);
2225 return offsetof(SMU71_SoftRegisters
, VBlankTimeout
);
2226 case UcodeLoadStatus
:
2227 return offsetof(SMU71_SoftRegisters
, UcodeLoadStatus
);
2228 case DRAM_LOG_ADDR_H
:
2229 return offsetof(SMU71_SoftRegisters
, DRAM_LOG_ADDR_H
);
2230 case DRAM_LOG_ADDR_L
:
2231 return offsetof(SMU71_SoftRegisters
, DRAM_LOG_ADDR_L
);
2232 case DRAM_LOG_PHY_ADDR_H
:
2233 return offsetof(SMU71_SoftRegisters
, DRAM_LOG_PHY_ADDR_H
);
2234 case DRAM_LOG_PHY_ADDR_L
:
2235 return offsetof(SMU71_SoftRegisters
, DRAM_LOG_PHY_ADDR_L
);
2236 case DRAM_LOG_BUFF_SIZE
:
2237 return offsetof(SMU71_SoftRegisters
, DRAM_LOG_BUFF_SIZE
);
2240 case SMU_Discrete_DpmTable
:
2242 case LowSclkInterruptThreshold
:
2243 return offsetof(SMU71_Discrete_DpmTable
, LowSclkInterruptThreshold
);
2247 pr_warn("can't get the offset of type %x member %x\n", type
, member
);
2251 static uint32_t iceland_get_mac_definition(uint32_t value
)
2254 case SMU_MAX_LEVELS_GRAPHICS
:
2255 return SMU71_MAX_LEVELS_GRAPHICS
;
2256 case SMU_MAX_LEVELS_MEMORY
:
2257 return SMU71_MAX_LEVELS_MEMORY
;
2258 case SMU_MAX_LEVELS_LINK
:
2259 return SMU71_MAX_LEVELS_LINK
;
2260 case SMU_MAX_ENTRIES_SMIO
:
2261 return SMU71_MAX_ENTRIES_SMIO
;
2262 case SMU_MAX_LEVELS_VDDC
:
2263 return SMU71_MAX_LEVELS_VDDC
;
2264 case SMU_MAX_LEVELS_VDDCI
:
2265 return SMU71_MAX_LEVELS_VDDCI
;
2266 case SMU_MAX_LEVELS_MVDD
:
2267 return SMU71_MAX_LEVELS_MVDD
;
2270 pr_warn("can't get the mac of %x\n", value
);
2274 static int iceland_process_firmware_header(struct pp_hwmgr
*hwmgr
)
2276 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2277 struct smu7_smumgr
*smu7_data
= (struct smu7_smumgr
*)(hwmgr
->smu_backend
);
2283 result
= smu7_read_smc_sram_dword(hwmgr
,
2284 SMU71_FIRMWARE_HEADER_LOCATION
+
2285 offsetof(SMU71_Firmware_Header
, DpmTable
),
2289 smu7_data
->dpm_table_start
= tmp
;
2292 error
|= (0 != result
);
2294 result
= smu7_read_smc_sram_dword(hwmgr
,
2295 SMU71_FIRMWARE_HEADER_LOCATION
+
2296 offsetof(SMU71_Firmware_Header
, SoftRegisters
),
2300 data
->soft_regs_start
= tmp
;
2301 smu7_data
->soft_regs_start
= tmp
;
2304 error
|= (0 != result
);
2307 result
= smu7_read_smc_sram_dword(hwmgr
,
2308 SMU71_FIRMWARE_HEADER_LOCATION
+
2309 offsetof(SMU71_Firmware_Header
, mcRegisterTable
),
2313 smu7_data
->mc_reg_table_start
= tmp
;
2316 result
= smu7_read_smc_sram_dword(hwmgr
,
2317 SMU71_FIRMWARE_HEADER_LOCATION
+
2318 offsetof(SMU71_Firmware_Header
, FanTable
),
2322 smu7_data
->fan_table_start
= tmp
;
2325 error
|= (0 != result
);
2327 result
= smu7_read_smc_sram_dword(hwmgr
,
2328 SMU71_FIRMWARE_HEADER_LOCATION
+
2329 offsetof(SMU71_Firmware_Header
, mcArbDramTimingTable
),
2333 smu7_data
->arb_table_start
= tmp
;
2336 error
|= (0 != result
);
2339 result
= smu7_read_smc_sram_dword(hwmgr
,
2340 SMU71_FIRMWARE_HEADER_LOCATION
+
2341 offsetof(SMU71_Firmware_Header
, Version
),
2345 hwmgr
->microcode_version_info
.SMC
= tmp
;
2348 error
|= (0 != result
);
2350 result
= smu7_read_smc_sram_dword(hwmgr
,
2351 SMU71_FIRMWARE_HEADER_LOCATION
+
2352 offsetof(SMU71_Firmware_Header
, UlvSettings
),
2356 smu7_data
->ulv_setting_starts
= tmp
;
2359 error
|= (0 != result
);
2361 return error
? 1 : 0;
2364 /*---------------------------MC----------------------------*/
2366 static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr
*hwmgr
)
2368 return (uint8_t) (0xFF & (cgs_read_register(hwmgr
->device
, mmBIOS_SCRATCH_4
) >> 16));
2371 static bool iceland_check_s0_mc_reg_index(uint16_t in_reg
, uint16_t *out_reg
)
2376 case mmMC_SEQ_RAS_TIMING
:
2377 *out_reg
= mmMC_SEQ_RAS_TIMING_LP
;
2380 case mmMC_SEQ_DLL_STBY
:
2381 *out_reg
= mmMC_SEQ_DLL_STBY_LP
;
2384 case mmMC_SEQ_G5PDX_CMD0
:
2385 *out_reg
= mmMC_SEQ_G5PDX_CMD0_LP
;
2388 case mmMC_SEQ_G5PDX_CMD1
:
2389 *out_reg
= mmMC_SEQ_G5PDX_CMD1_LP
;
2392 case mmMC_SEQ_G5PDX_CTRL
:
2393 *out_reg
= mmMC_SEQ_G5PDX_CTRL_LP
;
2396 case mmMC_SEQ_CAS_TIMING
:
2397 *out_reg
= mmMC_SEQ_CAS_TIMING_LP
;
2400 case mmMC_SEQ_MISC_TIMING
:
2401 *out_reg
= mmMC_SEQ_MISC_TIMING_LP
;
2404 case mmMC_SEQ_MISC_TIMING2
:
2405 *out_reg
= mmMC_SEQ_MISC_TIMING2_LP
;
2408 case mmMC_SEQ_PMG_DVS_CMD
:
2409 *out_reg
= mmMC_SEQ_PMG_DVS_CMD_LP
;
2412 case mmMC_SEQ_PMG_DVS_CTL
:
2413 *out_reg
= mmMC_SEQ_PMG_DVS_CTL_LP
;
2416 case mmMC_SEQ_RD_CTL_D0
:
2417 *out_reg
= mmMC_SEQ_RD_CTL_D0_LP
;
2420 case mmMC_SEQ_RD_CTL_D1
:
2421 *out_reg
= mmMC_SEQ_RD_CTL_D1_LP
;
2424 case mmMC_SEQ_WR_CTL_D0
:
2425 *out_reg
= mmMC_SEQ_WR_CTL_D0_LP
;
2428 case mmMC_SEQ_WR_CTL_D1
:
2429 *out_reg
= mmMC_SEQ_WR_CTL_D1_LP
;
2432 case mmMC_PMG_CMD_EMRS
:
2433 *out_reg
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
2436 case mmMC_PMG_CMD_MRS
:
2437 *out_reg
= mmMC_SEQ_PMG_CMD_MRS_LP
;
2440 case mmMC_PMG_CMD_MRS1
:
2441 *out_reg
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
2444 case mmMC_SEQ_PMG_TIMING
:
2445 *out_reg
= mmMC_SEQ_PMG_TIMING_LP
;
2448 case mmMC_PMG_CMD_MRS2
:
2449 *out_reg
= mmMC_SEQ_PMG_CMD_MRS2_LP
;
2452 case mmMC_SEQ_WR_CTL_2
:
2453 *out_reg
= mmMC_SEQ_WR_CTL_2_LP
;
2464 static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table
*table
)
2469 for (i
= 0; i
< table
->last
; i
++) {
2470 table
->mc_reg_address
[i
].s0
=
2471 iceland_check_s0_mc_reg_index(table
->mc_reg_address
[i
].s1
, &address
)
2472 ? address
: table
->mc_reg_address
[i
].s1
;
2477 static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table
*table
,
2478 struct iceland_mc_reg_table
*ni_table
)
2482 PP_ASSERT_WITH_CODE((table
->last
<= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
2483 "Invalid VramInfo table.", return -EINVAL
);
2484 PP_ASSERT_WITH_CODE((table
->num_entries
<= MAX_AC_TIMING_ENTRIES
),
2485 "Invalid VramInfo table.", return -EINVAL
);
2487 for (i
= 0; i
< table
->last
; i
++) {
2488 ni_table
->mc_reg_address
[i
].s1
= table
->mc_reg_address
[i
].s1
;
2490 ni_table
->last
= table
->last
;
2492 for (i
= 0; i
< table
->num_entries
; i
++) {
2493 ni_table
->mc_reg_table_entry
[i
].mclk_max
=
2494 table
->mc_reg_table_entry
[i
].mclk_max
;
2495 for (j
= 0; j
< table
->last
; j
++) {
2496 ni_table
->mc_reg_table_entry
[i
].mc_data
[j
] =
2497 table
->mc_reg_table_entry
[i
].mc_data
[j
];
2501 ni_table
->num_entries
= table
->num_entries
;
2506 static int iceland_set_mc_special_registers(struct pp_hwmgr
*hwmgr
,
2507 struct iceland_mc_reg_table
*table
)
2511 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2513 for (i
= 0, j
= table
->last
; i
< table
->last
; i
++) {
2514 PP_ASSERT_WITH_CODE((j
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
2515 "Invalid VramInfo table.", return -EINVAL
);
2517 switch (table
->mc_reg_address
[i
].s1
) {
2519 case mmMC_SEQ_MISC1
:
2520 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_EMRS
);
2521 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_EMRS
;
2522 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
2523 for (k
= 0; k
< table
->num_entries
; k
++) {
2524 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
2525 ((temp_reg
& 0xffff0000)) |
2526 ((table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16);
2530 PP_ASSERT_WITH_CODE((j
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
2531 "Invalid VramInfo table.", return -EINVAL
);
2532 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS
);
2533 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS
;
2534 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS_LP
;
2535 for (k
= 0; k
< table
->num_entries
; k
++) {
2536 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
2537 (temp_reg
& 0xffff0000) |
2538 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
2540 if (!data
->is_memory_gddr5
) {
2541 table
->mc_reg_table_entry
[k
].mc_data
[j
] |= 0x100;
2546 if (!data
->is_memory_gddr5
) {
2547 PP_ASSERT_WITH_CODE((j
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
2548 "Invalid VramInfo table.", return -EINVAL
);
2549 table
->mc_reg_address
[j
].s1
= mmMC_PMG_AUTO_CMD
;
2550 table
->mc_reg_address
[j
].s0
= mmMC_PMG_AUTO_CMD
;
2551 for (k
= 0; k
< table
->num_entries
; k
++) {
2552 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
2553 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16;
2560 case mmMC_SEQ_RESERVE_M
:
2561 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS1
);
2562 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS1
;
2563 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
2564 for (k
= 0; k
< table
->num_entries
; k
++) {
2565 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
2566 (temp_reg
& 0xffff0000) |
2567 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
2583 static int iceland_set_valid_flag(struct iceland_mc_reg_table
*table
)
2586 for (i
= 0; i
< table
->last
; i
++) {
2587 for (j
= 1; j
< table
->num_entries
; j
++) {
2588 if (table
->mc_reg_table_entry
[j
-1].mc_data
[i
] !=
2589 table
->mc_reg_table_entry
[j
].mc_data
[i
]) {
2590 table
->validflag
|= (1<<i
);
2599 static int iceland_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr
)
2602 struct iceland_smumgr
*smu_data
= (struct iceland_smumgr
*)(hwmgr
->smu_backend
);
2603 pp_atomctrl_mc_reg_table
*table
;
2604 struct iceland_mc_reg_table
*ni_table
= &smu_data
->mc_reg_table
;
2605 uint8_t module_index
= iceland_get_memory_modile_index(hwmgr
);
2607 table
= kzalloc(sizeof(pp_atomctrl_mc_reg_table
), GFP_KERNEL
);
2612 /* Program additional LP registers that are no longer programmed by VBIOS */
2613 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING
));
2614 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING
));
2615 cgs_write_register(hwmgr
->device
, mmMC_SEQ_DLL_STBY_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_DLL_STBY
));
2616 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD0
));
2617 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD1
));
2618 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CTRL_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CTRL
));
2619 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CMD_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CMD
));
2620 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CTL_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CTL
));
2621 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING
));
2622 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2
));
2623 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_EMRS_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_EMRS
));
2624 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS
));
2625 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS1_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS1
));
2626 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D0
));
2627 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1
));
2628 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0
));
2629 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1
));
2630 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING
));
2631 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS2_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS2
));
2632 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_2_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_2
));
2634 memset(table
, 0x00, sizeof(pp_atomctrl_mc_reg_table
));
2636 result
= atomctrl_initialize_mc_reg_table(hwmgr
, module_index
, table
);
2639 result
= iceland_copy_vbios_smc_reg_table(table
, ni_table
);
2642 iceland_set_s0_mc_reg_index(ni_table
);
2643 result
= iceland_set_mc_special_registers(hwmgr
, ni_table
);
2647 iceland_set_valid_flag(ni_table
);
2654 static bool iceland_is_dpm_running(struct pp_hwmgr
*hwmgr
)
2656 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr
->device
,
2657 CGS_IND_REG__SMC
, FEATURE_STATUS
, VOLTAGE_CONTROLLER_ON
))
2661 const struct pp_smumgr_func iceland_smu_funcs
= {
2662 .smu_init
= &iceland_smu_init
,
2663 .smu_fini
= &smu7_smu_fini
,
2664 .start_smu
= &iceland_start_smu
,
2665 .check_fw_load_finish
= &smu7_check_fw_load_finish
,
2666 .request_smu_load_fw
= &smu7_reload_firmware
,
2667 .request_smu_load_specific_fw
= &iceland_request_smu_load_specific_fw
,
2668 .send_msg_to_smc
= &smu7_send_msg_to_smc
,
2669 .send_msg_to_smc_with_parameter
= &smu7_send_msg_to_smc_with_parameter
,
2670 .download_pptable_settings
= NULL
,
2671 .upload_pptable_settings
= NULL
,
2672 .get_offsetof
= iceland_get_offsetof
,
2673 .process_firmware_header
= iceland_process_firmware_header
,
2674 .init_smc_table
= iceland_init_smc_table
,
2675 .update_sclk_threshold
= iceland_update_sclk_threshold
,
2676 .thermal_setup_fan_table
= iceland_thermal_setup_fan_table
,
2677 .populate_all_graphic_levels
= iceland_populate_all_graphic_levels
,
2678 .populate_all_memory_levels
= iceland_populate_all_memory_levels
,
2679 .get_mac_definition
= iceland_get_mac_definition
,
2680 .initialize_mc_reg_table
= iceland_initialize_mc_reg_table
,
2681 .is_dpm_running
= iceland_is_dpm_running
,