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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / i2c / tda998x_drv.c
bloba7c39f39793ff2c2ce152e3cba3c3036513a7f19
1 /*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <linux/component.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/hdmi.h>
21 #include <linux/module.h>
22 #include <linux/platform_data/tda9950.h>
23 #include <linux/irq.h>
24 #include <sound/asoundef.h>
25 #include <sound/hdmi-codec.h>
26
27 #include <drm/drmP.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_of.h>
32 #include <drm/i2c/tda998x.h>
33
34 #include <media/cec-notifier.h>
35
36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
37
38 struct tda998x_audio_port {
39 u8 format; /* AFMT_xxx */
40 u8 config; /* AP value */
41 };
42
43 struct tda998x_priv {
44 struct i2c_client *cec;
45 struct i2c_client *hdmi;
46 struct mutex mutex;
47 u16 rev;
48 u8 cec_addr;
49 u8 current_page;
50 bool is_on;
51 bool supports_infoframes;
52 bool sink_has_audio;
53 u8 vip_cntrl_0;
54 u8 vip_cntrl_1;
55 u8 vip_cntrl_2;
56 unsigned long tmds_clock;
57 struct tda998x_audio_params audio_params;
58
59 struct platform_device *audio_pdev;
60 struct mutex audio_mutex;
61
62 struct mutex edid_mutex;
63 wait_queue_head_t wq_edid;
64 volatile int wq_edid_wait;
65
66 struct work_struct detect_work;
67 struct timer_list edid_delay_timer;
68 wait_queue_head_t edid_delay_waitq;
69 bool edid_delay_active;
70
71 struct drm_encoder encoder;
72 struct drm_bridge bridge;
73 struct drm_connector connector;
74
75 struct tda998x_audio_port audio_port[2];
76 struct tda9950_glue cec_glue;
77 struct gpio_desc *calib;
78 struct cec_notifier *cec_notify;
79 };
80
81 #define conn_to_tda998x_priv(x) \
82 container_of(x, struct tda998x_priv, connector)
83 #define enc_to_tda998x_priv(x) \
84 container_of(x, struct tda998x_priv, encoder)
85 #define bridge_to_tda998x_priv(x) \
86 container_of(x, struct tda998x_priv, bridge)
87
88 /* The TDA9988 series of devices use a paged register scheme.. to simplify
89 * things we encode the page # in upper bits of the register #. To read/
90 * write a given register, we need to make sure CURPAGE register is set
91 * appropriately. Which implies reads/writes are not atomic. Fun!
92 */
93
94 #define REG(page, addr) (((page) << 8) | (addr))
95 #define REG2ADDR(reg) ((reg) & 0xff)
96 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
97
98 #define REG_CURPAGE 0xff /* write */
99
100
101 /* Page 00h: General Control */
102 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
103 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
104 # define MAIN_CNTRL0_SR (1 << 0)
105 # define MAIN_CNTRL0_DECS (1 << 1)
106 # define MAIN_CNTRL0_DEHS (1 << 2)
107 # define MAIN_CNTRL0_CECS (1 << 3)
108 # define MAIN_CNTRL0_CEHS (1 << 4)
109 # define MAIN_CNTRL0_SCALER (1 << 7)
110 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
111 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
112 # define SOFTRESET_AUDIO (1 << 0)
113 # define SOFTRESET_I2C_MASTER (1 << 1)
114 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
115 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
116 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
117 # define I2C_MASTER_DIS_MM (1 << 0)
118 # define I2C_MASTER_DIS_FILT (1 << 1)
119 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
120 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
121 # define FEAT_POWERDOWN_PREFILT BIT(0)
122 # define FEAT_POWERDOWN_CSC BIT(1)
123 # define FEAT_POWERDOWN_SPDIF (1 << 3)
124 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
125 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
126 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
127 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
128 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
129 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
130 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
131 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
132 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
133 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
134 # define VIP_CNTRL_0_MIRR_A (1 << 7)
135 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
136 # define VIP_CNTRL_0_MIRR_B (1 << 3)
137 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
138 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
139 # define VIP_CNTRL_1_MIRR_C (1 << 7)
140 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
141 # define VIP_CNTRL_1_MIRR_D (1 << 3)
142 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
143 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
144 # define VIP_CNTRL_2_MIRR_E (1 << 7)
145 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
146 # define VIP_CNTRL_2_MIRR_F (1 << 3)
147 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
148 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
149 # define VIP_CNTRL_3_X_TGL (1 << 0)
150 # define VIP_CNTRL_3_H_TGL (1 << 1)
151 # define VIP_CNTRL_3_V_TGL (1 << 2)
152 # define VIP_CNTRL_3_EMB (1 << 3)
153 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
154 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
155 # define VIP_CNTRL_3_DE_INT (1 << 6)
156 # define VIP_CNTRL_3_EDGE (1 << 7)
157 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
158 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
159 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
160 # define VIP_CNTRL_4_CCIR656 (1 << 4)
161 # define VIP_CNTRL_4_656_ALT (1 << 5)
162 # define VIP_CNTRL_4_TST_656 (1 << 6)
163 # define VIP_CNTRL_4_TST_PAT (1 << 7)
164 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
165 # define VIP_CNTRL_5_CKCASE (1 << 0)
166 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
167 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
168 # define MUX_AP_SELECT_I2S 0x64
169 # define MUX_AP_SELECT_SPDIF 0x40
170 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
171 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
172 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
173 # define MAT_CONTRL_MAT_BP (1 << 2)
174 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
175 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
176 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
177 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
178 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
179 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
180 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
181 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
182 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
183 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
184 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
185 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
186 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
187 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
188 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
189 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
190 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
191 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
192 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
193 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
194 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
195 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
196 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
197 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
198 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
199 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
200 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
201 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
202 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
203 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
204 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
205 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
206 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
207 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
208 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
209 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
210 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
211 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
212 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
213 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
214 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
215 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
216 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
217 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
218 # define TBG_CNTRL_0_DE_EXT (1 << 2)
219 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
220 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
221 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
222 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
223 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
224 # define TBG_CNTRL_1_H_TGL (1 << 0)
225 # define TBG_CNTRL_1_V_TGL (1 << 1)
226 # define TBG_CNTRL_1_TGL_EN (1 << 2)
227 # define TBG_CNTRL_1_X_EXT (1 << 3)
228 # define TBG_CNTRL_1_H_EXT (1 << 4)
229 # define TBG_CNTRL_1_V_EXT (1 << 5)
230 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
231 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
232 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
233 # define HVF_CNTRL_0_SM (1 << 7)
234 # define HVF_CNTRL_0_RWB (1 << 6)
235 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
236 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
237 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
238 # define HVF_CNTRL_1_FOR (1 << 0)
239 # define HVF_CNTRL_1_YUVBLK (1 << 1)
240 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
241 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
242 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
243 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
244 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
245 # define I2S_FORMAT(x) (((x) & 3) << 0)
246 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
247 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
248 # define AIP_CLKSEL_AIP_I2S (1 << 3)
249 # define AIP_CLKSEL_FS_ACLK (0 << 0)
250 # define AIP_CLKSEL_FS_MCLK (1 << 0)
251 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
252
253 /* Page 02h: PLL settings */
254 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
255 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
256 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
257 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
258 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
259 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
260 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
261 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
262 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
263 # define PLL_SERIAL_3_SRL_DE (1 << 2)
264 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
265 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
266 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
267 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
268 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
269 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
270 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
271 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
272 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
273 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
274 # define AUDIO_DIV_SERCLK_1 0
275 # define AUDIO_DIV_SERCLK_2 1
276 # define AUDIO_DIV_SERCLK_4 2
277 # define AUDIO_DIV_SERCLK_8 3
278 # define AUDIO_DIV_SERCLK_16 4
279 # define AUDIO_DIV_SERCLK_32 5
280 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
281 # define SEL_CLK_SEL_CLK1 (1 << 0)
282 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
283 # define SEL_CLK_ENA_SC_CLK (1 << 3)
284 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
285
286
287 /* Page 09h: EDID Control */
288 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
289 /* next 127 successive registers are the EDID block */
290 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
291 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
292 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
293 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
294 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
295
296
297 /* Page 10h: information frames and packets */
298 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
299 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
300 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
301 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
302 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
303
304
305 /* Page 11h: audio settings and content info packets */
306 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
307 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
308 # define AIP_CNTRL_0_SWAP (1 << 1)
309 # define AIP_CNTRL_0_LAYOUT (1 << 2)
310 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
311 # define AIP_CNTRL_0_RST_CTS (1 << 6)
312 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
313 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
314 # define CA_I2S_HBR_CHSTAT (1 << 6)
315 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
316 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
317 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
318 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
319 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
320 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
321 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
322 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
323 # define CTS_N_K(x) (((x) & 7) << 0)
324 # define CTS_N_M(x) (((x) & 3) << 4)
325 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
326 # define ENC_CNTRL_RST_ENC (1 << 0)
327 # define ENC_CNTRL_RST_SEL (1 << 1)
328 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
329 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
330 # define DIP_FLAGS_ACR (1 << 0)
331 # define DIP_FLAGS_GC (1 << 1)
332 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
333 # define DIP_IF_FLAGS_IF1 (1 << 1)
334 # define DIP_IF_FLAGS_IF2 (1 << 2)
335 # define DIP_IF_FLAGS_IF3 (1 << 3)
336 # define DIP_IF_FLAGS_IF4 (1 << 4)
337 # define DIP_IF_FLAGS_IF5 (1 << 5)
338 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
339
340
341 /* Page 12h: HDCP and OTP */
342 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
343 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
344 # define TX4_PD_RAM (1 << 1)
345 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
346 # define TX33_HDMI (1 << 1)
347
348
349 /* Page 13h: Gamut related metadata packets */
350
351
352
353 /* CEC registers: (not paged)
354 */
355 #define REG_CEC_INTSTATUS 0xee /* read */
356 # define CEC_INTSTATUS_CEC (1 << 0)
357 # define CEC_INTSTATUS_HDMI (1 << 1)
358 #define REG_CEC_CAL_XOSC_CTRL1 0xf2
359 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0)
360 #define REG_CEC_DES_FREQ2 0xf5
361 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
362 #define REG_CEC_CLK 0xf6
363 # define CEC_CLK_FRO 0x11
364 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
365 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
366 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
367 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
368 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
369 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
370 #define REG_CEC_RXSHPDINT 0xfd /* read */
371 # define CEC_RXSHPDINT_RXSENS BIT(0)
372 # define CEC_RXSHPDINT_HPD BIT(1)
373 #define REG_CEC_RXSHPDLEV 0xfe /* read */
374 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
375 # define CEC_RXSHPDLEV_HPD (1 << 1)
376
377 #define REG_CEC_ENAMODS 0xff /* read/write */
378 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7)
379 # define CEC_ENAMODS_DIS_FRO (1 << 6)
380 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
381 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
382 # define CEC_ENAMODS_EN_HDMI (1 << 1)
383 # define CEC_ENAMODS_EN_CEC (1 << 0)
384
385
386 /* Device versions: */
387 #define TDA9989N2 0x0101
388 #define TDA19989 0x0201
389 #define TDA19989N2 0x0202
390 #define TDA19988 0x0301
391
392 static void
393 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
394 {
395 u8 buf[] = {addr, val};
396 struct i2c_msg msg = {
397 .addr = priv->cec_addr,
398 .len = 2,
399 .buf = buf,
400 };
401 int ret;
402
403 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
404 if (ret < 0)
405 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
406 ret, addr);
407 }
408
409 static u8
410 cec_read(struct tda998x_priv *priv, u8 addr)
411 {
412 u8 val;
413 struct i2c_msg msg[2] = {
414 {
415 .addr = priv->cec_addr,
416 .len = 1,
417 .buf = &addr,
418 }, {
419 .addr = priv->cec_addr,
420 .flags = I2C_M_RD,
421 .len = 1,
422 .buf = &val,
423 },
424 };
425 int ret;
426
427 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
428 if (ret < 0) {
429 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
430 ret, addr);
431 val = 0;
432 }
433
434 return val;
435 }
436
437 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
438 {
439 int val = cec_read(priv, REG_CEC_ENAMODS);
440
441 if (val < 0)
442 return;
443
444 if (enable)
445 val |= mods;
446 else
447 val &= ~mods;
448
449 cec_write(priv, REG_CEC_ENAMODS, val);
450 }
451
452 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
453 {
454 if (enable) {
455 u8 val;
456
457 cec_write(priv, 0xf3, 0xc0);
458 cec_write(priv, 0xf4, 0xd4);
459
460 /* Enable automatic calibration mode */
461 val = cec_read(priv, REG_CEC_DES_FREQ2);
462 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
463 cec_write(priv, REG_CEC_DES_FREQ2, val);
464
465 /* Enable free running oscillator */
466 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
467 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
468
469 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
470 CEC_CAL_XOSC_CTRL1_ENA_CAL);
471 } else {
472 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
473 }
474 }
475
476 /*
477 * Calibration for the internal oscillator: we need to set calibration mode,
478 * and then pulse the IRQ line low for a 10ms ± 1% period.
479 */
480 static void tda998x_cec_calibration(struct tda998x_priv *priv)
481 {
482 struct gpio_desc *calib = priv->calib;
483
484 mutex_lock(&priv->edid_mutex);
485 if (priv->hdmi->irq > 0)
486 disable_irq(priv->hdmi->irq);
487 gpiod_direction_output(calib, 1);
488 tda998x_cec_set_calibration(priv, true);
489
490 local_irq_disable();
491 gpiod_set_value(calib, 0);
492 mdelay(10);
493 gpiod_set_value(calib, 1);
494 local_irq_enable();
495
496 tda998x_cec_set_calibration(priv, false);
497 gpiod_direction_input(calib);
498 if (priv->hdmi->irq > 0)
499 enable_irq(priv->hdmi->irq);
500 mutex_unlock(&priv->edid_mutex);
501 }
502
503 static int tda998x_cec_hook_init(void *data)
504 {
505 struct tda998x_priv *priv = data;
506 struct gpio_desc *calib;
507
508 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
509 if (IS_ERR(calib)) {
510 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
511 PTR_ERR(calib));
512 return PTR_ERR(calib);
513 }
514
515 priv->calib = calib;
516
517 return 0;
518 }
519
520 static void tda998x_cec_hook_exit(void *data)
521 {
522 struct tda998x_priv *priv = data;
523
524 gpiod_put(priv->calib);
525 priv->calib = NULL;
526 }
527
528 static int tda998x_cec_hook_open(void *data)
529 {
530 struct tda998x_priv *priv = data;
531
532 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
533 tda998x_cec_calibration(priv);
534
535 return 0;
536 }
537
538 static void tda998x_cec_hook_release(void *data)
539 {
540 struct tda998x_priv *priv = data;
541
542 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
543 }
544
545 static int
546 set_page(struct tda998x_priv *priv, u16 reg)
547 {
548 if (REG2PAGE(reg) != priv->current_page) {
549 struct i2c_client *client = priv->hdmi;
550 u8 buf[] = {
551 REG_CURPAGE, REG2PAGE(reg)
552 };
553 int ret = i2c_master_send(client, buf, sizeof(buf));
554 if (ret < 0) {
555 dev_err(&client->dev, "%s %04x err %d\n", __func__,
556 reg, ret);
557 return ret;
558 }
559
560 priv->current_page = REG2PAGE(reg);
561 }
562 return 0;
563 }
564
565 static int
566 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
567 {
568 struct i2c_client *client = priv->hdmi;
569 u8 addr = REG2ADDR(reg);
570 int ret;
571
572 mutex_lock(&priv->mutex);
573 ret = set_page(priv, reg);
574 if (ret < 0)
575 goto out;
576
577 ret = i2c_master_send(client, &addr, sizeof(addr));
578 if (ret < 0)
579 goto fail;
580
581 ret = i2c_master_recv(client, buf, cnt);
582 if (ret < 0)
583 goto fail;
584
585 goto out;
586
587 fail:
588 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
589 out:
590 mutex_unlock(&priv->mutex);
591 return ret;
592 }
593
594 #define MAX_WRITE_RANGE_BUF 32
595
596 static void
597 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
598 {
599 struct i2c_client *client = priv->hdmi;
600 /* This is the maximum size of the buffer passed in */
601 u8 buf[MAX_WRITE_RANGE_BUF + 1];
602 int ret;
603
604 if (cnt > MAX_WRITE_RANGE_BUF) {
605 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
606 MAX_WRITE_RANGE_BUF);
607 return;
608 }
609
610 buf[0] = REG2ADDR(reg);
611 memcpy(&buf[1], p, cnt);
612
613 mutex_lock(&priv->mutex);
614 ret = set_page(priv, reg);
615 if (ret < 0)
616 goto out;
617
618 ret = i2c_master_send(client, buf, cnt + 1);
619 if (ret < 0)
620 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
621 out:
622 mutex_unlock(&priv->mutex);
623 }
624
625 static int
626 reg_read(struct tda998x_priv *priv, u16 reg)
627 {
628 u8 val = 0;
629 int ret;
630
631 ret = reg_read_range(priv, reg, &val, sizeof(val));
632 if (ret < 0)
633 return ret;
634 return val;
635 }
636
637 static void
638 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
639 {
640 struct i2c_client *client = priv->hdmi;
641 u8 buf[] = {REG2ADDR(reg), val};
642 int ret;
643
644 mutex_lock(&priv->mutex);
645 ret = set_page(priv, reg);
646 if (ret < 0)
647 goto out;
648
649 ret = i2c_master_send(client, buf, sizeof(buf));
650 if (ret < 0)
651 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
652 out:
653 mutex_unlock(&priv->mutex);
654 }
655
656 static void
657 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
658 {
659 struct i2c_client *client = priv->hdmi;
660 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
661 int ret;
662
663 mutex_lock(&priv->mutex);
664 ret = set_page(priv, reg);
665 if (ret < 0)
666 goto out;
667
668 ret = i2c_master_send(client, buf, sizeof(buf));
669 if (ret < 0)
670 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
671 out:
672 mutex_unlock(&priv->mutex);
673 }
674
675 static void
676 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
677 {
678 int old_val;
679
680 old_val = reg_read(priv, reg);
681 if (old_val >= 0)
682 reg_write(priv, reg, old_val | val);
683 }
684
685 static void
686 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
687 {
688 int old_val;
689
690 old_val = reg_read(priv, reg);
691 if (old_val >= 0)
692 reg_write(priv, reg, old_val & ~val);
693 }
694
695 static void
696 tda998x_reset(struct tda998x_priv *priv)
697 {
698 /* reset audio and i2c master: */
699 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
700 msleep(50);
701 reg_write(priv, REG_SOFTRESET, 0);
702 msleep(50);
703
704 /* reset transmitter: */
705 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
706 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
707
708 /* PLL registers common configuration */
709 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
710 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
711 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
712 reg_write(priv, REG_SERIALIZER, 0x00);
713 reg_write(priv, REG_BUFFER_OUT, 0x00);
714 reg_write(priv, REG_PLL_SCG1, 0x00);
715 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
716 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
717 reg_write(priv, REG_PLL_SCGN1, 0xfa);
718 reg_write(priv, REG_PLL_SCGN2, 0x00);
719 reg_write(priv, REG_PLL_SCGR1, 0x5b);
720 reg_write(priv, REG_PLL_SCGR2, 0x00);
721 reg_write(priv, REG_PLL_SCG2, 0x10);
722
723 /* Write the default value MUX register */
724 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
725 }
726
727 /*
728 * The TDA998x has a problem when trying to read the EDID close to a
729 * HPD assertion: it needs a delay of 100ms to avoid timing out while
730 * trying to read EDID data.
731 *
732 * However, tda998x_connector_get_modes() may be called at any moment
733 * after tda998x_connector_detect() indicates that we are connected, so
734 * we need to delay probing modes in tda998x_connector_get_modes() after
735 * we have seen a HPD inactive->active transition. This code implements
736 * that delay.
737 */
738 static void tda998x_edid_delay_done(struct timer_list *t)
739 {
740 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
741
742 priv->edid_delay_active = false;
743 wake_up(&priv->edid_delay_waitq);
744 schedule_work(&priv->detect_work);
745 }
746
747 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
748 {
749 priv->edid_delay_active = true;
750 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
751 }
752
753 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
754 {
755 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
756 }
757
758 /*
759 * We need to run the KMS hotplug event helper outside of our threaded
760 * interrupt routine as this can call back into our get_modes method,
761 * which will want to make use of interrupts.
762 */
763 static void tda998x_detect_work(struct work_struct *work)
764 {
765 struct tda998x_priv *priv =
766 container_of(work, struct tda998x_priv, detect_work);
767 struct drm_device *dev = priv->connector.dev;
768
769 if (dev)
770 drm_kms_helper_hotplug_event(dev);
771 }
772
773 /*
774 * only 2 interrupts may occur: screen plug/unplug and EDID read
775 */
776 static irqreturn_t tda998x_irq_thread(int irq, void *data)
777 {
778 struct tda998x_priv *priv = data;
779 u8 sta, cec, lvl, flag0, flag1, flag2;
780 bool handled = false;
781
782 sta = cec_read(priv, REG_CEC_INTSTATUS);
783 if (sta & CEC_INTSTATUS_HDMI) {
784 cec = cec_read(priv, REG_CEC_RXSHPDINT);
785 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
786 flag0 = reg_read(priv, REG_INT_FLAGS_0);
787 flag1 = reg_read(priv, REG_INT_FLAGS_1);
788 flag2 = reg_read(priv, REG_INT_FLAGS_2);
789 DRM_DEBUG_DRIVER(
790 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
791 sta, cec, lvl, flag0, flag1, flag2);
792
793 if (cec & CEC_RXSHPDINT_HPD) {
794 if (lvl & CEC_RXSHPDLEV_HPD) {
795 tda998x_edid_delay_start(priv);
796 } else {
797 schedule_work(&priv->detect_work);
798 cec_notifier_set_phys_addr(priv->cec_notify,
799 CEC_PHYS_ADDR_INVALID);
800 }
801
802 handled = true;
803 }
804
805 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
806 priv->wq_edid_wait = 0;
807 wake_up(&priv->wq_edid);
808 handled = true;
809 }
810 }
811
812 return IRQ_RETVAL(handled);
813 }
814
815 static void
816 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
817 union hdmi_infoframe *frame)
818 {
819 u8 buf[MAX_WRITE_RANGE_BUF];
820 ssize_t len;
821
822 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
823 if (len < 0) {
824 dev_err(&priv->hdmi->dev,
825 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
826 frame->any.type, len);
827 return;
828 }
829
830 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
831 reg_write_range(priv, addr, buf, len);
832 reg_set(priv, REG_DIP_IF_FLAGS, bit);
833 }
834
835 static int tda998x_write_aif(struct tda998x_priv *priv,
836 struct hdmi_audio_infoframe *cea)
837 {
838 union hdmi_infoframe frame;
839
840 frame.audio = *cea;
841
842 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
843
844 return 0;
845 }
846
847 static void
848 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
849 {
850 union hdmi_infoframe frame;
851
852 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
853 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
854
855 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
856 }
857
858 /* Audio support */
859
860 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
861 {
862 if (on) {
863 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
864 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
865 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
866 } else {
867 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
868 }
869 }
870
871 static int
872 tda998x_configure_audio(struct tda998x_priv *priv,
873 struct tda998x_audio_params *params)
874 {
875 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
876 u32 n;
877
878 /* Enable audio ports */
879 reg_write(priv, REG_ENA_AP, params->config);
880
881 /* Set audio input source */
882 switch (params->format) {
883 case AFMT_SPDIF:
884 reg_write(priv, REG_ENA_ACLK, 0);
885 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
886 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
887 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
888 cts_n = CTS_N_M(3) | CTS_N_K(3);
889 break;
890
891 case AFMT_I2S:
892 reg_write(priv, REG_ENA_ACLK, 1);
893 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
894 clksel_aip = AIP_CLKSEL_AIP_I2S;
895 clksel_fs = AIP_CLKSEL_FS_ACLK;
896 switch (params->sample_width) {
897 case 16:
898 cts_n = CTS_N_M(3) | CTS_N_K(1);
899 break;
900 case 18:
901 case 20:
902 case 24:
903 cts_n = CTS_N_M(3) | CTS_N_K(2);
904 break;
905 default:
906 case 32:
907 cts_n = CTS_N_M(3) | CTS_N_K(3);
908 break;
909 }
910 break;
911
912 default:
913 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
914 return -EINVAL;
915 }
916
917 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
918 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
919 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
920 reg_write(priv, REG_CTS_N, cts_n);
921
922 /*
923 * Audio input somehow depends on HDMI line rate which is
924 * related to pixclk. Testing showed that modes with pixclk
925 * >100MHz need a larger divider while <40MHz need the default.
926 * There is no detailed info in the datasheet, so we just
927 * assume 100MHz requires larger divider.
928 */
929 adiv = AUDIO_DIV_SERCLK_8;
930 if (priv->tmds_clock > 100000)
931 adiv++; /* AUDIO_DIV_SERCLK_16 */
932
933 /* S/PDIF asks for a larger divider */
934 if (params->format == AFMT_SPDIF)
935 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
936
937 reg_write(priv, REG_AUDIO_DIV, adiv);
938
939 /*
940 * This is the approximate value of N, which happens to be
941 * the recommended values for non-coherent clocks.
942 */
943 n = 128 * params->sample_rate / 1000;
944
945 /* Write the CTS and N values */
946 buf[0] = 0x44;
947 buf[1] = 0x42;
948 buf[2] = 0x01;
949 buf[3] = n;
950 buf[4] = n >> 8;
951 buf[5] = n >> 16;
952 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
953
954 /* Set CTS clock reference */
955 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
956
957 /* Reset CTS generator */
958 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
959 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
960
961 /* Write the channel status
962 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
963 * there is a separate register for each I2S wire.
964 */
965 buf[0] = params->status[0];
966 buf[1] = params->status[1];
967 buf[2] = params->status[3];
968 buf[3] = params->status[4];
969 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
970
971 tda998x_audio_mute(priv, true);
972 msleep(20);
973 tda998x_audio_mute(priv, false);
974
975 return tda998x_write_aif(priv, &params->cea);
976 }
977
978 static int tda998x_audio_hw_params(struct device *dev, void *data,
979 struct hdmi_codec_daifmt *daifmt,
980 struct hdmi_codec_params *params)
981 {
982 struct tda998x_priv *priv = dev_get_drvdata(dev);
983 int i, ret;
984 struct tda998x_audio_params audio = {
985 .sample_width = params->sample_width,
986 .sample_rate = params->sample_rate,
987 .cea = params->cea,
988 };
989
990 memcpy(audio.status, params->iec.status,
991 min(sizeof(audio.status), sizeof(params->iec.status)));
992
993 switch (daifmt->fmt) {
994 case HDMI_I2S:
995 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
996 daifmt->bit_clk_master || daifmt->frame_clk_master) {
997 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
998 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
999 daifmt->bit_clk_master,
1000 daifmt->frame_clk_master);
1001 return -EINVAL;
1002 }
1003 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1004 if (priv->audio_port[i].format == AFMT_I2S)
1005 audio.config = priv->audio_port[i].config;
1006 audio.format = AFMT_I2S;
1007 break;
1008 case HDMI_SPDIF:
1009 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1010 if (priv->audio_port[i].format == AFMT_SPDIF)
1011 audio.config = priv->audio_port[i].config;
1012 audio.format = AFMT_SPDIF;
1013 break;
1014 default:
1015 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1016 return -EINVAL;
1017 }
1018
1019 if (audio.config == 0) {
1020 dev_err(dev, "%s: No audio configuration found\n", __func__);
1021 return -EINVAL;
1022 }
1023
1024 mutex_lock(&priv->audio_mutex);
1025 if (priv->supports_infoframes && priv->sink_has_audio)
1026 ret = tda998x_configure_audio(priv, &audio);
1027 else
1028 ret = 0;
1029
1030 if (ret == 0)
1031 priv->audio_params = audio;
1032 mutex_unlock(&priv->audio_mutex);
1033
1034 return ret;
1035 }
1036
1037 static void tda998x_audio_shutdown(struct device *dev, void *data)
1038 {
1039 struct tda998x_priv *priv = dev_get_drvdata(dev);
1040
1041 mutex_lock(&priv->audio_mutex);
1042
1043 reg_write(priv, REG_ENA_AP, 0);
1044
1045 priv->audio_params.format = AFMT_UNUSED;
1046
1047 mutex_unlock(&priv->audio_mutex);
1048 }
1049
1050 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1051 {
1052 struct tda998x_priv *priv = dev_get_drvdata(dev);
1053
1054 mutex_lock(&priv->audio_mutex);
1055
1056 tda998x_audio_mute(priv, enable);
1057
1058 mutex_unlock(&priv->audio_mutex);
1059 return 0;
1060 }
1061
1062 static int tda998x_audio_get_eld(struct device *dev, void *data,
1063 uint8_t *buf, size_t len)
1064 {
1065 struct tda998x_priv *priv = dev_get_drvdata(dev);
1066
1067 mutex_lock(&priv->audio_mutex);
1068 memcpy(buf, priv->connector.eld,
1069 min(sizeof(priv->connector.eld), len));
1070 mutex_unlock(&priv->audio_mutex);
1071
1072 return 0;
1073 }
1074
1075 static const struct hdmi_codec_ops audio_codec_ops = {
1076 .hw_params = tda998x_audio_hw_params,
1077 .audio_shutdown = tda998x_audio_shutdown,
1078 .digital_mute = tda998x_audio_digital_mute,
1079 .get_eld = tda998x_audio_get_eld,
1080 };
1081
1082 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1083 struct device *dev)
1084 {
1085 struct hdmi_codec_pdata codec_data = {
1086 .ops = &audio_codec_ops,
1087 .max_i2s_channels = 2,
1088 };
1089 int i;
1090
1091 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
1092 if (priv->audio_port[i].format == AFMT_I2S &&
1093 priv->audio_port[i].config != 0)
1094 codec_data.i2s = 1;
1095 if (priv->audio_port[i].format == AFMT_SPDIF &&
1096 priv->audio_port[i].config != 0)
1097 codec_data.spdif = 1;
1098 }
1099
1100 priv->audio_pdev = platform_device_register_data(
1101 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1102 &codec_data, sizeof(codec_data));
1103
1104 return PTR_ERR_OR_ZERO(priv->audio_pdev);
1105 }
1106
1107 /* DRM connector functions */
1108
1109 static enum drm_connector_status
1110 tda998x_connector_detect(struct drm_connector *connector, bool force)
1111 {
1112 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1113 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1114
1115 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1116 connector_status_disconnected;
1117 }
1118
1119 static void tda998x_connector_destroy(struct drm_connector *connector)
1120 {
1121 drm_connector_cleanup(connector);
1122 }
1123
1124 static const struct drm_connector_funcs tda998x_connector_funcs = {
1125 .dpms = drm_helper_connector_dpms,
1126 .reset = drm_atomic_helper_connector_reset,
1127 .fill_modes = drm_helper_probe_single_connector_modes,
1128 .detect = tda998x_connector_detect,
1129 .destroy = tda998x_connector_destroy,
1130 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1131 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1132 };
1133
1134 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1135 {
1136 struct tda998x_priv *priv = data;
1137 u8 offset, segptr;
1138 int ret, i;
1139
1140 offset = (blk & 1) ? 128 : 0;
1141 segptr = blk / 2;
1142
1143 mutex_lock(&priv->edid_mutex);
1144
1145 reg_write(priv, REG_DDC_ADDR, 0xa0);
1146 reg_write(priv, REG_DDC_OFFS, offset);
1147 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1148 reg_write(priv, REG_DDC_SEGM, segptr);
1149
1150 /* enable reading EDID: */
1151 priv->wq_edid_wait = 1;
1152 reg_write(priv, REG_EDID_CTRL, 0x1);
1153
1154 /* flag must be cleared by sw: */
1155 reg_write(priv, REG_EDID_CTRL, 0x0);
1156
1157 /* wait for block read to complete: */
1158 if (priv->hdmi->irq) {
1159 i = wait_event_timeout(priv->wq_edid,
1160 !priv->wq_edid_wait,
1161 msecs_to_jiffies(100));
1162 if (i < 0) {
1163 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1164 ret = i;
1165 goto failed;
1166 }
1167 } else {
1168 for (i = 100; i > 0; i--) {
1169 msleep(1);
1170 ret = reg_read(priv, REG_INT_FLAGS_2);
1171 if (ret < 0)
1172 goto failed;
1173 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1174 break;
1175 }
1176 }
1177
1178 if (i == 0) {
1179 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1180 ret = -ETIMEDOUT;
1181 goto failed;
1182 }
1183
1184 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1185 if (ret != length) {
1186 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1187 blk, ret);
1188 goto failed;
1189 }
1190
1191 ret = 0;
1192
1193 failed:
1194 mutex_unlock(&priv->edid_mutex);
1195 return ret;
1196 }
1197
1198 static int tda998x_connector_get_modes(struct drm_connector *connector)
1199 {
1200 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1201 struct edid *edid;
1202 int n;
1203
1204 /*
1205 * If we get killed while waiting for the HPD timeout, return
1206 * no modes found: we are not in a restartable path, so we
1207 * can't handle signals gracefully.
1208 */
1209 if (tda998x_edid_delay_wait(priv))
1210 return 0;
1211
1212 if (priv->rev == TDA19988)
1213 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1214
1215 edid = drm_do_get_edid(connector, read_edid_block, priv);
1216
1217 if (priv->rev == TDA19988)
1218 reg_set(priv, REG_TX4, TX4_PD_RAM);
1219
1220 if (!edid) {
1221 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1222 return 0;
1223 }
1224
1225 drm_connector_update_edid_property(connector, edid);
1226 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1227
1228 mutex_lock(&priv->audio_mutex);
1229 n = drm_add_edid_modes(connector, edid);
1230 priv->sink_has_audio = drm_detect_monitor_audio(edid);
1231 mutex_unlock(&priv->audio_mutex);
1232
1233 kfree(edid);
1234
1235 return n;
1236 }
1237
1238 static struct drm_encoder *
1239 tda998x_connector_best_encoder(struct drm_connector *connector)
1240 {
1241 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1242
1243 return priv->bridge.encoder;
1244 }
1245
1246 static
1247 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1248 .get_modes = tda998x_connector_get_modes,
1249 .best_encoder = tda998x_connector_best_encoder,
1250 };
1251
1252 static int tda998x_connector_init(struct tda998x_priv *priv,
1253 struct drm_device *drm)
1254 {
1255 struct drm_connector *connector = &priv->connector;
1256 int ret;
1257
1258 connector->interlace_allowed = 1;
1259
1260 if (priv->hdmi->irq)
1261 connector->polled = DRM_CONNECTOR_POLL_HPD;
1262 else
1263 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1264 DRM_CONNECTOR_POLL_DISCONNECT;
1265
1266 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1267 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1268 DRM_MODE_CONNECTOR_HDMIA);
1269 if (ret)
1270 return ret;
1271
1272 drm_connector_attach_encoder(&priv->connector,
1273 priv->bridge.encoder);
1274
1275 return 0;
1276 }
1277
1278 /* DRM bridge functions */
1279
1280 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1281 {
1282 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1283
1284 return tda998x_connector_init(priv, bridge->dev);
1285 }
1286
1287 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1288 {
1289 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1290
1291 drm_connector_cleanup(&priv->connector);
1292 }
1293
1294 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1295 const struct drm_display_mode *mode)
1296 {
1297 /* TDA19988 dotclock can go up to 165MHz */
1298 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1299
1300 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1301 return MODE_CLOCK_HIGH;
1302 if (mode->htotal >= BIT(13))
1303 return MODE_BAD_HVALUE;
1304 if (mode->vtotal >= BIT(11))
1305 return MODE_BAD_VVALUE;
1306 return MODE_OK;
1307 }
1308
1309 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1310 {
1311 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1312
1313 if (!priv->is_on) {
1314 /* enable video ports, audio will be enabled later */
1315 reg_write(priv, REG_ENA_VP_0, 0xff);
1316 reg_write(priv, REG_ENA_VP_1, 0xff);
1317 reg_write(priv, REG_ENA_VP_2, 0xff);
1318 /* set muxing after enabling ports: */
1319 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1320 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1321 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1322
1323 priv->is_on = true;
1324 }
1325 }
1326
1327 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1328 {
1329 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1330
1331 if (priv->is_on) {
1332 /* disable video ports */
1333 reg_write(priv, REG_ENA_VP_0, 0x00);
1334 reg_write(priv, REG_ENA_VP_1, 0x00);
1335 reg_write(priv, REG_ENA_VP_2, 0x00);
1336
1337 priv->is_on = false;
1338 }
1339 }
1340
1341 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1342 struct drm_display_mode *mode,
1343 struct drm_display_mode *adjusted_mode)
1344 {
1345 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1346 unsigned long tmds_clock;
1347 u16 ref_pix, ref_line, n_pix, n_line;
1348 u16 hs_pix_s, hs_pix_e;
1349 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1350 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1351 u16 vwin1_line_s, vwin1_line_e;
1352 u16 vwin2_line_s, vwin2_line_e;
1353 u16 de_pix_s, de_pix_e;
1354 u8 reg, div, rep;
1355
1356 /*
1357 * Internally TDA998x is using ITU-R BT.656 style sync but
1358 * we get VESA style sync. TDA998x is using a reference pixel
1359 * relative to ITU to sync to the input frame and for output
1360 * sync generation. Currently, we are using reference detection
1361 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1362 * which is position of rising VS with coincident rising HS.
1363 *
1364 * Now there is some issues to take care of:
1365 * - HDMI data islands require sync-before-active
1366 * - TDA998x register values must be > 0 to be enabled
1367 * - REFLINE needs an additional offset of +1
1368 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1369 *
1370 * So we add +1 to all horizontal and vertical register values,
1371 * plus an additional +3 for REFPIX as we are using RGB input only.
1372 */
1373 n_pix = mode->htotal;
1374 n_line = mode->vtotal;
1375
1376 hs_pix_e = mode->hsync_end - mode->hdisplay;
1377 hs_pix_s = mode->hsync_start - mode->hdisplay;
1378 de_pix_e = mode->htotal;
1379 de_pix_s = mode->htotal - mode->hdisplay;
1380 ref_pix = 3 + hs_pix_s;
1381
1382 /*
1383 * Attached LCD controllers may generate broken sync. Allow
1384 * those to adjust the position of the rising VS edge by adding
1385 * HSKEW to ref_pix.
1386 */
1387 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1388 ref_pix += adjusted_mode->hskew;
1389
1390 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1391 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1392 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1393 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1394 vs1_pix_s = vs1_pix_e = hs_pix_s;
1395 vs1_line_s = mode->vsync_start - mode->vdisplay;
1396 vs1_line_e = vs1_line_s +
1397 mode->vsync_end - mode->vsync_start;
1398 vwin2_line_s = vwin2_line_e = 0;
1399 vs2_pix_s = vs2_pix_e = 0;
1400 vs2_line_s = vs2_line_e = 0;
1401 } else {
1402 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1403 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1404 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1405 vs1_pix_s = vs1_pix_e = hs_pix_s;
1406 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1407 vs1_line_e = vs1_line_s +
1408 (mode->vsync_end - mode->vsync_start)/2;
1409 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1410 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1411 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1412 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1413 vs2_line_e = vs2_line_s +
1414 (mode->vsync_end - mode->vsync_start)/2;
1415 }
1416
1417 tmds_clock = mode->clock;
1418
1419 /*
1420 * The divisor is power-of-2. The TDA9983B datasheet gives
1421 * this as ranges of Msample/s, which is 10x the TMDS clock:
1422 * 0 - 800 to 1500 Msample/s
1423 * 1 - 400 to 800 Msample/s
1424 * 2 - 200 to 400 Msample/s
1425 * 3 - as 2 above
1426 */
1427 for (div = 0; div < 3; div++)
1428 if (80000 >> div <= tmds_clock)
1429 break;
1430
1431 mutex_lock(&priv->audio_mutex);
1432
1433 /* mute the audio FIFO: */
1434 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1435
1436 /* set HDMI HDCP mode off: */
1437 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1438 reg_clear(priv, REG_TX33, TX33_HDMI);
1439 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1440
1441 /* no pre-filter or interpolator: */
1442 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1443 HVF_CNTRL_0_INTPOL(0));
1444 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1445 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1446 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1447 VIP_CNTRL_4_BLC(0));
1448
1449 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1450 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1451 PLL_SERIAL_3_SRL_DE);
1452 reg_write(priv, REG_SERIALIZER, 0);
1453 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1454
1455 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1456 rep = 0;
1457 reg_write(priv, REG_RPT_CNTRL, 0);
1458 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1459 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1460
1461 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1462 PLL_SERIAL_2_SRL_PR(rep));
1463
1464 /* set color matrix bypass flag: */
1465 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1466 MAT_CONTRL_MAT_SC(1));
1467 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1468
1469 /* set BIAS tmds value: */
1470 reg_write(priv, REG_ANA_GENERAL, 0x09);
1471
1472 /*
1473 * Sync on rising HSYNC/VSYNC
1474 */
1475 reg = VIP_CNTRL_3_SYNC_HS;
1476
1477 /*
1478 * TDA19988 requires high-active sync at input stage,
1479 * so invert low-active sync provided by master encoder here
1480 */
1481 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1482 reg |= VIP_CNTRL_3_H_TGL;
1483 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1484 reg |= VIP_CNTRL_3_V_TGL;
1485 reg_write(priv, REG_VIP_CNTRL_3, reg);
1486
1487 reg_write(priv, REG_VIDFORMAT, 0x00);
1488 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1489 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1490 reg_write16(priv, REG_NPIX_MSB, n_pix);
1491 reg_write16(priv, REG_NLINE_MSB, n_line);
1492 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1493 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1494 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1495 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1496 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1497 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1498 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1499 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1500 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1501 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1502 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1503 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1504 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1505 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1506 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1507 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1508
1509 if (priv->rev == TDA19988) {
1510 /* let incoming pixels fill the active space (if any) */
1511 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1512 }
1513
1514 /*
1515 * Always generate sync polarity relative to input sync and
1516 * revert input stage toggled sync at output stage
1517 */
1518 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1519 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1520 reg |= TBG_CNTRL_1_H_TGL;
1521 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1522 reg |= TBG_CNTRL_1_V_TGL;
1523 reg_write(priv, REG_TBG_CNTRL_1, reg);
1524
1525 /* must be last register set: */
1526 reg_write(priv, REG_TBG_CNTRL_0, 0);
1527
1528 priv->tmds_clock = adjusted_mode->clock;
1529
1530 /* CEA-861B section 6 says that:
1531 * CEA version 1 (CEA-861) has no support for infoframes.
1532 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1533 * and optional basic audio.
1534 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1535 * and optional digital audio, with audio infoframes.
1536 *
1537 * Since we only support generation of version 2 AVI infoframes,
1538 * ignore CEA version 2 and below (iow, behave as if we're a
1539 * CEA-861 source.)
1540 */
1541 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1542
1543 if (priv->supports_infoframes) {
1544 /* We need to turn HDMI HDCP stuff on to get audio through */
1545 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1546 reg_write(priv, REG_TBG_CNTRL_1, reg);
1547 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1548 reg_set(priv, REG_TX33, TX33_HDMI);
1549
1550 tda998x_write_avi(priv, adjusted_mode);
1551
1552 if (priv->audio_params.format != AFMT_UNUSED &&
1553 priv->sink_has_audio)
1554 tda998x_configure_audio(priv, &priv->audio_params);
1555 }
1556
1557 mutex_unlock(&priv->audio_mutex);
1558 }
1559
1560 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1561 .attach = tda998x_bridge_attach,
1562 .detach = tda998x_bridge_detach,
1563 .mode_valid = tda998x_bridge_mode_valid,
1564 .disable = tda998x_bridge_disable,
1565 .mode_set = tda998x_bridge_mode_set,
1566 .enable = tda998x_bridge_enable,
1567 };
1568
1569 /* I2C driver functions */
1570
1571 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1572 struct device_node *np)
1573 {
1574 const u32 *port_data;
1575 u32 size;
1576 int i;
1577
1578 port_data = of_get_property(np, "audio-ports", &size);
1579 if (!port_data)
1580 return 0;
1581
1582 size /= sizeof(u32);
1583 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1584 dev_err(&priv->hdmi->dev,
1585 "Bad number of elements in audio-ports dt-property\n");
1586 return -EINVAL;
1587 }
1588
1589 size /= 2;
1590
1591 for (i = 0; i < size; i++) {
1592 u8 afmt = be32_to_cpup(&port_data[2*i]);
1593 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1594
1595 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1596 dev_err(&priv->hdmi->dev,
1597 "Bad audio format %u\n", afmt);
1598 return -EINVAL;
1599 }
1600
1601 priv->audio_port[i].format = afmt;
1602 priv->audio_port[i].config = ena_ap;
1603 }
1604
1605 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1606 dev_err(&priv->hdmi->dev,
1607 "There can only be on I2S port and one SPDIF port\n");
1608 return -EINVAL;
1609 }
1610 return 0;
1611 }
1612
1613 static void tda998x_set_config(struct tda998x_priv *priv,
1614 const struct tda998x_encoder_params *p)
1615 {
1616 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1617 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1618 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1619 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1620 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1621 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1622 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1623 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1624 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1625 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1626 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1627 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1628
1629 priv->audio_params = p->audio_params;
1630 }
1631
1632 static void tda998x_destroy(struct device *dev)
1633 {
1634 struct tda998x_priv *priv = dev_get_drvdata(dev);
1635
1636 drm_bridge_remove(&priv->bridge);
1637
1638 /* disable all IRQs and free the IRQ handler */
1639 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1640 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1641
1642 if (priv->audio_pdev)
1643 platform_device_unregister(priv->audio_pdev);
1644
1645 if (priv->hdmi->irq)
1646 free_irq(priv->hdmi->irq, priv);
1647
1648 del_timer_sync(&priv->edid_delay_timer);
1649 cancel_work_sync(&priv->detect_work);
1650
1651 i2c_unregister_device(priv->cec);
1652
1653 if (priv->cec_notify)
1654 cec_notifier_put(priv->cec_notify);
1655 }
1656
1657 static int tda998x_create(struct device *dev)
1658 {
1659 struct i2c_client *client = to_i2c_client(dev);
1660 struct device_node *np = client->dev.of_node;
1661 struct i2c_board_info cec_info;
1662 struct tda998x_priv *priv;
1663 u32 video;
1664 int rev_lo, rev_hi, ret;
1665
1666 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1667 if (!priv)
1668 return -ENOMEM;
1669
1670 dev_set_drvdata(dev, priv);
1671
1672 mutex_init(&priv->mutex); /* protect the page access */
1673 mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1674 mutex_init(&priv->edid_mutex);
1675 INIT_LIST_HEAD(&priv->bridge.list);
1676 init_waitqueue_head(&priv->edid_delay_waitq);
1677 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1678 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1679
1680 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1681 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1682 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1683
1684 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1685 priv->cec_addr = 0x34 + (client->addr & 0x03);
1686 priv->current_page = 0xff;
1687 priv->hdmi = client;
1688
1689 /* wake up the device: */
1690 cec_write(priv, REG_CEC_ENAMODS,
1691 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1692
1693 tda998x_reset(priv);
1694
1695 /* read version: */
1696 rev_lo = reg_read(priv, REG_VERSION_LSB);
1697 if (rev_lo < 0) {
1698 dev_err(dev, "failed to read version: %d\n", rev_lo);
1699 return rev_lo;
1700 }
1701
1702 rev_hi = reg_read(priv, REG_VERSION_MSB);
1703 if (rev_hi < 0) {
1704 dev_err(dev, "failed to read version: %d\n", rev_hi);
1705 return rev_hi;
1706 }
1707
1708 priv->rev = rev_lo | rev_hi << 8;
1709
1710 /* mask off feature bits: */
1711 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1712
1713 switch (priv->rev) {
1714 case TDA9989N2:
1715 dev_info(dev, "found TDA9989 n2");
1716 break;
1717 case TDA19989:
1718 dev_info(dev, "found TDA19989");
1719 break;
1720 case TDA19989N2:
1721 dev_info(dev, "found TDA19989 n2");
1722 break;
1723 case TDA19988:
1724 dev_info(dev, "found TDA19988");
1725 break;
1726 default:
1727 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1728 return -ENXIO;
1729 }
1730
1731 /* after reset, enable DDC: */
1732 reg_write(priv, REG_DDC_DISABLE, 0x00);
1733
1734 /* set clock on DDC channel: */
1735 reg_write(priv, REG_TX3, 39);
1736
1737 /* if necessary, disable multi-master: */
1738 if (priv->rev == TDA19989)
1739 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1740
1741 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1742 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1743
1744 /* ensure interrupts are disabled */
1745 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1746
1747 /* clear pending interrupts */
1748 cec_read(priv, REG_CEC_RXSHPDINT);
1749 reg_read(priv, REG_INT_FLAGS_0);
1750 reg_read(priv, REG_INT_FLAGS_1);
1751 reg_read(priv, REG_INT_FLAGS_2);
1752
1753 /* initialize the optional IRQ */
1754 if (client->irq) {
1755 unsigned long irq_flags;
1756
1757 /* init read EDID waitqueue and HDP work */
1758 init_waitqueue_head(&priv->wq_edid);
1759
1760 irq_flags =
1761 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1762
1763 priv->cec_glue.irq_flags = irq_flags;
1764
1765 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1766 ret = request_threaded_irq(client->irq, NULL,
1767 tda998x_irq_thread, irq_flags,
1768 "tda998x", priv);
1769 if (ret) {
1770 dev_err(dev, "failed to request IRQ#%u: %d\n",
1771 client->irq, ret);
1772 goto err_irq;
1773 }
1774
1775 /* enable HPD irq */
1776 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1777 }
1778
1779 priv->cec_notify = cec_notifier_get(dev);
1780 if (!priv->cec_notify) {
1781 ret = -ENOMEM;
1782 goto fail;
1783 }
1784
1785 priv->cec_glue.parent = dev;
1786 priv->cec_glue.data = priv;
1787 priv->cec_glue.init = tda998x_cec_hook_init;
1788 priv->cec_glue.exit = tda998x_cec_hook_exit;
1789 priv->cec_glue.open = tda998x_cec_hook_open;
1790 priv->cec_glue.release = tda998x_cec_hook_release;
1791
1792 /*
1793 * Some TDA998x are actually two I2C devices merged onto one piece
1794 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1795 * with a slightly modified TDA9950 CEC device. The CEC device
1796 * is at the TDA9950 address, with the address pins strapped across
1797 * to the TDA998x address pins. Hence, it always has the same
1798 * offset.
1799 */
1800 memset(&cec_info, 0, sizeof(cec_info));
1801 strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1802 cec_info.addr = priv->cec_addr;
1803 cec_info.platform_data = &priv->cec_glue;
1804 cec_info.irq = client->irq;
1805
1806 priv->cec = i2c_new_device(client->adapter, &cec_info);
1807 if (!priv->cec) {
1808 ret = -ENODEV;
1809 goto fail;
1810 }
1811
1812 /* enable EDID read irq: */
1813 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1814
1815 if (np) {
1816 /* get the device tree parameters */
1817 ret = of_property_read_u32(np, "video-ports", &video);
1818 if (ret == 0) {
1819 priv->vip_cntrl_0 = video >> 16;
1820 priv->vip_cntrl_1 = video >> 8;
1821 priv->vip_cntrl_2 = video;
1822 }
1823
1824 ret = tda998x_get_audio_ports(priv, np);
1825 if (ret)
1826 goto fail;
1827
1828 if (priv->audio_port[0].format != AFMT_UNUSED)
1829 tda998x_audio_codec_init(priv, &client->dev);
1830 } else if (dev->platform_data) {
1831 tda998x_set_config(priv, dev->platform_data);
1832 }
1833
1834 priv->bridge.funcs = &tda998x_bridge_funcs;
1835 #ifdef CONFIG_OF
1836 priv->bridge.of_node = dev->of_node;
1837 #endif
1838
1839 drm_bridge_add(&priv->bridge);
1840
1841 return 0;
1842
1843 fail:
1844 tda998x_destroy(dev);
1845 err_irq:
1846 return ret;
1847 }
1848
1849 /* DRM encoder functions */
1850
1851 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1852 {
1853 drm_encoder_cleanup(encoder);
1854 }
1855
1856 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1857 .destroy = tda998x_encoder_destroy,
1858 };
1859
1860 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
1861 {
1862 struct tda998x_priv *priv = dev_get_drvdata(dev);
1863 u32 crtcs = 0;
1864 int ret;
1865
1866 if (dev->of_node)
1867 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1868
1869 /* If no CRTCs were found, fall back to our old behaviour */
1870 if (crtcs == 0) {
1871 dev_warn(dev, "Falling back to first CRTC\n");
1872 crtcs = 1 << 0;
1873 }
1874
1875 priv->encoder.possible_crtcs = crtcs;
1876
1877 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1878 DRM_MODE_ENCODER_TMDS, NULL);
1879 if (ret)
1880 goto err_encoder;
1881
1882 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
1883 if (ret)
1884 goto err_bridge;
1885
1886 return 0;
1887
1888 err_bridge:
1889 drm_encoder_cleanup(&priv->encoder);
1890 err_encoder:
1891 return ret;
1892 }
1893
1894 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1895 {
1896 struct drm_device *drm = data;
1897
1898 return tda998x_encoder_init(dev, drm);
1899 }
1900
1901 static void tda998x_unbind(struct device *dev, struct device *master,
1902 void *data)
1903 {
1904 struct tda998x_priv *priv = dev_get_drvdata(dev);
1905
1906 drm_encoder_cleanup(&priv->encoder);
1907 }
1908
1909 static const struct component_ops tda998x_ops = {
1910 .bind = tda998x_bind,
1911 .unbind = tda998x_unbind,
1912 };
1913
1914 static int
1915 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1916 {
1917 int ret;
1918
1919 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1920 dev_warn(&client->dev, "adapter does not support I2C\n");
1921 return -EIO;
1922 }
1923
1924 ret = tda998x_create(&client->dev);
1925 if (ret)
1926 return ret;
1927
1928 ret = component_add(&client->dev, &tda998x_ops);
1929 if (ret)
1930 tda998x_destroy(&client->dev);
1931 return ret;
1932 }
1933
1934 static int tda998x_remove(struct i2c_client *client)
1935 {
1936 component_del(&client->dev, &tda998x_ops);
1937 tda998x_destroy(&client->dev);
1938 return 0;
1939 }
1940
1941 #ifdef CONFIG_OF
1942 static const struct of_device_id tda998x_dt_ids[] = {
1943 { .compatible = "nxp,tda998x", },
1944 { }
1945 };
1946 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1947 #endif
1948
1949 static const struct i2c_device_id tda998x_ids[] = {
1950 { "tda998x", 0 },
1951 { }
1952 };
1953 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1954
1955 static struct i2c_driver tda998x_driver = {
1956 .probe = tda998x_probe,
1957 .remove = tda998x_remove,
1958 .driver = {
1959 .name = "tda998x",
1960 .of_match_table = of_match_ptr(tda998x_dt_ids),
1961 },
1962 .id_table = tda998x_ids,
1963 };
1964
1965 module_i2c_driver(tda998x_driver);
1966
1967 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1968 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1969 MODULE_LICENSE("GPL");
Linux with added FPC-III support