drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / meson / meson_canvas.c
blob08f6073d967e04ce2e0f89650f656d08d953f9aa
1 /*
2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 * Copyright (C) 2014 Endless Mobile
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include "meson_drv.h"
24 #include "meson_canvas.h"
25 #include "meson_registers.h"
27 /**
28 * DOC: Canvas
30 * CANVAS is a memory zone where physical memory frames information
31 * are stored for the VIU to scanout.
34 /* DMC Registers */
35 #define DMC_CAV_LUT_DATAL 0x48 /* 0x12 offset in data sheet */
36 #define CANVAS_WIDTH_LBIT 29
37 #define CANVAS_WIDTH_LWID 3
38 #define DMC_CAV_LUT_DATAH 0x4c /* 0x13 offset in data sheet */
39 #define CANVAS_WIDTH_HBIT 0
40 #define CANVAS_HEIGHT_BIT 9
41 #define CANVAS_BLKMODE_BIT 24
42 #define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
43 #define CANVAS_LUT_WR_EN (0x2 << 8)
44 #define CANVAS_LUT_RD_EN (0x1 << 8)
46 void meson_canvas_setup(struct meson_drm *priv,
47 uint32_t canvas_index, uint32_t addr,
48 uint32_t stride, uint32_t height,
49 unsigned int wrap,
50 unsigned int blkmode)
52 unsigned int val;
54 regmap_write(priv->dmc, DMC_CAV_LUT_DATAL,
55 (((addr + 7) >> 3)) |
56 (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
58 regmap_write(priv->dmc, DMC_CAV_LUT_DATAH,
59 ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
60 CANVAS_WIDTH_HBIT) |
61 (height << CANVAS_HEIGHT_BIT) |
62 (wrap << 22) |
63 (blkmode << CANVAS_BLKMODE_BIT));
65 regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,
66 CANVAS_LUT_WR_EN | canvas_index);
68 /* Force a read-back to make sure everything is flushed. */
69 regmap_read(priv->dmc, DMC_CAV_LUT_DATAH, &val);