drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / meson / meson_drv.h
blob8450d6ac8c9bc1dcd049fd8c2205d1c5a8c7c924
1 /*
2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of the
8 * License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef __MESON_DRV_H
20 #define __MESON_DRV_H
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/of.h>
25 #include <drm/drmP.h>
27 struct meson_drm {
28 struct device *dev;
29 void __iomem *io_base;
30 struct regmap *hhi;
31 struct regmap *dmc;
32 int vsync_irq;
34 struct drm_device *drm;
35 struct drm_crtc *crtc;
36 struct drm_fbdev_cma *fbdev;
37 struct drm_plane *primary_plane;
39 /* Components Data */
40 struct {
41 bool osd1_enabled;
42 bool osd1_interlace;
43 bool osd1_commit;
44 uint32_t osd1_ctrl_stat;
45 uint32_t osd1_blk0_cfg[5];
46 uint32_t osd1_addr;
47 uint32_t osd1_stride;
48 uint32_t osd1_height;
49 } viu;
51 struct {
52 unsigned int current_mode;
53 bool hdmi_repeat;
54 bool venc_repeat;
55 bool hdmi_use_enci;
56 } venc;
59 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
60 const char *compat)
62 return of_device_is_compatible(priv->dev->of_node, compat);
65 #endif /* __MESON_DRV_H */