drivers/gpu/drm/meson/meson_vclk.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <drm/drmP.h>
  23 #include "meson_drv.h"
  24 #include "meson_vclk.h"
  25
  26 /**
  27  * DOC: Video Clocks
  28  *
  29  * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
  30  * We handle the following encodings :
  31  *
  32  * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
  33  * - HDMI Pixel Clocks generation
  34  *
  35  * What is missing :
  36  *
  37  * - Genenate Pixel clocks for 2K/4K 10bit formats
  38  *
  39  * Clock generator scheme :
  40  *
  41  * .. code::
  42  *
  43  *    __________   _________            _____
  44  *   |          | |         |          |     |--ENCI
  45  *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL
  46  *   |__________| |_________| \        | MUX |--ENCP
  47  *                             --VCLK2-|     |--VDAC
  48  *                                     |_____|--HDMI-TX
  49  *
  50  * Final clocks can take input for either VCLK or VCLK2, but
  51  * VCLK is the preferred path for HDMI clocking and VCLK2 is the
  52  * preferred path for CVBS VDAC clocking.
  53  *
  54  * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
  55  *
  56  * The PLL_DIV can achieve an additional fractional dividing like
  57  * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
  58  */
  59
  60 /* HHI Registers */
  61 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  62 #define VID_PLL_EN              BIT(19)
  63 #define VID_PLL_BYPASS          BIT(18)
  64 #define VID_PLL_PRESET          BIT(15)
  65 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  66 #define VCLK2_DIV_MASK          0xff
  67 #define VCLK2_DIV_EN            BIT(16)
  68 #define VCLK2_DIV_RESET         BIT(17)
  69 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  70 #define CTS_VDAC_SEL_SHIFT      28
  71 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  72 #define VCLK2_EN                BIT(19)
  73 #define VCLK2_SEL_MASK          (0x7 << 16)
  74 #define VCLK2_SEL_SHIFT         16
  75 #define VCLK2_SOFT_RESET        BIT(15)
  76 #define VCLK2_DIV1_EN           BIT(0)
  77 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  78 #define VCLK_DIV_MASK           0xff
  79 #define VCLK_DIV_EN             BIT(16)
  80 #define VCLK_DIV_RESET          BIT(17)
  81 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  82 #define CTS_ENCP_SEL_SHIFT      24
  83 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  84 #define CTS_ENCI_SEL_SHIFT      28
  85 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  86 #define VCLK_EN                 BIT(19)
  87 #define VCLK_SEL_MASK           (0x7 << 16)
  88 #define VCLK_SEL_SHIFT          16
  89 #define VCLK_SOFT_RESET         BIT(15)
  90 #define VCLK_DIV1_EN            BIT(0)
  91 #define VCLK_DIV2_EN            BIT(1)
  92 #define VCLK_DIV4_EN            BIT(2)
  93 #define VCLK_DIV6_EN            BIT(3)
  94 #define VCLK_DIV12_EN           BIT(4)
  95 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  96 #define CTS_ENCI_EN             BIT(0)
  97 #define CTS_ENCP_EN             BIT(2)
  98 #define CTS_VDAC_EN             BIT(4)
  99 #define HDMI_TX_PIXEL_EN        BIT(5)
 100 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
 101 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
 102 #define HDMI_TX_PIXEL_SEL_SHIFT 16
 103 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
 104 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
 105 #define CTS_HDMI_SYS_EN         BIT(8)
 106
 107 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
 108 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
 109
 110 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
 111 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
 112 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
 113 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
 114 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
 115 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
 116
 117 #define HDMI_PLL_RESET          BIT(28)
 118 #define HDMI_PLL_LOCK           BIT(31)
 119
 120 /* VID PLL Dividers */
 121 enum {
 122         VID_PLL_DIV_1 = 0,
 123         VID_PLL_DIV_2,
 124         VID_PLL_DIV_2p5,
 125         VID_PLL_DIV_3,
 126         VID_PLL_DIV_3p5,
 127         VID_PLL_DIV_3p75,
 128         VID_PLL_DIV_4,
 129         VID_PLL_DIV_5,
 130         VID_PLL_DIV_6,
 131         VID_PLL_DIV_6p25,
 132         VID_PLL_DIV_7,
 133         VID_PLL_DIV_7p5,
 134         VID_PLL_DIV_12,
 135         VID_PLL_DIV_14,
 136         VID_PLL_DIV_15,
 137 };
 138
 139 void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 140 {
 141         unsigned int shift_val = 0;
 142         unsigned int shift_sel = 0;
 143
 144         /* Disable vid_pll output clock */
 145         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 146         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 147
 148         switch (div) {
 149         case VID_PLL_DIV_2:
 150                 shift_val = 0x0aaa;
 151                 shift_sel = 0;
 152                 break;
 153         case VID_PLL_DIV_2p5:
 154                 shift_val = 0x5294;
 155                 shift_sel = 2;
 156                 break;
 157         case VID_PLL_DIV_3:
 158                 shift_val = 0x0db6;
 159                 shift_sel = 0;
 160                 break;
 161         case VID_PLL_DIV_3p5:
 162                 shift_val = 0x36cc;
 163                 shift_sel = 1;
 164                 break;
 165         case VID_PLL_DIV_3p75:
 166                 shift_val = 0x6666;
 167                 shift_sel = 2;
 168                 break;
 169         case VID_PLL_DIV_4:
 170                 shift_val = 0x0ccc;
 171                 shift_sel = 0;
 172                 break;
 173         case VID_PLL_DIV_5:
 174                 shift_val = 0x739c;
 175                 shift_sel = 2;
 176                 break;
 177         case VID_PLL_DIV_6:
 178                 shift_val = 0x0e38;
 179                 shift_sel = 0;
 180                 break;
 181         case VID_PLL_DIV_6p25:
 182                 shift_val = 0x0000;
 183                 shift_sel = 3;
 184                 break;
 185         case VID_PLL_DIV_7:
 186                 shift_val = 0x3c78;
 187                 shift_sel = 1;
 188                 break;
 189         case VID_PLL_DIV_7p5:
 190                 shift_val = 0x78f0;
 191                 shift_sel = 2;
 192                 break;
 193         case VID_PLL_DIV_12:
 194                 shift_val = 0x0fc0;
 195                 shift_sel = 0;
 196                 break;
 197         case VID_PLL_DIV_14:
 198                 shift_val = 0x3f80;
 199                 shift_sel = 1;
 200                 break;
 201         case VID_PLL_DIV_15:
 202                 shift_val = 0x7f80;
 203                 shift_sel = 2;
 204                 break;
 205         }
 206
 207         if (div == VID_PLL_DIV_1)
 208                 /* Enable vid_pll bypass to HDMI pll */
 209                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 210                                    VID_PLL_BYPASS, VID_PLL_BYPASS);
 211         else {
 212                 /* Disable Bypass */
 213                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 214                                    VID_PLL_BYPASS, 0);
 215                 /* Clear sel */
 216                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 217                                    3 << 16, 0);
 218                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 219                                    VID_PLL_PRESET, 0);
 220                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 221                                    0x7fff, 0);
 222
 223                 /* Setup sel and val */
 224                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 225                                    3 << 16, shift_sel << 16);
 226                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 227                                    VID_PLL_PRESET, VID_PLL_PRESET);
 228                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 229                                    0x7fff, shift_val);
 230
 231                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 232                                    VID_PLL_PRESET, 0);
 233         }
 234
 235         /* Enable the vid_pll output clock */
 236         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 237                                 VID_PLL_EN, VID_PLL_EN);
 238 }
 239
 240 /*
 241  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 242  *
 243  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 244  */
 245 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 246 {
 247         unsigned int val;
 248
 249         /* Setup PLL to output 1.485GHz */
 250         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 251                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
 252                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
 253                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 254                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 255                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 256                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 257                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
 258         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 259                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 260                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
 261                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
 262                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
 263                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 264                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 265                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 266
 267                 /* Reset PLL */
 268                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 269                                         HDMI_PLL_RESET, HDMI_PLL_RESET);
 270                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 271                                         HDMI_PLL_RESET, 0);
 272         }
 273
 274         /* Poll for lock bit */
 275         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 276                                  (val & HDMI_PLL_LOCK), 10, 0);
 277
 278         /* Disable VCLK2 */
 279         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 280
 281         /* Setup vid_pll to /1 */
 282         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 283
 284         /* Setup the VCLK2 divider value to achieve 27MHz */
 285         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 286                                 VCLK2_DIV_MASK, (55 - 1));
 287
 288         /* select vid_pll for vclk2 */
 289         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 290                                 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 291         /* enable vclk2 gate */
 292         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 293
 294         /* select vclk_div1 for enci */
 295         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 296                                 CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 297         /* select vclk_div1 for vdac */
 298         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 299                                 CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 300
 301         /* release vclk2_div_reset and enable vclk2_div */
 302         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 303                                 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 304
 305         /* enable vclk2_div1 gate */
 306         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 307                                 VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 308
 309         /* reset vclk2 */
 310         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 311                                 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 312         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 313                                 VCLK2_SOFT_RESET, 0);
 314
 315         /* enable enci_clk */
 316         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 317                                 CTS_ENCI_EN, CTS_ENCI_EN);
 318         /* enable vdac_clk */
 319         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 320                                 CTS_VDAC_EN, CTS_VDAC_EN);
 321 }
 322
 323 enum {
 324 /* PLL  O1 O2 O3 VP DV     EN TX */
 325 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 326         MESON_VCLK_HDMI_ENCI_54000 = 1,
 327 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 328         MESON_VCLK_HDMI_DDR_54000,
 329 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 330         MESON_VCLK_HDMI_DDR_148500,
 331 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 332         MESON_VCLK_HDMI_74250,
 333 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 334         MESON_VCLK_HDMI_148500,
 335 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 336         MESON_VCLK_HDMI_297000,
 337 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 338         MESON_VCLK_HDMI_594000
 339 };
 340
 341 struct meson_vclk_params {
 342         unsigned int pll_base_freq;
 343         unsigned int pll_od1;
 344         unsigned int pll_od2;
 345         unsigned int pll_od3;
 346         unsigned int vid_pll_div;
 347         unsigned int vclk_div;
 348 } params[] = {
 349         [MESON_VCLK_HDMI_ENCI_54000] = {
 350                 .pll_base_freq = 4320000,
 351                 .pll_od1 = 4,
 352                 .pll_od2 = 4,
 353                 .pll_od3 = 1,
 354                 .vid_pll_div = VID_PLL_DIV_5,
 355                 .vclk_div = 1,
 356         },
 357         [MESON_VCLK_HDMI_DDR_54000] = {
 358                 .pll_base_freq = 4320000,
 359                 .pll_od1 = 4,
 360                 .pll_od2 = 4,
 361                 .pll_od3 = 1,
 362                 .vid_pll_div = VID_PLL_DIV_5,
 363                 .vclk_div = 1,
 364         },
 365         [MESON_VCLK_HDMI_DDR_148500] = {
 366                 .pll_base_freq = 2970000,
 367                 .pll_od1 = 4,
 368                 .pll_od2 = 1,
 369                 .pll_od3 = 1,
 370                 .vid_pll_div = VID_PLL_DIV_5,
 371                 .vclk_div = 1,
 372         },
 373         [MESON_VCLK_HDMI_74250] = {
 374                 .pll_base_freq = 2970000,
 375                 .pll_od1 = 2,
 376                 .pll_od2 = 2,
 377                 .pll_od3 = 2,
 378                 .vid_pll_div = VID_PLL_DIV_5,
 379                 .vclk_div = 1,
 380         },
 381         [MESON_VCLK_HDMI_148500] = {
 382                 .pll_base_freq = 2970000,
 383                 .pll_od1 = 1,
 384                 .pll_od2 = 2,
 385                 .pll_od3 = 2,
 386                 .vid_pll_div = VID_PLL_DIV_5,
 387                 .vclk_div = 1,
 388         },
 389         [MESON_VCLK_HDMI_297000] = {
 390                 .pll_base_freq = 2970000,
 391                 .pll_od1 = 1,
 392                 .pll_od2 = 1,
 393                 .pll_od3 = 1,
 394                 .vid_pll_div = VID_PLL_DIV_5,
 395                 .vclk_div = 2,
 396         },
 397         [MESON_VCLK_HDMI_594000] = {
 398                 .pll_base_freq = 5940000,
 399                 .pll_od1 = 1,
 400                 .pll_od2 = 1,
 401                 .pll_od3 = 2,
 402                 .vid_pll_div = VID_PLL_DIV_5,
 403                 .vclk_div = 1,
 404         },
 405 };
 406
 407 static inline unsigned int pll_od_to_reg(unsigned int od)
 408 {
 409         switch (od) {
 410         case 1:
 411                 return 0;
 412         case 2:
 413                 return 1;
 414         case 4:
 415                 return 2;
 416         case 8:
 417                 return 3;
 418         }
 419
 420         /* Invalid */
 421         return 0;
 422 }
 423
 424 void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
 425                                unsigned int frac, unsigned int od1,
 426                                unsigned int od2, unsigned int od3)
 427 {
 428         unsigned int val;
 429
 430         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 431                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
 432                 if (frac)
 433                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 434                                      0x00004000 | frac);
 435                 else
 436                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 437                                      0x00000000);
 438                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 439                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 440                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 441                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 442
 443                 /* Enable and unreset */
 444                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 445                                    0x7 << 28, 0x4 << 28);
 446
 447                 /* Poll for lock bit */
 448                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 449                                          val, (val & HDMI_PLL_LOCK), 10, 0);
 450         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 451                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 452                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
 453                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
 454                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 455                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 456                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 457                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 458
 459                 /* Reset PLL */
 460                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 461                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 462                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 463                                 HDMI_PLL_RESET, 0);
 464
 465                 /* Poll for lock bit */
 466                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 467                                 (val & HDMI_PLL_LOCK), 10, 0);
 468         }
 469
 470         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 471                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 472                                 3 << 16, pll_od_to_reg(od1) << 16);
 473         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 474                         meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 475                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 476                                 3 << 21, pll_od_to_reg(od1) << 21);
 477
 478         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 479                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 480                                 3 << 22, pll_od_to_reg(od2) << 22);
 481         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 482                         meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 483                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 484                                 3 << 23, pll_od_to_reg(od2) << 23);
 485
 486         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 487                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 488                                 3 << 18, pll_od_to_reg(od3) << 18);
 489         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 490                         meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 491                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 492                                 3 << 19, pll_od_to_reg(od3) << 19);
 493
 494 }
 495
 496 #define XTAL_FREQ 24000
 497
 498 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
 499                                          unsigned int pll_freq)
 500 {
 501         /* The GXBB PLL has a /2 pre-multiplier */
 502         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 503                 pll_freq /= 2;
 504
 505         return pll_freq / XTAL_FREQ;
 506 }
 507
 508 #define HDMI_FRAC_MAX_GXBB      4096
 509 #define HDMI_FRAC_MAX_GXL       1024
 510
 511 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
 512                                             unsigned int m,
 513                                             unsigned int pll_freq)
 514 {
 515         unsigned int parent_freq = XTAL_FREQ;
 516         unsigned int frac_max = HDMI_FRAC_MAX_GXL;
 517         unsigned int frac_m;
 518         unsigned int frac;
 519
 520         /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
 521         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 522                 frac_max = HDMI_FRAC_MAX_GXBB;
 523                 parent_freq *= 2;
 524         }
 525
 526         /* We can have a perfect match !*/
 527         if (pll_freq / m == parent_freq &&
 528             pll_freq % m == 0)
 529                 return 0;
 530
 531         frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
 532         frac_m = m * frac_max;
 533         if (frac_m > frac)
 534                 return frac_max;
 535         frac -= frac_m;
 536
 537         return min((u16)frac, (u16)(frac_max - 1));
 538 }
 539
 540 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
 541                                            unsigned int m,
 542                                            unsigned int frac)
 543 {
 544         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 545                 /* Empiric supported min/max dividers */
 546                 if (m < 53 || m > 123)
 547                         return false;
 548                 if (frac >= HDMI_FRAC_MAX_GXBB)
 549                         return false;
 550         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 551                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 552                 /* Empiric supported min/max dividers */
 553                 if (m < 106 || m > 247)
 554                         return false;
 555                 if (frac >= HDMI_FRAC_MAX_GXL)
 556                         return false;
 557         }
 558
 559         return true;
 560 }
 561
 562 static bool meson_hdmi_pll_find_params(struct meson_drm *priv,
 563                                        unsigned int freq,
 564                                        unsigned int *m,
 565                                        unsigned int *frac,
 566                                        unsigned int *od)
 567 {
 568         /* Cycle from /16 to /2 */
 569         for (*od = 16 ; *od > 1 ; *od >>= 1) {
 570                 *m = meson_hdmi_pll_get_m(priv, freq * *od);
 571                 if (!*m)
 572                         continue;
 573                 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
 574
 575                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",
 576                                  freq, *m, *frac, *od);
 577
 578                 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
 579                         return true;
 580         }
 581
 582         return false;
 583 }
 584
 585 /* pll_freq is the frequency after the OD dividers */
 586 enum drm_mode_status
 587 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
 588 {
 589         unsigned int od, m, frac;
 590
 591         /* In DMT mode, path after PLL is always /10 */
 592         freq *= 10;
 593
 594         if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
 595                 return MODE_OK;
 596
 597         return MODE_CLOCK_RANGE;
 598 }
 599 EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq);
 600
 601 /* pll_freq is the frequency after the OD dividers */
 602 static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
 603                                        unsigned int pll_freq)
 604 {
 605         unsigned int od, m, frac, od1, od2, od3;
 606
 607         if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
 608                 od3 = 1;
 609                 if (od < 4) {
 610                         od1 = 2;
 611                         od2 = 1;
 612                 } else {
 613                         od2 = od / 4;
 614                         od1 = od / od2;
 615                 }
 616
 617                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
 618                                  pll_freq, m, frac, od1, od2, od3);
 619
 620                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 621
 622                 return;
 623         }
 624
 625         DRM_ERROR("Fatal, unable to find parameters for PLL freq %d\n",
 626                   pll_freq);
 627 }
 628
 629 static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 630                            unsigned int od1, unsigned int od2, unsigned int od3,
 631                            unsigned int vid_pll_div, unsigned int vclk_div,
 632                            unsigned int hdmi_tx_div, unsigned int venc_div,
 633                            bool hdmi_use_enci)
 634 {
 635         /* Set HDMI-TX sys clock */
 636         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 637                            CTS_HDMI_SYS_SEL_MASK, 0);
 638         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 639                            CTS_HDMI_SYS_DIV_MASK, 0);
 640         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 641                            CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 642
 643         /* Set HDMI PLL rate */
 644         if (!od1 && !od2 && !od3) {
 645                 meson_hdmi_pll_generic_set(priv, pll_base_freq);
 646         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 647                 switch (pll_base_freq) {
 648                 case 2970000:
 649                         meson_hdmi_pll_set_params(priv, 0x3d, 0xe00,
 650                                                   od1, od2, od3);
 651                         break;
 652                 case 4320000:
 653                         meson_hdmi_pll_set_params(priv, 0x5a, 0,
 654                                                   od1, od2, od3);
 655                         break;
 656                 case 5940000:
 657                         meson_hdmi_pll_set_params(priv, 0x7b, 0xc00,
 658                                                   od1, od2, od3);
 659                         break;
 660                 }
 661         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 662                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 663                 switch (pll_base_freq) {
 664                 case 2970000:
 665                         meson_hdmi_pll_set_params(priv, 0x7b, 0x300,
 666                                                   od1, od2, od3);
 667                         break;
 668                 case 4320000:
 669                         meson_hdmi_pll_set_params(priv, 0xb4, 0,
 670                                                   od1, od2, od3);
 671                         break;
 672                 case 5940000:
 673                         meson_hdmi_pll_set_params(priv, 0xf7, 0x200,
 674                                                   od1, od2, od3);
 675                         break;
 676                 }
 677         }
 678
 679         /* Setup vid_pll divider */
 680         meson_vid_pll_set(priv, vid_pll_div);
 681
 682         /* Set VCLK div */
 683         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 684                            VCLK_SEL_MASK, 0);
 685         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 686                            VCLK_DIV_MASK, vclk_div - 1);
 687
 688         /* Set HDMI-TX source */
 689         switch (hdmi_tx_div) {
 690         case 1:
 691                 /* enable vclk_div1 gate */
 692                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 693                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 694
 695                 /* select vclk_div1 for HDMI-TX */
 696                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 697                                    HDMI_TX_PIXEL_SEL_MASK, 0);
 698                 break;
 699         case 2:
 700                 /* enable vclk_div2 gate */
 701                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 702                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 703
 704                 /* select vclk_div2 for HDMI-TX */
 705                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 706                         HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 707                 break;
 708         case 4:
 709                 /* enable vclk_div4 gate */
 710                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 711                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 712
 713                 /* select vclk_div4 for HDMI-TX */
 714                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 715                         HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 716                 break;
 717         case 6:
 718                 /* enable vclk_div6 gate */
 719                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 720                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 721
 722                 /* select vclk_div6 for HDMI-TX */
 723                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 724                         HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 725                 break;
 726         case 12:
 727                 /* enable vclk_div12 gate */
 728                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 729                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 730
 731                 /* select vclk_div12 for HDMI-TX */
 732                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 733                         HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 734                 break;
 735         }
 736         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 737                                    HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 738
 739         /* Set ENCI/ENCP Source */
 740         switch (venc_div) {
 741         case 1:
 742                 /* enable vclk_div1 gate */
 743                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 744                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 745
 746                 if (hdmi_use_enci)
 747                         /* select vclk_div1 for enci */
 748                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 749                                            CTS_ENCI_SEL_MASK, 0);
 750                 else
 751                         /* select vclk_div1 for encp */
 752                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 753                                            CTS_ENCP_SEL_MASK, 0);
 754                 break;
 755         case 2:
 756                 /* enable vclk_div2 gate */
 757                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 758                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 759
 760                 if (hdmi_use_enci)
 761                         /* select vclk_div2 for enci */
 762                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 763                                 CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
 764                 else
 765                         /* select vclk_div2 for encp */
 766                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 767                                 CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
 768                 break;
 769         case 4:
 770                 /* enable vclk_div4 gate */
 771                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 772                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 773
 774                 if (hdmi_use_enci)
 775                         /* select vclk_div4 for enci */
 776                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 777                                 CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
 778                 else
 779                         /* select vclk_div4 for encp */
 780                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 781                                 CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
 782                 break;
 783         case 6:
 784                 /* enable vclk_div6 gate */
 785                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 786                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 787
 788                 if (hdmi_use_enci)
 789                         /* select vclk_div6 for enci */
 790                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 791                                 CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
 792                 else
 793                         /* select vclk_div6 for encp */
 794                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 795                                 CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
 796                 break;
 797         case 12:
 798                 /* enable vclk_div12 gate */
 799                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 800                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 801
 802                 if (hdmi_use_enci)
 803                         /* select vclk_div12 for enci */
 804                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 805                                 CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
 806                 else
 807                         /* select vclk_div12 for encp */
 808                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 809                                 CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
 810                 break;
 811         }
 812
 813         if (hdmi_use_enci)
 814                 /* Enable ENCI clock gate */
 815                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 816                                    CTS_ENCI_EN, CTS_ENCI_EN);
 817         else
 818                 /* Enable ENCP clock gate */
 819                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 820                                    CTS_ENCP_EN, CTS_ENCP_EN);
 821
 822         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 823 }
 824
 825 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
 826                       unsigned int vclk_freq, unsigned int venc_freq,
 827                       unsigned int dac_freq, bool hdmi_use_enci)
 828 {
 829         unsigned int freq;
 830         unsigned int hdmi_tx_div;
 831         unsigned int venc_div;
 832
 833         if (target == MESON_VCLK_TARGET_CVBS) {
 834                 meson_venci_cvbs_clock_config(priv);
 835                 return;
 836         } else if (target == MESON_VCLK_TARGET_DMT) {
 837                 /* The DMT clock path is fixed after the PLL:
 838                  * - automatic PLL freq + OD management
 839                  * - vid_pll_div = VID_PLL_DIV_5
 840                  * - vclk_div = 2
 841                  * - hdmi_tx_div = 1
 842                  * - venc_div = 1
 843                  * - encp encoder
 844                  */
 845                 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
 846                                VID_PLL_DIV_5, 2, 1, 1, false);
 847                 return;
 848         }
 849
 850         hdmi_tx_div = vclk_freq / dac_freq;
 851
 852         if (hdmi_tx_div == 0) {
 853                 pr_err("Fatal Error, invalid HDMI-TX freq %d\n",
 854                        dac_freq);
 855                 return;
 856         }
 857
 858         venc_div = vclk_freq / venc_freq;
 859
 860         if (venc_div == 0) {
 861                 pr_err("Fatal Error, invalid HDMI venc freq %d\n",
 862                        venc_freq);
 863                 return;
 864         }
 865
 866         switch (vclk_freq) {
 867         case 54000:
 868                 if (hdmi_use_enci)
 869                         freq = MESON_VCLK_HDMI_ENCI_54000;
 870                 else
 871                         freq = MESON_VCLK_HDMI_DDR_54000;
 872                 break;
 873         case 74250:
 874                 freq = MESON_VCLK_HDMI_74250;
 875                 break;
 876         case 148500:
 877                 if (dac_freq != 148500)
 878                         freq = MESON_VCLK_HDMI_DDR_148500;
 879                 else
 880                         freq = MESON_VCLK_HDMI_148500;
 881                 break;
 882         case 297000:
 883                 freq = MESON_VCLK_HDMI_297000;
 884                 break;
 885         case 594000:
 886                 freq = MESON_VCLK_HDMI_594000;
 887                 break;
 888         default:
 889                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n",
 890                        vclk_freq);
 891                 return;
 892         }
 893
 894         meson_vclk_set(priv, params[freq].pll_base_freq,
 895                        params[freq].pll_od1, params[freq].pll_od2,
 896                        params[freq].pll_od3, params[freq].vid_pll_div,
 897                        params[freq].vclk_div, hdmi_tx_div, venc_div,
 898                        hdmi_use_enci);
 899 }
 900 EXPORT_SYMBOL_GPL(meson_vclk_setup);