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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / dispnv04 / hw.c
blob0c9bdf023f5b559059479232075d612172971905
1 /*
2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include <drm/drmP.h>
26 #include "nouveau_drv.h"
27 #include "hw.h"
28
29 #include <subdev/bios/pll.h>
30
31 #define CHIPSET_NFORCE 0x01a0
32 #define CHIPSET_NFORCE2 0x01f0
33
34 /*
35 * misc hw access wrappers/control functions
36 */
37
38 void
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
40 {
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
43 }
44
45 uint8_t
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
47 {
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
50 }
51
52 void
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
54 {
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
57 }
58
59 uint8_t
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
61 {
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
64 }
65
66 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
67 * it affects only the 8 bit vga io regs, which we access using mmio at
68 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
69 * in general, the set value of cr44 does not matter: reg access works as
70 * expected and values can be set for the appropriate head by using a 0x2000
71 * offset as required
72 * however:
73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
74 * cr44 must be set to 0 or 3 for accessing values on the correct head
75 * through the common 0xc03c* addresses
76 * b) in tied mode (4) head B is programmed to the values set on head A, and
77 * access using the head B addresses can have strange results, ergo we leave
78 * tied mode in init once we know to what cr44 should be restored on exit
79 *
80 * the owner parameter is slightly abused:
81 * 0 and 1 are treated as head values and so the set value is (owner * 3)
82 * other values are treated as literal values to set
83 */
84 void
85 NVSetOwner(struct drm_device *dev, int owner)
86 {
87 struct nouveau_drm *drm = nouveau_drm(dev);
88
89 if (owner == 1)
90 owner *= 3;
91
92 if (drm->client.device.info.chipset == 0x11) {
93 /* This might seem stupid, but the blob does it and
94 * omitting it often locks the system up.
95 */
96 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
97 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
98 }
99
100 /* CR44 is always changed on CRTC0 */
101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
102
103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
106 }
107 }
108
109 void
110 NVBlankScreen(struct drm_device *dev, int head, bool blank)
111 {
112 unsigned char seq1;
113
114 if (nv_two_heads(dev))
115 NVSetOwner(dev, head);
116
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
118
119 NVVgaSeqReset(dev, head, true);
120 if (blank)
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
122 else
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
124 NVVgaSeqReset(dev, head, false);
125 }
126
127 /*
128 * PLL getting
129 */
130
131 static void
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
133 uint32_t pll2, struct nvkm_pll_vals *pllvals)
134 {
135 struct nouveau_drm *drm = nouveau_drm(dev);
136
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
138
139 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
140 pllvals->log2P = (pll1 >> 16) & 0x7;
141 pllvals->N2 = pllvals->M2 = 1;
142
143 if (reg1 <= 0x405c) {
144 pllvals->NM1 = pll2 & 0xffff;
145 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
146 if (!(pll1 & 0x1100))
147 pllvals->NM2 = pll2 >> 16;
148 } else {
149 pllvals->NM1 = pll1 & 0xffff;
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
151 pllvals->NM2 = pll2 & 0xffff;
152 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) {
153 pllvals->M1 &= 0xf; /* only 4 bits */
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
155 pllvals->M2 = (pll1 >> 4) & 0x7;
156 pllvals->N2 = ((pll1 >> 21) & 0x18) |
157 ((pll1 >> 19) & 0x7);
158 }
159 }
160 }
161 }
162
163 int
164 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
165 struct nvkm_pll_vals *pllvals)
166 {
167 struct nouveau_drm *drm = nouveau_drm(dev);
168 struct nvif_object *device = &drm->client.device.object;
169 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
170 uint32_t reg1, pll1, pll2 = 0;
171 struct nvbios_pll pll_lim;
172 int ret;
173
174 ret = nvbios_pll_parse(bios, plltype, &pll_lim);
175 if (ret || !(reg1 = pll_lim.reg))
176 return -ENOENT;
177
178 pll1 = nvif_rd32(device, reg1);
179 if (reg1 <= 0x405c)
180 pll2 = nvif_rd32(device, reg1 + 4);
181 else if (nv_two_reg_pll(dev)) {
182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
183
184 pll2 = nvif_rd32(device, reg2);
185 }
186
187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
188 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
189
190 /* check whether vpll has been forced into single stage mode */
191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
192 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
193 pll2 = 0;
194 } else
195 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
196 pll2 = 0;
197 }
198
199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
200 pllvals->refclk = pll_lim.refclk;
201 return 0;
202 }
203
204 int
205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv)
206 {
207 /* Avoid divide by zero if called at an inappropriate time */
208 if (!pv->M1 || !pv->M2)
209 return 0;
210
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
212 }
213
214 int
215 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
216 {
217 struct nvkm_pll_vals pllvals;
218 int ret;
219 int domain;
220
221 domain = pci_domain_nr(dev->pdev->bus);
222
223 if (plltype == PLL_MEMORY &&
224 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
225 uint32_t mpllP;
226 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
227 0x6c, &mpllP);
228 mpllP = (mpllP >> 8) & 0xf;
229 if (!mpllP)
230 mpllP = 4;
231
232 return 400000 / mpllP;
233 } else
234 if (plltype == PLL_MEMORY &&
235 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
236 uint32_t clock;
237
238 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
239 0x4c, &clock);
240 return clock / 1000;
241 }
242
243 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
244 if (ret)
245 return ret;
246
247 return nouveau_hw_pllvals_to_clk(&pllvals);
248 }
249
250 static void
251 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
252 {
253 /* the vpll on an unused head can come up with a random value, way
254 * beyond the pll limits. for some reason this causes the chip to
255 * lock up when reading the dac palette regs, so set a valid pll here
256 * when such a condition detected. only seen on nv11 to date
257 */
258
259 struct nouveau_drm *drm = nouveau_drm(dev);
260 struct nvif_device *device = &drm->client.device;
261 struct nvkm_clk *clk = nvxx_clk(device);
262 struct nvkm_bios *bios = nvxx_bios(device);
263 struct nvbios_pll pll_lim;
264 struct nvkm_pll_vals pv;
265 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
266
267 if (nvbios_pll_parse(bios, pll, &pll_lim))
268 return;
269 nouveau_hw_get_pllvals(dev, pll, &pv);
270
271 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
272 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
273 pv.log2P <= pll_lim.max_p)
274 return;
275
276 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
277
278 /* set lowest clock within static limits */
279 pv.M1 = pll_lim.vco1.max_m;
280 pv.N1 = pll_lim.vco1.min_n;
281 pv.log2P = pll_lim.max_p_usable;
282 clk->pll_prog(clk, pll_lim.reg, &pv);
283 }
284
285 /*
286 * vga font save/restore
287 */
288
289 static void nouveau_vga_font_io(struct drm_device *dev,
290 void __iomem *iovram,
291 bool save, unsigned plane)
292 {
293 unsigned i;
294
295 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
296 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
297 for (i = 0; i < 16384; i++) {
298 if (save) {
299 nv04_display(dev)->saved_vga_font[plane][i] =
300 ioread32_native(iovram + i * 4);
301 } else {
302 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
303 iovram + i * 4);
304 }
305 }
306 }
307
308 void
309 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
310 {
311 struct nouveau_drm *drm = nouveau_drm(dev);
312 uint8_t misc, gr4, gr5, gr6, seq2, seq4;
313 bool graphicsmode;
314 unsigned plane;
315 void __iomem *iovram;
316
317 if (nv_two_heads(dev))
318 NVSetOwner(dev, 0);
319
320 NVSetEnablePalette(dev, 0, true);
321 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
322 NVSetEnablePalette(dev, 0, false);
323
324 if (graphicsmode) /* graphics mode => framebuffer => no need to save */
325 return;
326
327 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
328
329 /* map first 64KiB of VRAM, holds VGA fonts etc */
330 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
331 if (!iovram) {
332 NV_ERROR(drm, "Failed to map VRAM, "
333 "cannot save/restore VGA fonts.\n");
334 return;
335 }
336
337 if (nv_two_heads(dev))
338 NVBlankScreen(dev, 1, true);
339 NVBlankScreen(dev, 0, true);
340
341 /* save control regs */
342 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
343 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
344 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
345 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
346 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
347 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
348
349 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
350 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
351 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
352 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
353
354 /* store font in planes 0..3 */
355 for (plane = 0; plane < 4; plane++)
356 nouveau_vga_font_io(dev, iovram, save, plane);
357
358 /* restore control regs */
359 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
360 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
361 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
362 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
363 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
364 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
365
366 if (nv_two_heads(dev))
367 NVBlankScreen(dev, 1, false);
368 NVBlankScreen(dev, 0, false);
369
370 iounmap(iovram);
371 }
372
373 /*
374 * mode state save/load
375 */
376
377 static void
378 rd_cio_state(struct drm_device *dev, int head,
379 struct nv04_crtc_reg *crtcstate, int index)
380 {
381 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
382 }
383
384 static void
385 wr_cio_state(struct drm_device *dev, int head,
386 struct nv04_crtc_reg *crtcstate, int index)
387 {
388 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
389 }
390
391 static void
392 nv_save_state_ramdac(struct drm_device *dev, int head,
393 struct nv04_mode_state *state)
394 {
395 struct nouveau_drm *drm = nouveau_drm(dev);
396 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
397 int i;
398
399 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
400 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
401
402 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
403 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
404 if (nv_two_heads(dev))
405 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
406 if (drm->client.device.info.chipset == 0x11)
407 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
408
409 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
410
411 if (nv_gf4_disp_arch(dev))
412 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
413 if (drm->client.device.info.chipset >= 0x30)
414 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
415
416 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
417 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
418 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
419 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
420 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
421 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
422 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
423 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
424
425 for (i = 0; i < 7; i++) {
426 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
427 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
428 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
429 }
430
431 if (nv_gf4_disp_arch(dev)) {
432 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
433 for (i = 0; i < 3; i++) {
434 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
435 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
436 }
437 }
438
439 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
440 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
441 if (!nv_gf4_disp_arch(dev) && head == 0) {
442 /* early chips don't allow access to PRAMDAC_TMDS_* without
443 * the head A FPCLK on (nv11 even locks up) */
444 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
445 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
446 }
447 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
448 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
449
450 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
451
452 if (nv_gf4_disp_arch(dev))
453 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
454
455 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
456 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
457 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
458 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
459
460 for (i = 0; i < 38; i++)
461 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
462 NV_PRAMDAC_CTV + 4*i);
463 }
464 }
465
466 static void
467 nv_load_state_ramdac(struct drm_device *dev, int head,
468 struct nv04_mode_state *state)
469 {
470 struct nouveau_drm *drm = nouveau_drm(dev);
471 struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
472 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
473 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
474 int i;
475
476 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
477 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
478
479 clk->pll_prog(clk, pllreg, &regp->pllvals);
480 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
481 if (nv_two_heads(dev))
482 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
483 if (drm->client.device.info.chipset == 0x11)
484 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
485
486 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
487
488 if (nv_gf4_disp_arch(dev))
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
490 if (drm->client.device.info.chipset >= 0x30)
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
492
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
501
502 for (i = 0; i < 7; i++) {
503 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
504
505 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
506 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
507 }
508
509 if (nv_gf4_disp_arch(dev)) {
510 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
511 for (i = 0; i < 3; i++) {
512 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
514 }
515 }
516
517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
521
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
523
524 if (nv_gf4_disp_arch(dev))
525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
526
527 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
531
532 for (i = 0; i < 38; i++)
533 NVWriteRAMDAC(dev, head,
534 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
535 }
536 }
537
538 static void
539 nv_save_state_vga(struct drm_device *dev, int head,
540 struct nv04_mode_state *state)
541 {
542 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
543 int i;
544
545 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
546
547 for (i = 0; i < 25; i++)
548 rd_cio_state(dev, head, regp, i);
549
550 NVSetEnablePalette(dev, head, true);
551 for (i = 0; i < 21; i++)
552 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
553 NVSetEnablePalette(dev, head, false);
554
555 for (i = 0; i < 9; i++)
556 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
557
558 for (i = 0; i < 5; i++)
559 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
560 }
561
562 static void
563 nv_load_state_vga(struct drm_device *dev, int head,
564 struct nv04_mode_state *state)
565 {
566 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
567 int i;
568
569 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
570
571 for (i = 0; i < 5; i++)
572 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
573
574 nv_lock_vga_crtc_base(dev, head, false);
575 for (i = 0; i < 25; i++)
576 wr_cio_state(dev, head, regp, i);
577 nv_lock_vga_crtc_base(dev, head, true);
578
579 for (i = 0; i < 9; i++)
580 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
581
582 NVSetEnablePalette(dev, head, true);
583 for (i = 0; i < 21; i++)
584 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
585 NVSetEnablePalette(dev, head, false);
586 }
587
588 static void
589 nv_save_state_ext(struct drm_device *dev, int head,
590 struct nv04_mode_state *state)
591 {
592 struct nouveau_drm *drm = nouveau_drm(dev);
593 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
594 int i;
595
596 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
597 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
603
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
605 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
607
608 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
609 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
610
611 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
612 rd_cio_state(dev, head, regp, 0x9f);
613
614 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
619
620 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
621 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
622 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
623
624 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
625 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
626
627 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
628 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
629
630 if (nv_two_heads(dev))
631 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
632 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
633 }
634
635 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
636
637 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
639 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
644 }
645 /* NV11 and NV20 don't have this, they stop at 0x52. */
646 if (nv_gf4_disp_arch(dev)) {
647 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
648 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
650
651 for (i = 0; i < 0x10; i++)
652 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
653 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
654 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
655
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
657 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
658 }
659
660 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
661 }
662
663 static void
664 nv_load_state_ext(struct drm_device *dev, int head,
665 struct nv04_mode_state *state)
666 {
667 struct nouveau_drm *drm = nouveau_drm(dev);
668 struct nvif_object *device = &drm->client.device.object;
669 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
670 uint32_t reg900;
671 int i;
672
673 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
674 if (nv_two_heads(dev))
675 /* setting ENGINE_CTRL (EC) *must* come before
676 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
677 * EC that should not be overwritten by writing stale EC
678 */
679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
680
681 nvif_wr32(device, NV_PVIDEO_STOP, 1);
682 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
683 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
684 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
685 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1);
686 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1);
687 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1);
688 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1);
689 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
690
691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
694
695 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
697
698 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
700
701 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
702 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
703 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
704 else
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
706 }
707 }
708
709 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
710
711 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
720
721 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
722 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
723
724 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
725 wr_cio_state(dev, head, regp, 0x9f);
726
727 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
731 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
732 nv_fix_nv40_hw_cursor(dev, head);
733 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
734
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
737 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
742 }
743 /* NV11 and NV20 stop at 0x52. */
744 if (nv_gf4_disp_arch(dev)) {
745 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
746 /* Not waiting for vertical retrace before modifying
747 CRE_53/CRE_54 causes lockups. */
748 nvif_msec(&drm->client.device, 650,
749 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
750 break;
751 );
752 nvif_msec(&drm->client.device, 650,
753 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
754 break;
755 );
756 }
757
758 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
759 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
761
762 for (i = 0; i < 0x10; i++)
763 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
764 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
765 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
766
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
768 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
769 }
770
771 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
772 }
773
774 static void
775 nv_save_state_palette(struct drm_device *dev, int head,
776 struct nv04_mode_state *state)
777 {
778 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
779 int head_offset = head * NV_PRMDIO_SIZE, i;
780
781 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
782 NV_PRMDIO_PIXEL_MASK_MASK);
783 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
784
785 for (i = 0; i < 768; i++) {
786 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
787 NV_PRMDIO_PALETTE_DATA + head_offset);
788 }
789
790 NVSetEnablePalette(dev, head, false);
791 }
792
793 void
794 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
795 struct nv04_mode_state *state)
796 {
797 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
798 int head_offset = head * NV_PRMDIO_SIZE, i;
799
800 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
801 NV_PRMDIO_PIXEL_MASK_MASK);
802 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
803
804 for (i = 0; i < 768; i++) {
805 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
806 state->crtc_reg[head].DAC[i]);
807 }
808
809 NVSetEnablePalette(dev, head, false);
810 }
811
812 void nouveau_hw_save_state(struct drm_device *dev, int head,
813 struct nv04_mode_state *state)
814 {
815 struct nouveau_drm *drm = nouveau_drm(dev);
816
817 if (drm->client.device.info.chipset == 0x11)
818 /* NB: no attempt is made to restore the bad pll later on */
819 nouveau_hw_fix_bad_vpll(dev, head);
820 nv_save_state_ramdac(dev, head, state);
821 nv_save_state_vga(dev, head, state);
822 nv_save_state_palette(dev, head, state);
823 nv_save_state_ext(dev, head, state);
824 }
825
826 void nouveau_hw_load_state(struct drm_device *dev, int head,
827 struct nv04_mode_state *state)
828 {
829 NVVgaProtect(dev, head, true);
830 nv_load_state_ramdac(dev, head, state);
831 nv_load_state_ext(dev, head, state);
832 nouveau_hw_load_state_palette(dev, head, state);
833 nv_load_state_vga(dev, head, state);
834 NVVgaProtect(dev, head, false);
835 }
Linux with added FPC-III support