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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / stm / ltdc.c
blob808d9fb627e97ab07562c17183ade0508abfe0b7
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 * Fabien Dessenne <fabien.dessenne@st.com>
8 * Mickael Reulier <mickael.reulier@st.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/of_address.h>
14 #include <linux/of_graph.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_plane_helper.h>
25
26 #include <video/videomode.h>
27
28 #include "ltdc.h"
29
30 #define NB_CRTC 1
31 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
32
33 #define MAX_IRQ 4
34
35 #define MAX_ENDPOINTS 2
36
37 #define HWVER_10200 0x010200
38 #define HWVER_10300 0x010300
39 #define HWVER_20101 0x020101
40
41 /*
42 * The address of some registers depends on the HW version: such registers have
43 * an extra offset specified with reg_ofs.
44 */
45 #define REG_OFS_NONE 0
46 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
47 #define REG_OFS (ldev->caps.reg_ofs)
48 #define LAY_OFS 0x80 /* Register Offset between 2 layers */
49
50 /* Global register offsets */
51 #define LTDC_IDR 0x0000 /* IDentification */
52 #define LTDC_LCR 0x0004 /* Layer Count */
53 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
54 #define LTDC_BPCR 0x000C /* Back Porch Configuration */
55 #define LTDC_AWCR 0x0010 /* Active Width Configuration */
56 #define LTDC_TWCR 0x0014 /* Total Width Configuration */
57 #define LTDC_GCR 0x0018 /* Global Control */
58 #define LTDC_GC1R 0x001C /* Global Configuration 1 */
59 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
60 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
61 #define LTDC_GACR 0x0028 /* GAmma Correction */
62 #define LTDC_BCCR 0x002C /* Background Color Configuration */
63 #define LTDC_IER 0x0034 /* Interrupt Enable */
64 #define LTDC_ISR 0x0038 /* Interrupt Status */
65 #define LTDC_ICR 0x003C /* Interrupt Clear */
66 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
67 #define LTDC_CPSR 0x0044 /* Current Position Status */
68 #define LTDC_CDSR 0x0048 /* Current Display Status */
69
70 /* Layer register offsets */
71 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
72 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
73 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
74 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
75 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
76 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
77 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
78 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
79 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
80 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
81 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
82 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
83 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
84 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
85 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
86 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
87 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
88 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
89 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
90 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
91 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
92
93 /* Bit definitions */
94 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
95 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
96
97 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
98 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
99
100 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
101 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
102
103 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
104 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
105
106 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
107 #define GCR_DEN BIT(16) /* Dither ENable */
108 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
109 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
110 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
111 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
112
113 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
114 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
115 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
116 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
117 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
118 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
119 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
120 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
121 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
122 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
123 #define GC1R_TP BIT(25) /* Timing Programmable */
124 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
125 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
126 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
127 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
128 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
129
130 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
131 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
132 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
133 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
134 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
135 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
136
137 #define SRCR_IMR BIT(0) /* IMmediate Reload */
138 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
139
140 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
141 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
142 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
143 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
144 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
145
146 #define IER_LIE BIT(0) /* Line Interrupt Enable */
147 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
148 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
149 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
150
151 #define ISR_LIF BIT(0) /* Line Interrupt Flag */
152 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
153 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
154 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
155
156 #define LXCR_LEN BIT(0) /* Layer ENable */
157 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
158 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
159
160 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
161 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
162
163 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
164 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
165
166 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
167
168 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
169
170 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
171 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
172
173 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
174 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
175
176 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
177
178 #define CLUT_SIZE 256
179
180 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
181 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
182 #define BF1_CA 0x400 /* Constant Alpha */
183 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
184 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
185
186 #define NB_PF 8 /* Max nb of HW pixel format */
187
188 enum ltdc_pix_fmt {
189 PF_NONE,
190 /* RGB formats */
191 PF_ARGB8888, /* ARGB [32 bits] */
192 PF_RGBA8888, /* RGBA [32 bits] */
193 PF_RGB888, /* RGB [24 bits] */
194 PF_RGB565, /* RGB [16 bits] */
195 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
196 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
197 /* Indexed formats */
198 PF_L8, /* Indexed 8 bits [8 bits] */
199 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
200 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
201 };
202
203 /* The index gives the encoding of the pixel format for an HW version */
204 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
205 PF_ARGB8888, /* 0x00 */
206 PF_RGB888, /* 0x01 */
207 PF_RGB565, /* 0x02 */
208 PF_ARGB1555, /* 0x03 */
209 PF_ARGB4444, /* 0x04 */
210 PF_L8, /* 0x05 */
211 PF_AL44, /* 0x06 */
212 PF_AL88 /* 0x07 */
213 };
214
215 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
216 PF_ARGB8888, /* 0x00 */
217 PF_RGB888, /* 0x01 */
218 PF_RGB565, /* 0x02 */
219 PF_RGBA8888, /* 0x03 */
220 PF_AL44, /* 0x04 */
221 PF_L8, /* 0x05 */
222 PF_ARGB1555, /* 0x06 */
223 PF_ARGB4444 /* 0x07 */
224 };
225
226 static inline u32 reg_read(void __iomem *base, u32 reg)
227 {
228 return readl_relaxed(base + reg);
229 }
230
231 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
232 {
233 writel_relaxed(val, base + reg);
234 }
235
236 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
237 {
238 reg_write(base, reg, reg_read(base, reg) | mask);
239 }
240
241 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
242 {
243 reg_write(base, reg, reg_read(base, reg) & ~mask);
244 }
245
246 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
247 u32 val)
248 {
249 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
250 }
251
252 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
253 {
254 return (struct ltdc_device *)crtc->dev->dev_private;
255 }
256
257 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
258 {
259 return (struct ltdc_device *)plane->dev->dev_private;
260 }
261
262 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
263 {
264 return (struct ltdc_device *)enc->dev->dev_private;
265 }
266
267 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
268 {
269 enum ltdc_pix_fmt pf;
270
271 switch (drm_fmt) {
272 case DRM_FORMAT_ARGB8888:
273 case DRM_FORMAT_XRGB8888:
274 pf = PF_ARGB8888;
275 break;
276 case DRM_FORMAT_RGBA8888:
277 case DRM_FORMAT_RGBX8888:
278 pf = PF_RGBA8888;
279 break;
280 case DRM_FORMAT_RGB888:
281 pf = PF_RGB888;
282 break;
283 case DRM_FORMAT_RGB565:
284 pf = PF_RGB565;
285 break;
286 case DRM_FORMAT_ARGB1555:
287 case DRM_FORMAT_XRGB1555:
288 pf = PF_ARGB1555;
289 break;
290 case DRM_FORMAT_ARGB4444:
291 case DRM_FORMAT_XRGB4444:
292 pf = PF_ARGB4444;
293 break;
294 case DRM_FORMAT_C8:
295 pf = PF_L8;
296 break;
297 default:
298 pf = PF_NONE;
299 break;
300 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
301 }
302
303 return pf;
304 }
305
306 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
307 {
308 switch (pf) {
309 case PF_ARGB8888:
310 return DRM_FORMAT_ARGB8888;
311 case PF_RGBA8888:
312 return DRM_FORMAT_RGBA8888;
313 case PF_RGB888:
314 return DRM_FORMAT_RGB888;
315 case PF_RGB565:
316 return DRM_FORMAT_RGB565;
317 case PF_ARGB1555:
318 return DRM_FORMAT_ARGB1555;
319 case PF_ARGB4444:
320 return DRM_FORMAT_ARGB4444;
321 case PF_L8:
322 return DRM_FORMAT_C8;
323 case PF_AL44: /* No DRM support */
324 case PF_AL88: /* No DRM support */
325 case PF_NONE:
326 default:
327 return 0;
328 }
329 }
330
331 static inline u32 get_pixelformat_without_alpha(u32 drm)
332 {
333 switch (drm) {
334 case DRM_FORMAT_ARGB4444:
335 return DRM_FORMAT_XRGB4444;
336 case DRM_FORMAT_RGBA4444:
337 return DRM_FORMAT_RGBX4444;
338 case DRM_FORMAT_ARGB1555:
339 return DRM_FORMAT_XRGB1555;
340 case DRM_FORMAT_RGBA5551:
341 return DRM_FORMAT_RGBX5551;
342 case DRM_FORMAT_ARGB8888:
343 return DRM_FORMAT_XRGB8888;
344 case DRM_FORMAT_RGBA8888:
345 return DRM_FORMAT_RGBX8888;
346 default:
347 return 0;
348 }
349 }
350
351 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
352 {
353 struct drm_device *ddev = arg;
354 struct ltdc_device *ldev = ddev->dev_private;
355 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
356
357 /* Line IRQ : trigger the vblank event */
358 if (ldev->irq_status & ISR_LIF)
359 drm_crtc_handle_vblank(crtc);
360
361 /* Save FIFO Underrun & Transfer Error status */
362 mutex_lock(&ldev->err_lock);
363 if (ldev->irq_status & ISR_FUIF)
364 ldev->error_status |= ISR_FUIF;
365 if (ldev->irq_status & ISR_TERRIF)
366 ldev->error_status |= ISR_TERRIF;
367 mutex_unlock(&ldev->err_lock);
368
369 return IRQ_HANDLED;
370 }
371
372 static irqreturn_t ltdc_irq(int irq, void *arg)
373 {
374 struct drm_device *ddev = arg;
375 struct ltdc_device *ldev = ddev->dev_private;
376
377 /* Read & Clear the interrupt status */
378 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
379 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
380
381 return IRQ_WAKE_THREAD;
382 }
383
384 /*
385 * DRM_CRTC
386 */
387
388 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
389 {
390 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
391 struct drm_color_lut *lut;
392 u32 val;
393 int i;
394
395 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
396 return;
397
398 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
399
400 for (i = 0; i < CLUT_SIZE; i++, lut++) {
401 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
402 (lut->blue >> 8) | (i << 24);
403 reg_write(ldev->regs, LTDC_L1CLUTWR, val);
404 }
405 }
406
407 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
408 struct drm_crtc_state *old_state)
409 {
410 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
411
412 DRM_DEBUG_DRIVER("\n");
413
414 /* Sets the background color value */
415 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
416
417 /* Enable IRQ */
418 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
419
420 /* Immediately commit the planes */
421 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
422
423 /* Enable LTDC */
424 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
425
426 drm_crtc_vblank_on(crtc);
427 }
428
429 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
430 struct drm_crtc_state *old_state)
431 {
432 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
433
434 DRM_DEBUG_DRIVER("\n");
435
436 drm_crtc_vblank_off(crtc);
437
438 /* disable LTDC */
439 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
440
441 /* disable IRQ */
442 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
443
444 /* immediately commit disable of layers before switching off LTDC */
445 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
446 }
447
448 #define CLK_TOLERANCE_HZ 50
449
450 static enum drm_mode_status
451 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
452 const struct drm_display_mode *mode)
453 {
454 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
455 int target = mode->clock * 1000;
456 int target_min = target - CLK_TOLERANCE_HZ;
457 int target_max = target + CLK_TOLERANCE_HZ;
458 int result;
459
460 result = clk_round_rate(ldev->pixel_clk, target);
461
462 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
463
464 /* Filter modes according to the max frequency supported by the pads */
465 if (result > ldev->caps.pad_max_freq_hz)
466 return MODE_CLOCK_HIGH;
467
468 /*
469 * Accept all "preferred" modes:
470 * - this is important for panels because panel clock tolerances are
471 * bigger than hdmi ones and there is no reason to not accept them
472 * (the fps may vary a little but it is not a problem).
473 * - the hdmi preferred mode will be accepted too, but userland will
474 * be able to use others hdmi "valid" modes if necessary.
475 */
476 if (mode->type & DRM_MODE_TYPE_PREFERRED)
477 return MODE_OK;
478
479 /*
480 * Filter modes according to the clock value, particularly useful for
481 * hdmi modes that require precise pixel clocks.
482 */
483 if (result < target_min || result > target_max)
484 return MODE_CLOCK_RANGE;
485
486 return MODE_OK;
487 }
488
489 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
490 const struct drm_display_mode *mode,
491 struct drm_display_mode *adjusted_mode)
492 {
493 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
494 int rate = mode->clock * 1000;
495
496 /*
497 * TODO clk_round_rate() does not work yet. When ready, it can
498 * be used instead of clk_set_rate() then clk_get_rate().
499 */
500
501 clk_disable(ldev->pixel_clk);
502 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
503 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
504 return false;
505 }
506 clk_enable(ldev->pixel_clk);
507
508 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
509
510 return true;
511 }
512
513 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
514 {
515 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
516 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
517 struct videomode vm;
518 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
519 u32 total_width, total_height;
520 u32 val;
521
522 drm_display_mode_to_videomode(mode, &vm);
523
524 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
525 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
526 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
527 vm.hfront_porch, vm.hback_porch, vm.hsync_len,
528 vm.vfront_porch, vm.vback_porch, vm.vsync_len);
529
530 /* Convert video timings to ltdc timings */
531 hsync = vm.hsync_len - 1;
532 vsync = vm.vsync_len - 1;
533 accum_hbp = hsync + vm.hback_porch;
534 accum_vbp = vsync + vm.vback_porch;
535 accum_act_w = accum_hbp + vm.hactive;
536 accum_act_h = accum_vbp + vm.vactive;
537 total_width = accum_act_w + vm.hfront_porch;
538 total_height = accum_act_h + vm.vfront_porch;
539
540 /* Configures the HS, VS, DE and PC polarities. Default Active Low */
541 val = 0;
542
543 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
544 val |= GCR_HSPOL;
545
546 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
547 val |= GCR_VSPOL;
548
549 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
550 val |= GCR_DEPOL;
551
552 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
553 val |= GCR_PCPOL;
554
555 reg_update_bits(ldev->regs, LTDC_GCR,
556 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
557
558 /* Set Synchronization size */
559 val = (hsync << 16) | vsync;
560 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
561
562 /* Set Accumulated Back porch */
563 val = (accum_hbp << 16) | accum_vbp;
564 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
565
566 /* Set Accumulated Active Width */
567 val = (accum_act_w << 16) | accum_act_h;
568 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
569
570 /* Set total width & height */
571 val = (total_width << 16) | total_height;
572 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
573
574 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
575 }
576
577 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
578 struct drm_crtc_state *old_crtc_state)
579 {
580 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
581 struct drm_pending_vblank_event *event = crtc->state->event;
582
583 DRM_DEBUG_ATOMIC("\n");
584
585 ltdc_crtc_update_clut(crtc);
586
587 /* Commit shadow registers = update planes at next vblank */
588 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
589
590 if (event) {
591 crtc->state->event = NULL;
592
593 spin_lock_irq(&crtc->dev->event_lock);
594 if (drm_crtc_vblank_get(crtc) == 0)
595 drm_crtc_arm_vblank_event(crtc, event);
596 else
597 drm_crtc_send_vblank_event(crtc, event);
598 spin_unlock_irq(&crtc->dev->event_lock);
599 }
600 }
601
602 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
603 .mode_valid = ltdc_crtc_mode_valid,
604 .mode_fixup = ltdc_crtc_mode_fixup,
605 .mode_set_nofb = ltdc_crtc_mode_set_nofb,
606 .atomic_flush = ltdc_crtc_atomic_flush,
607 .atomic_enable = ltdc_crtc_atomic_enable,
608 .atomic_disable = ltdc_crtc_atomic_disable,
609 };
610
611 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
612 {
613 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
614
615 DRM_DEBUG_DRIVER("\n");
616 reg_set(ldev->regs, LTDC_IER, IER_LIE);
617
618 return 0;
619 }
620
621 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
622 {
623 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
624
625 DRM_DEBUG_DRIVER("\n");
626 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
627 }
628
629 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
630 .destroy = drm_crtc_cleanup,
631 .set_config = drm_atomic_helper_set_config,
632 .page_flip = drm_atomic_helper_page_flip,
633 .reset = drm_atomic_helper_crtc_reset,
634 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
635 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
636 .enable_vblank = ltdc_crtc_enable_vblank,
637 .disable_vblank = ltdc_crtc_disable_vblank,
638 .gamma_set = drm_atomic_helper_legacy_gamma_set,
639 };
640
641 /*
642 * DRM_PLANE
643 */
644
645 static int ltdc_plane_atomic_check(struct drm_plane *plane,
646 struct drm_plane_state *state)
647 {
648 struct drm_framebuffer *fb = state->fb;
649 u32 src_x, src_y, src_w, src_h;
650
651 DRM_DEBUG_DRIVER("\n");
652
653 if (!fb)
654 return 0;
655
656 /* convert src_ from 16:16 format */
657 src_x = state->src_x >> 16;
658 src_y = state->src_y >> 16;
659 src_w = state->src_w >> 16;
660 src_h = state->src_h >> 16;
661
662 /* Reject scaling */
663 if (src_w != state->crtc_w || src_h != state->crtc_h) {
664 DRM_ERROR("Scaling is not supported");
665 return -EINVAL;
666 }
667
668 return 0;
669 }
670
671 static void ltdc_plane_atomic_update(struct drm_plane *plane,
672 struct drm_plane_state *oldstate)
673 {
674 struct ltdc_device *ldev = plane_to_ltdc(plane);
675 struct drm_plane_state *state = plane->state;
676 struct drm_framebuffer *fb = state->fb;
677 u32 lofs = plane->index * LAY_OFS;
678 u32 x0 = state->crtc_x;
679 u32 x1 = state->crtc_x + state->crtc_w - 1;
680 u32 y0 = state->crtc_y;
681 u32 y1 = state->crtc_y + state->crtc_h - 1;
682 u32 src_x, src_y, src_w, src_h;
683 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
684 enum ltdc_pix_fmt pf;
685
686 if (!state->crtc || !fb) {
687 DRM_DEBUG_DRIVER("fb or crtc NULL");
688 return;
689 }
690
691 /* convert src_ from 16:16 format */
692 src_x = state->src_x >> 16;
693 src_y = state->src_y >> 16;
694 src_w = state->src_w >> 16;
695 src_h = state->src_h >> 16;
696
697 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
698 plane->base.id, fb->base.id,
699 src_w, src_h, src_x, src_y,
700 state->crtc_w, state->crtc_h,
701 state->crtc_x, state->crtc_y);
702
703 bpcr = reg_read(ldev->regs, LTDC_BPCR);
704 ahbp = (bpcr & BPCR_AHBP) >> 16;
705 avbp = bpcr & BPCR_AVBP;
706
707 /* Configures the horizontal start and stop position */
708 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
709 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
710 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
711
712 /* Configures the vertical start and stop position */
713 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
714 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
715 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
716
717 /* Specifies the pixel format */
718 pf = to_ltdc_pixelformat(fb->format->format);
719 for (val = 0; val < NB_PF; val++)
720 if (ldev->caps.pix_fmt_hw[val] == pf)
721 break;
722
723 if (val == NB_PF) {
724 DRM_ERROR("Pixel format %.4s not supported\n",
725 (char *)&fb->format->format);
726 val = 0; /* set by default ARGB 32 bits */
727 }
728 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
729
730 /* Configures the color frame buffer pitch in bytes & line length */
731 pitch_in_bytes = fb->pitches[0];
732 line_length = drm_format_plane_cpp(fb->format->format, 0) *
733 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
734 val = ((pitch_in_bytes << 16) | line_length);
735 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
736 LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
737
738 /* Specifies the constant alpha value */
739 val = CONSTA_MAX;
740 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
741
742 /* Specifies the blending factors */
743 val = BF1_PAXCA | BF2_1PAXCA;
744 if (!fb->format->has_alpha)
745 val = BF1_CA | BF2_1CA;
746
747 /* Manage hw-specific capabilities */
748 if (ldev->caps.non_alpha_only_l1 &&
749 plane->type != DRM_PLANE_TYPE_PRIMARY)
750 val = BF1_PAXCA | BF2_1PAXCA;
751
752 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
753 LXBFCR_BF2 | LXBFCR_BF1, val);
754
755 /* Configures the frame buffer line number */
756 val = y1 - y0 + 1;
757 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
758
759 /* Sets the FB address */
760 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
761
762 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
763 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
764
765 /* Enable layer and CLUT if needed */
766 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
767 val |= LXCR_LEN;
768 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
769 LXCR_LEN | LXCR_CLUTEN, val);
770
771 ldev->plane_fpsi[plane->index].counter++;
772
773 mutex_lock(&ldev->err_lock);
774 if (ldev->error_status & ISR_FUIF) {
775 DRM_DEBUG_DRIVER("Fifo underrun\n");
776 ldev->error_status &= ~ISR_FUIF;
777 }
778 if (ldev->error_status & ISR_TERRIF) {
779 DRM_DEBUG_DRIVER("Transfer error\n");
780 ldev->error_status &= ~ISR_TERRIF;
781 }
782 mutex_unlock(&ldev->err_lock);
783 }
784
785 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
786 struct drm_plane_state *oldstate)
787 {
788 struct ltdc_device *ldev = plane_to_ltdc(plane);
789 u32 lofs = plane->index * LAY_OFS;
790
791 /* disable layer */
792 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
793
794 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
795 oldstate->crtc->base.id, plane->base.id);
796 }
797
798 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
799 const struct drm_plane_state *state)
800 {
801 struct drm_plane *plane = state->plane;
802 struct ltdc_device *ldev = plane_to_ltdc(plane);
803 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
804 int ms_since_last;
805 ktime_t now;
806
807 now = ktime_get();
808 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
809
810 drm_printf(p, "\tuser_updates=%dfps\n",
811 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
812
813 fpsi->last_timestamp = now;
814 fpsi->counter = 0;
815 }
816
817 static const struct drm_plane_funcs ltdc_plane_funcs = {
818 .update_plane = drm_atomic_helper_update_plane,
819 .disable_plane = drm_atomic_helper_disable_plane,
820 .destroy = drm_plane_cleanup,
821 .reset = drm_atomic_helper_plane_reset,
822 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
823 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
824 .atomic_print_state = ltdc_plane_atomic_print_state,
825 };
826
827 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
828 .atomic_check = ltdc_plane_atomic_check,
829 .atomic_update = ltdc_plane_atomic_update,
830 .atomic_disable = ltdc_plane_atomic_disable,
831 };
832
833 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
834 enum drm_plane_type type)
835 {
836 unsigned long possible_crtcs = CRTC_MASK;
837 struct ltdc_device *ldev = ddev->dev_private;
838 struct device *dev = ddev->dev;
839 struct drm_plane *plane;
840 unsigned int i, nb_fmt = 0;
841 u32 formats[NB_PF * 2];
842 u32 drm_fmt, drm_fmt_no_alpha;
843 int ret;
844
845 /* Get supported pixel formats */
846 for (i = 0; i < NB_PF; i++) {
847 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
848 if (!drm_fmt)
849 continue;
850 formats[nb_fmt++] = drm_fmt;
851
852 /* Add the no-alpha related format if any & supported */
853 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
854 if (!drm_fmt_no_alpha)
855 continue;
856
857 /* Manage hw-specific capabilities */
858 if (ldev->caps.non_alpha_only_l1 &&
859 type != DRM_PLANE_TYPE_PRIMARY)
860 continue;
861
862 formats[nb_fmt++] = drm_fmt_no_alpha;
863 }
864
865 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
866 if (!plane)
867 return NULL;
868
869 ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
870 &ltdc_plane_funcs, formats, nb_fmt,
871 NULL, type, NULL);
872 if (ret < 0)
873 return NULL;
874
875 drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
876
877 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
878
879 return plane;
880 }
881
882 static void ltdc_plane_destroy_all(struct drm_device *ddev)
883 {
884 struct drm_plane *plane, *plane_temp;
885
886 list_for_each_entry_safe(plane, plane_temp,
887 &ddev->mode_config.plane_list, head)
888 drm_plane_cleanup(plane);
889 }
890
891 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
892 {
893 struct ltdc_device *ldev = ddev->dev_private;
894 struct drm_plane *primary, *overlay;
895 unsigned int i;
896 int ret;
897
898 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
899 if (!primary) {
900 DRM_ERROR("Can not create primary plane\n");
901 return -EINVAL;
902 }
903
904 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
905 &ltdc_crtc_funcs, NULL);
906 if (ret) {
907 DRM_ERROR("Can not initialize CRTC\n");
908 goto cleanup;
909 }
910
911 drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
912
913 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
914 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
915
916 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
917
918 /* Add planes. Note : the first layer is used by primary plane */
919 for (i = 1; i < ldev->caps.nb_layers; i++) {
920 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
921 if (!overlay) {
922 ret = -ENOMEM;
923 DRM_ERROR("Can not create overlay plane %d\n", i);
924 goto cleanup;
925 }
926 }
927
928 return 0;
929
930 cleanup:
931 ltdc_plane_destroy_all(ddev);
932 return ret;
933 }
934
935 /*
936 * DRM_ENCODER
937 */
938
939 static const struct drm_encoder_funcs ltdc_encoder_funcs = {
940 .destroy = drm_encoder_cleanup,
941 };
942
943 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
944 {
945 struct drm_encoder *encoder;
946 int ret;
947
948 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
949 if (!encoder)
950 return -ENOMEM;
951
952 encoder->possible_crtcs = CRTC_MASK;
953 encoder->possible_clones = 0; /* No cloning support */
954
955 drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
956 DRM_MODE_ENCODER_DPI, NULL);
957
958 ret = drm_bridge_attach(encoder, bridge, NULL);
959 if (ret) {
960 drm_encoder_cleanup(encoder);
961 return -EINVAL;
962 }
963
964 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
965
966 return 0;
967 }
968
969 static int ltdc_get_caps(struct drm_device *ddev)
970 {
971 struct ltdc_device *ldev = ddev->dev_private;
972 u32 bus_width_log2, lcr, gc2r;
973
974 /* at least 1 layer must be managed */
975 lcr = reg_read(ldev->regs, LTDC_LCR);
976
977 ldev->caps.nb_layers = max_t(int, lcr, 1);
978
979 /* set data bus width */
980 gc2r = reg_read(ldev->regs, LTDC_GC2R);
981 bus_width_log2 = (gc2r & GC2R_BW) >> 4;
982 ldev->caps.bus_width = 8 << bus_width_log2;
983 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
984
985 switch (ldev->caps.hw_version) {
986 case HWVER_10200:
987 case HWVER_10300:
988 ldev->caps.reg_ofs = REG_OFS_NONE;
989 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
990 /*
991 * Hw older versions support non-alpha color formats derived
992 * from native alpha color formats only on the primary layer.
993 * For instance, RG16 native format without alpha works fine
994 * on 2nd layer but XR24 (derived color format from AR24)
995 * does not work on 2nd layer.
996 */
997 ldev->caps.non_alpha_only_l1 = true;
998 ldev->caps.pad_max_freq_hz = 90000000;
999 if (ldev->caps.hw_version == HWVER_10200)
1000 ldev->caps.pad_max_freq_hz = 65000000;
1001 break;
1002 case HWVER_20101:
1003 ldev->caps.reg_ofs = REG_OFS_4;
1004 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1005 ldev->caps.non_alpha_only_l1 = false;
1006 ldev->caps.pad_max_freq_hz = 150000000;
1007 break;
1008 default:
1009 return -ENODEV;
1010 }
1011
1012 return 0;
1013 }
1014
1015 int ltdc_load(struct drm_device *ddev)
1016 {
1017 struct platform_device *pdev = to_platform_device(ddev->dev);
1018 struct ltdc_device *ldev = ddev->dev_private;
1019 struct device *dev = ddev->dev;
1020 struct device_node *np = dev->of_node;
1021 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL};
1022 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL};
1023 struct drm_crtc *crtc;
1024 struct reset_control *rstc;
1025 struct resource *res;
1026 int irq, ret, i, endpoint_not_ready = -ENODEV;
1027
1028 DRM_DEBUG_DRIVER("\n");
1029
1030 /* Get endpoints if any */
1031 for (i = 0; i < MAX_ENDPOINTS; i++) {
1032 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i],
1033 &bridge[i]);
1034
1035 /*
1036 * If at least one endpoint is -EPROBE_DEFER, defer probing,
1037 * else if at least one endpoint is ready, continue probing.
1038 */
1039 if (ret == -EPROBE_DEFER)
1040 return ret;
1041 else if (!ret)
1042 endpoint_not_ready = 0;
1043 }
1044
1045 if (endpoint_not_ready)
1046 return endpoint_not_ready;
1047
1048 rstc = devm_reset_control_get_exclusive(dev, NULL);
1049
1050 mutex_init(&ldev->err_lock);
1051
1052 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1053 if (IS_ERR(ldev->pixel_clk)) {
1054 DRM_ERROR("Unable to get lcd clock\n");
1055 return -ENODEV;
1056 }
1057
1058 if (clk_prepare_enable(ldev->pixel_clk)) {
1059 DRM_ERROR("Unable to prepare pixel clock\n");
1060 return -ENODEV;
1061 }
1062
1063 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1064 ldev->regs = devm_ioremap_resource(dev, res);
1065 if (IS_ERR(ldev->regs)) {
1066 DRM_ERROR("Unable to get ltdc registers\n");
1067 ret = PTR_ERR(ldev->regs);
1068 goto err;
1069 }
1070
1071 for (i = 0; i < MAX_IRQ; i++) {
1072 irq = platform_get_irq(pdev, i);
1073 if (irq < 0)
1074 continue;
1075
1076 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1077 ltdc_irq_thread, IRQF_ONESHOT,
1078 dev_name(dev), ddev);
1079 if (ret) {
1080 DRM_ERROR("Failed to register LTDC interrupt\n");
1081 goto err;
1082 }
1083 }
1084
1085 if (!IS_ERR(rstc)) {
1086 reset_control_assert(rstc);
1087 usleep_range(10, 20);
1088 reset_control_deassert(rstc);
1089 }
1090
1091 /* Disable interrupts */
1092 reg_clear(ldev->regs, LTDC_IER,
1093 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1094
1095 ret = ltdc_get_caps(ddev);
1096 if (ret) {
1097 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1098 ldev->caps.hw_version);
1099 goto err;
1100 }
1101
1102 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
1103
1104 /* Add endpoints panels or bridges if any */
1105 for (i = 0; i < MAX_ENDPOINTS; i++) {
1106 if (panel[i]) {
1107 bridge[i] = drm_panel_bridge_add(panel[i],
1108 DRM_MODE_CONNECTOR_DPI);
1109 if (IS_ERR(bridge[i])) {
1110 DRM_ERROR("panel-bridge endpoint %d\n", i);
1111 ret = PTR_ERR(bridge[i]);
1112 goto err;
1113 }
1114 }
1115
1116 if (bridge[i]) {
1117 ret = ltdc_encoder_init(ddev, bridge[i]);
1118 if (ret) {
1119 DRM_ERROR("init encoder endpoint %d\n", i);
1120 goto err;
1121 }
1122 }
1123 }
1124
1125 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1126 if (!crtc) {
1127 DRM_ERROR("Failed to allocate crtc\n");
1128 ret = -ENOMEM;
1129 goto err;
1130 }
1131
1132 ret = ltdc_crtc_init(ddev, crtc);
1133 if (ret) {
1134 DRM_ERROR("Failed to init crtc\n");
1135 goto err;
1136 }
1137
1138 ret = drm_vblank_init(ddev, NB_CRTC);
1139 if (ret) {
1140 DRM_ERROR("Failed calling drm_vblank_init()\n");
1141 goto err;
1142 }
1143
1144 /* Allow usage of vblank without having to call drm_irq_install */
1145 ddev->irq_enabled = 1;
1146
1147 return 0;
1148
1149 err:
1150 for (i = 0; i < MAX_ENDPOINTS; i++)
1151 drm_panel_bridge_remove(bridge[i]);
1152
1153 clk_disable_unprepare(ldev->pixel_clk);
1154
1155 return ret;
1156 }
1157
1158 void ltdc_unload(struct drm_device *ddev)
1159 {
1160 struct ltdc_device *ldev = ddev->dev_private;
1161 int i;
1162
1163 DRM_DEBUG_DRIVER("\n");
1164
1165 for (i = 0; i < MAX_ENDPOINTS; i++)
1166 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1167
1168 clk_disable_unprepare(ldev->pixel_clk);
1169 }
1170
1171 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1172 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1173 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1174 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1175 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1176 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support