?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / hdmi.c
blob0082468f703c8c12ec89b142142b61b84b22fe89
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/hdmi.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
18
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_crtc_helper.h>
22
23 #include <sound/hda_verbs.h>
24
25 #include <media/cec-notifier.h>
26
27 #include "hdmi.h"
28 #include "drm.h"
29 #include "dc.h"
30 #include "trace.h"
31
32 #define HDMI_ELD_BUFFER_SIZE 96
33
34 struct tmds_config {
35 unsigned int pclk;
36 u32 pll0;
37 u32 pll1;
38 u32 pe_current;
39 u32 drive_current;
40 u32 peak_current;
41 };
42
43 struct tegra_hdmi_config {
44 const struct tmds_config *tmds;
45 unsigned int num_tmds;
46
47 unsigned long fuse_override_offset;
48 u32 fuse_override_value;
49
50 bool has_sor_io_peak_current;
51 bool has_hda;
52 bool has_hbr;
53 };
54
55 struct tegra_hdmi {
56 struct host1x_client client;
57 struct tegra_output output;
58 struct device *dev;
59
60 struct regulator *hdmi;
61 struct regulator *pll;
62 struct regulator *vdd;
63
64 void __iomem *regs;
65 unsigned int irq;
66
67 struct clk *clk_parent;
68 struct clk *clk;
69 struct reset_control *rst;
70
71 const struct tegra_hdmi_config *config;
72
73 unsigned int audio_source;
74 unsigned int audio_sample_rate;
75 unsigned int audio_channels;
76
77 unsigned int pixel_clock;
78 bool stereo;
79 bool dvi;
80
81 struct drm_info_list *debugfs_files;
82 };
83
84 static inline struct tegra_hdmi *
85 host1x_client_to_hdmi(struct host1x_client *client)
86 {
87 return container_of(client, struct tegra_hdmi, client);
88 }
89
90 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
91 {
92 return container_of(output, struct tegra_hdmi, output);
93 }
94
95 #define HDMI_AUDIOCLK_FREQ 216000000
96 #define HDMI_REKEY_DEFAULT 56
97
98 enum {
99 AUTO = 0,
100 SPDIF,
101 HDA,
102 };
103
104 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
105 unsigned int offset)
106 {
107 u32 value = readl(hdmi->regs + (offset << 2));
108
109 trace_hdmi_readl(hdmi->dev, offset, value);
110
111 return value;
112 }
113
114 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
115 unsigned int offset)
116 {
117 trace_hdmi_writel(hdmi->dev, offset, value);
118 writel(value, hdmi->regs + (offset << 2));
119 }
120
121 struct tegra_hdmi_audio_config {
122 unsigned int pclk;
123 unsigned int n;
124 unsigned int cts;
125 unsigned int aval;
126 };
127
128 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
129 { 25200000, 4096, 25200, 24000 },
130 { 27000000, 4096, 27000, 24000 },
131 { 74250000, 4096, 74250, 24000 },
132 { 148500000, 4096, 148500, 24000 },
133 { 0, 0, 0, 0 },
134 };
135
136 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
137 { 25200000, 5880, 26250, 25000 },
138 { 27000000, 5880, 28125, 25000 },
139 { 74250000, 4704, 61875, 20000 },
140 { 148500000, 4704, 123750, 20000 },
141 { 0, 0, 0, 0 },
142 };
143
144 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
145 { 25200000, 6144, 25200, 24000 },
146 { 27000000, 6144, 27000, 24000 },
147 { 74250000, 6144, 74250, 24000 },
148 { 148500000, 6144, 148500, 24000 },
149 { 0, 0, 0, 0 },
150 };
151
152 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
153 { 25200000, 11760, 26250, 25000 },
154 { 27000000, 11760, 28125, 25000 },
155 { 74250000, 9408, 61875, 20000 },
156 { 148500000, 9408, 123750, 20000 },
157 { 0, 0, 0, 0 },
158 };
159
160 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
161 { 25200000, 12288, 25200, 24000 },
162 { 27000000, 12288, 27000, 24000 },
163 { 74250000, 12288, 74250, 24000 },
164 { 148500000, 12288, 148500, 24000 },
165 { 0, 0, 0, 0 },
166 };
167
168 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
169 { 25200000, 23520, 26250, 25000 },
170 { 27000000, 23520, 28125, 25000 },
171 { 74250000, 18816, 61875, 20000 },
172 { 148500000, 18816, 123750, 20000 },
173 { 0, 0, 0, 0 },
174 };
175
176 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
177 { 25200000, 24576, 25200, 24000 },
178 { 27000000, 24576, 27000, 24000 },
179 { 74250000, 24576, 74250, 24000 },
180 { 148500000, 24576, 148500, 24000 },
181 { 0, 0, 0, 0 },
182 };
183
184 static const struct tmds_config tegra20_tmds_config[] = {
185 { /* slow pixel clock modes */
186 .pclk = 27000000,
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
188 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
189 SOR_PLL_TX_REG_LOAD(3),
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
191 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
192 PE_CURRENT1(PE_CURRENT_0_0_mA) |
193 PE_CURRENT2(PE_CURRENT_0_0_mA) |
194 PE_CURRENT3(PE_CURRENT_0_0_mA),
195 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
196 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
197 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
198 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
199 },
200 { /* high pixel clock modes */
201 .pclk = UINT_MAX,
202 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
203 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
204 SOR_PLL_TX_REG_LOAD(3),
205 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
206 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
207 PE_CURRENT1(PE_CURRENT_6_0_mA) |
208 PE_CURRENT2(PE_CURRENT_6_0_mA) |
209 PE_CURRENT3(PE_CURRENT_6_0_mA),
210 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
211 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
212 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
213 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
214 },
215 };
216
217 static const struct tmds_config tegra30_tmds_config[] = {
218 { /* 480p modes */
219 .pclk = 27000000,
220 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
221 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
222 SOR_PLL_TX_REG_LOAD(0),
223 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
224 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
225 PE_CURRENT1(PE_CURRENT_0_0_mA) |
226 PE_CURRENT2(PE_CURRENT_0_0_mA) |
227 PE_CURRENT3(PE_CURRENT_0_0_mA),
228 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
229 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
230 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
231 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
232 }, { /* 720p modes */
233 .pclk = 74250000,
234 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
235 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
236 SOR_PLL_TX_REG_LOAD(0),
237 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
238 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
239 PE_CURRENT1(PE_CURRENT_5_0_mA) |
240 PE_CURRENT2(PE_CURRENT_5_0_mA) |
241 PE_CURRENT3(PE_CURRENT_5_0_mA),
242 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
243 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
244 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
245 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
246 }, { /* 1080p modes */
247 .pclk = UINT_MAX,
248 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
249 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
250 SOR_PLL_TX_REG_LOAD(0),
251 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
252 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
253 PE_CURRENT1(PE_CURRENT_5_0_mA) |
254 PE_CURRENT2(PE_CURRENT_5_0_mA) |
255 PE_CURRENT3(PE_CURRENT_5_0_mA),
256 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
257 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
258 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
259 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
260 },
261 };
262
263 static const struct tmds_config tegra114_tmds_config[] = {
264 { /* 480p/576p / 25.2MHz/27MHz modes */
265 .pclk = 27000000,
266 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
267 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
268 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
269 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
270 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
271 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
272 PE_CURRENT3(PE_CURRENT_0_mA_T114),
273 .drive_current =
274 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
275 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
276 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
277 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
278 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
279 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
280 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
281 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
282 }, { /* 720p / 74.25MHz modes */
283 .pclk = 74250000,
284 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
285 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
286 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
287 SOR_PLL_TMDS_TERMADJ(0),
288 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
289 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
290 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
291 PE_CURRENT3(PE_CURRENT_15_mA_T114),
292 .drive_current =
293 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
294 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
295 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
296 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
297 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
298 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
299 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
300 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
301 }, { /* 1080p / 148.5MHz modes */
302 .pclk = 148500000,
303 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
304 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
305 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
306 SOR_PLL_TMDS_TERMADJ(0),
307 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
308 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
309 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
310 PE_CURRENT3(PE_CURRENT_10_mA_T114),
311 .drive_current =
312 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
313 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
314 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
315 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
316 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
317 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
318 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
319 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
320 }, { /* 225/297MHz modes */
321 .pclk = UINT_MAX,
322 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
323 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
324 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
325 | SOR_PLL_TMDS_TERM_ENABLE,
326 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
327 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
328 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
329 PE_CURRENT3(PE_CURRENT_0_mA_T114),
330 .drive_current =
331 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
332 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
333 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
334 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
335 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
336 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
337 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
338 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
339 },
340 };
341
342 static const struct tmds_config tegra124_tmds_config[] = {
343 { /* 480p/576p / 25.2MHz/27MHz modes */
344 .pclk = 27000000,
345 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
346 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
347 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
348 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
349 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
350 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
351 PE_CURRENT3(PE_CURRENT_0_mA_T114),
352 .drive_current =
353 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
354 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
355 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
356 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
357 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
358 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
359 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
360 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
361 }, { /* 720p / 74.25MHz modes */
362 .pclk = 74250000,
363 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
364 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
365 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
366 SOR_PLL_TMDS_TERMADJ(0),
367 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
368 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
369 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
370 PE_CURRENT3(PE_CURRENT_15_mA_T114),
371 .drive_current =
372 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
373 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
374 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
375 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
376 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
377 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
378 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
379 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
380 }, { /* 1080p / 148.5MHz modes */
381 .pclk = 148500000,
382 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
383 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
384 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
385 SOR_PLL_TMDS_TERMADJ(0),
386 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
387 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
388 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
389 PE_CURRENT3(PE_CURRENT_10_mA_T114),
390 .drive_current =
391 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
392 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
393 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
394 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
395 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
396 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
397 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
398 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
399 }, { /* 225/297MHz modes */
400 .pclk = UINT_MAX,
401 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
402 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
403 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
404 | SOR_PLL_TMDS_TERM_ENABLE,
405 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
406 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
407 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
408 PE_CURRENT3(PE_CURRENT_0_mA_T114),
409 .drive_current =
410 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
411 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
412 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
413 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
414 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
415 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
416 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
417 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
418 },
419 };
420
421 static const struct tegra_hdmi_audio_config *
422 tegra_hdmi_get_audio_config(unsigned int sample_rate, unsigned int pclk)
423 {
424 const struct tegra_hdmi_audio_config *table;
425
426 switch (sample_rate) {
427 case 32000:
428 table = tegra_hdmi_audio_32k;
429 break;
430
431 case 44100:
432 table = tegra_hdmi_audio_44_1k;
433 break;
434
435 case 48000:
436 table = tegra_hdmi_audio_48k;
437 break;
438
439 case 88200:
440 table = tegra_hdmi_audio_88_2k;
441 break;
442
443 case 96000:
444 table = tegra_hdmi_audio_96k;
445 break;
446
447 case 176400:
448 table = tegra_hdmi_audio_176_4k;
449 break;
450
451 case 192000:
452 table = tegra_hdmi_audio_192k;
453 break;
454
455 default:
456 return NULL;
457 }
458
459 while (table->pclk) {
460 if (table->pclk == pclk)
461 return table;
462
463 table++;
464 }
465
466 return NULL;
467 }
468
469 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
470 {
471 const unsigned int freqs[] = {
472 32000, 44100, 48000, 88200, 96000, 176400, 192000
473 };
474 unsigned int i;
475
476 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
477 unsigned int f = freqs[i];
478 unsigned int eight_half;
479 unsigned int delta;
480 u32 value;
481
482 if (f > 96000)
483 delta = 2;
484 else if (f > 48000)
485 delta = 6;
486 else
487 delta = 9;
488
489 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
490 value = AUDIO_FS_LOW(eight_half - delta) |
491 AUDIO_FS_HIGH(eight_half + delta);
492 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
493 }
494 }
495
496 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
497 {
498 static const struct {
499 unsigned int sample_rate;
500 unsigned int offset;
501 } regs[] = {
502 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
503 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
504 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
505 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
506 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
507 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
508 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
509 };
510 unsigned int i;
511
512 for (i = 0; i < ARRAY_SIZE(regs); i++) {
513 if (regs[i].sample_rate == hdmi->audio_sample_rate) {
514 tegra_hdmi_writel(hdmi, value, regs[i].offset);
515 break;
516 }
517 }
518 }
519
520 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
521 {
522 const struct tegra_hdmi_audio_config *config;
523 u32 source, value;
524
525 switch (hdmi->audio_source) {
526 case HDA:
527 if (hdmi->config->has_hda)
528 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
529 else
530 return -EINVAL;
531
532 break;
533
534 case SPDIF:
535 if (hdmi->config->has_hda)
536 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
537 else
538 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
539 break;
540
541 default:
542 if (hdmi->config->has_hda)
543 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
544 else
545 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
546 break;
547 }
548
549 /*
550 * Tegra30 and later use a slightly modified version of the register
551 * layout to accomodate for changes related to supporting HDA as the
552 * audio input source for HDMI. The source select field has moved to
553 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
554 * per block fields remain in the AUDIO_CNTRL0 register.
555 */
556 if (hdmi->config->has_hda) {
557 /*
558 * Inject null samples into the audio FIFO for every frame in
559 * which the codec did not receive any samples. This applies
560 * to stereo LPCM only.
561 *
562 * XXX: This seems to be a remnant of MCP days when this was
563 * used to work around issues with monitors not being able to
564 * play back system startup sounds early. It is possibly not
565 * needed on Linux at all.
566 */
567 if (hdmi->audio_channels == 2)
568 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
569 else
570 value = 0;
571
572 value |= source;
573
574 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
575 }
576
577 /*
578 * On Tegra20, HDA is not a supported audio source and the source
579 * select field is part of the AUDIO_CNTRL0 register.
580 */
581 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
582 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
583
584 if (!hdmi->config->has_hda)
585 value |= source;
586
587 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
588
589 /*
590 * Advertise support for High Bit-Rate on Tegra114 and later.
591 */
592 if (hdmi->config->has_hbr) {
593 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
594 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
595 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
596 }
597
598 config = tegra_hdmi_get_audio_config(hdmi->audio_sample_rate,
599 hdmi->pixel_clock);
600 if (!config) {
601 dev_err(hdmi->dev,
602 "cannot set audio to %u Hz at %u Hz pixel clock\n",
603 hdmi->audio_sample_rate, hdmi->pixel_clock);
604 return -EINVAL;
605 }
606
607 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
608
609 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
610 AUDIO_N_VALUE(config->n - 1);
611 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
612
613 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
614 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
615
616 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
617 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
618
619 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
620 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
621
622 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
623 value &= ~AUDIO_N_RESETF;
624 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
625
626 if (hdmi->config->has_hda)
627 tegra_hdmi_write_aval(hdmi, config->aval);
628
629 tegra_hdmi_setup_audio_fs_tables(hdmi);
630
631 return 0;
632 }
633
634 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
635 {
636 u32 value;
637
638 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
639 value &= ~GENERIC_CTRL_AUDIO;
640 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
641 }
642
643 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
644 {
645 u32 value;
646
647 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
648 value |= GENERIC_CTRL_AUDIO;
649 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
650 }
651
652 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
653 {
654 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
655 u32 value;
656
657 for (i = 0; i < length; i++)
658 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
659 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
660
661 /*
662 * The HDA codec will always report an ELD buffer size of 96 bytes and
663 * the HDA codec driver will check that each byte read from the buffer
664 * is valid. Therefore every byte must be written, even if no 96 bytes
665 * were parsed from EDID.
666 */
667 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
668 tegra_hdmi_writel(hdmi, i << 8 | 0,
669 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
670
671 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
672 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
673 }
674
675 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
676 {
677 u32 value = 0;
678 size_t i;
679
680 for (i = size; i > 0; i--)
681 value = (value << 8) | ptr[i - 1];
682
683 return value;
684 }
685
686 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
687 size_t size)
688 {
689 const u8 *ptr = data;
690 unsigned long offset;
691 size_t i, j;
692 u32 value;
693
694 switch (ptr[0]) {
695 case HDMI_INFOFRAME_TYPE_AVI:
696 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
697 break;
698
699 case HDMI_INFOFRAME_TYPE_AUDIO:
700 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
701 break;
702
703 case HDMI_INFOFRAME_TYPE_VENDOR:
704 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
705 break;
706
707 default:
708 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
709 ptr[0]);
710 return;
711 }
712
713 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
714 INFOFRAME_HEADER_VERSION(ptr[1]) |
715 INFOFRAME_HEADER_LEN(ptr[2]);
716 tegra_hdmi_writel(hdmi, value, offset);
717 offset++;
718
719 /*
720 * Each subpack contains 7 bytes, divided into:
721 * - subpack_low: bytes 0 - 3
722 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
723 */
724 for (i = 3, j = 0; i < size; i += 7, j += 8) {
725 size_t rem = size - i, num = min_t(size_t, rem, 4);
726
727 value = tegra_hdmi_subpack(&ptr[i], num);
728 tegra_hdmi_writel(hdmi, value, offset++);
729
730 num = min_t(size_t, rem - num, 3);
731
732 value = tegra_hdmi_subpack(&ptr[i + 4], num);
733 tegra_hdmi_writel(hdmi, value, offset++);
734 }
735 }
736
737 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
738 struct drm_display_mode *mode)
739 {
740 struct hdmi_avi_infoframe frame;
741 u8 buffer[17];
742 ssize_t err;
743
744 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
745 if (err < 0) {
746 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
747 return;
748 }
749
750 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
751 if (err < 0) {
752 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
753 return;
754 }
755
756 tegra_hdmi_write_infopack(hdmi, buffer, err);
757 }
758
759 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
760 {
761 u32 value;
762
763 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
764 value &= ~INFOFRAME_CTRL_ENABLE;
765 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
766 }
767
768 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
769 {
770 u32 value;
771
772 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
773 value |= INFOFRAME_CTRL_ENABLE;
774 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
775 }
776
777 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
778 {
779 struct hdmi_audio_infoframe frame;
780 u8 buffer[14];
781 ssize_t err;
782
783 err = hdmi_audio_infoframe_init(&frame);
784 if (err < 0) {
785 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
786 err);
787 return;
788 }
789
790 frame.channels = hdmi->audio_channels;
791
792 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
793 if (err < 0) {
794 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
795 err);
796 return;
797 }
798
799 /*
800 * The audio infoframe has only one set of subpack registers, so the
801 * infoframe needs to be truncated. One set of subpack registers can
802 * contain 7 bytes. Including the 3 byte header only the first 10
803 * bytes can be programmed.
804 */
805 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
806 }
807
808 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
809 {
810 u32 value;
811
812 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
813 value &= ~INFOFRAME_CTRL_ENABLE;
814 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
815 }
816
817 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
818 {
819 u32 value;
820
821 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
822 value |= INFOFRAME_CTRL_ENABLE;
823 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
824 }
825
826 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
827 {
828 struct hdmi_vendor_infoframe frame;
829 u8 buffer[10];
830 ssize_t err;
831
832 hdmi_vendor_infoframe_init(&frame);
833 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
834
835 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
836 if (err < 0) {
837 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
838 err);
839 return;
840 }
841
842 tegra_hdmi_write_infopack(hdmi, buffer, err);
843 }
844
845 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
846 {
847 u32 value;
848
849 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
850 value &= ~GENERIC_CTRL_ENABLE;
851 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
852 }
853
854 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
855 {
856 u32 value;
857
858 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
859 value |= GENERIC_CTRL_ENABLE;
860 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
861 }
862
863 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
864 const struct tmds_config *tmds)
865 {
866 u32 value;
867
868 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
869 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
870 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
871
872 tegra_hdmi_writel(hdmi, tmds->drive_current,
873 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
874
875 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
876 value |= hdmi->config->fuse_override_value;
877 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
878
879 if (hdmi->config->has_sor_io_peak_current)
880 tegra_hdmi_writel(hdmi, tmds->peak_current,
881 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
882 }
883
884 static bool tegra_output_is_hdmi(struct tegra_output *output)
885 {
886 struct edid *edid;
887
888 if (!output->connector.edid_blob_ptr)
889 return false;
890
891 edid = (struct edid *)output->connector.edid_blob_ptr->data;
892
893 return drm_detect_hdmi_monitor(edid);
894 }
895
896 static enum drm_connector_status
897 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
898 {
899 struct tegra_output *output = connector_to_output(connector);
900 struct tegra_hdmi *hdmi = to_hdmi(output);
901 enum drm_connector_status status;
902
903 status = tegra_output_connector_detect(connector, force);
904 if (status == connector_status_connected)
905 return status;
906
907 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
908 return status;
909 }
910
911 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
912
913 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
914 DEBUGFS_REG32(HDMI_CTXSW),
915 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
916 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
917 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
918 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
919 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
920 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
921 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
922 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
923 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
924 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
925 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
926 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
927 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
928 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
929 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
930 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
931 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
932 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
933 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
934 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
935 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
936 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
937 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
938 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
939 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
974 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
975 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
976 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
977 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
978 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
979 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
980 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
981 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
982 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
983 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
984 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
985 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
986 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
987 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
988 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
989 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
990 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
991 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
992 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
993 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
994 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
995 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
996 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1021 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1022 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1023 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1024 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1025 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1026 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1027 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1028 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1029 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1030 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1031 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1032 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1033 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1034 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1035 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1036 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1037 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1038 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1039 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1040 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1041 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1042 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1043 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1044 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1045 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1046 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1047 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1048 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1049 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1050 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1051 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1052 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1053 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1054 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1055 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1056 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1057 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1058 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1059 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1060 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1061 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1062 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1063 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1064 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1065 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1066 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1067 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1068 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1069 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1070 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1071 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1072 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1073 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1074 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1075 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1076 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1077 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1078 };
1079
1080 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1081 {
1082 struct drm_info_node *node = s->private;
1083 struct tegra_hdmi *hdmi = node->info_ent->data;
1084 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1085 struct drm_device *drm = node->minor->dev;
1086 unsigned int i;
1087 int err = 0;
1088
1089 drm_modeset_lock_all(drm);
1090
1091 if (!crtc || !crtc->state->active) {
1092 err = -EBUSY;
1093 goto unlock;
1094 }
1095
1096 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1097 unsigned int offset = tegra_hdmi_regs[i].offset;
1098
1099 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1100 offset, tegra_hdmi_readl(hdmi, offset));
1101 }
1102
1103 unlock:
1104 drm_modeset_unlock_all(drm);
1105 return err;
1106 }
1107
1108 static struct drm_info_list debugfs_files[] = {
1109 { "regs", tegra_hdmi_show_regs, 0, NULL },
1110 };
1111
1112 static int tegra_hdmi_late_register(struct drm_connector *connector)
1113 {
1114 struct tegra_output *output = connector_to_output(connector);
1115 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1116 struct drm_minor *minor = connector->dev->primary;
1117 struct dentry *root = connector->debugfs_entry;
1118 struct tegra_hdmi *hdmi = to_hdmi(output);
1119 int err;
1120
1121 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1122 GFP_KERNEL);
1123 if (!hdmi->debugfs_files)
1124 return -ENOMEM;
1125
1126 for (i = 0; i < count; i++)
1127 hdmi->debugfs_files[i].data = hdmi;
1128
1129 err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1130 if (err < 0)
1131 goto free;
1132
1133 return 0;
1134
1135 free:
1136 kfree(hdmi->debugfs_files);
1137 hdmi->debugfs_files = NULL;
1138
1139 return err;
1140 }
1141
1142 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1143 {
1144 struct tegra_output *output = connector_to_output(connector);
1145 struct drm_minor *minor = connector->dev->primary;
1146 unsigned int count = ARRAY_SIZE(debugfs_files);
1147 struct tegra_hdmi *hdmi = to_hdmi(output);
1148
1149 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1150 kfree(hdmi->debugfs_files);
1151 hdmi->debugfs_files = NULL;
1152 }
1153
1154 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1155 .reset = drm_atomic_helper_connector_reset,
1156 .detect = tegra_hdmi_connector_detect,
1157 .fill_modes = drm_helper_probe_single_connector_modes,
1158 .destroy = tegra_output_connector_destroy,
1159 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1160 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1161 .late_register = tegra_hdmi_late_register,
1162 .early_unregister = tegra_hdmi_early_unregister,
1163 };
1164
1165 static enum drm_mode_status
1166 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1167 struct drm_display_mode *mode)
1168 {
1169 struct tegra_output *output = connector_to_output(connector);
1170 struct tegra_hdmi *hdmi = to_hdmi(output);
1171 unsigned long pclk = mode->clock * 1000;
1172 enum drm_mode_status status = MODE_OK;
1173 struct clk *parent;
1174 long err;
1175
1176 parent = clk_get_parent(hdmi->clk_parent);
1177
1178 err = clk_round_rate(parent, pclk * 4);
1179 if (err <= 0)
1180 status = MODE_NOCLOCK;
1181
1182 return status;
1183 }
1184
1185 static const struct drm_connector_helper_funcs
1186 tegra_hdmi_connector_helper_funcs = {
1187 .get_modes = tegra_output_connector_get_modes,
1188 .mode_valid = tegra_hdmi_connector_mode_valid,
1189 };
1190
1191 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
1192 .destroy = tegra_output_encoder_destroy,
1193 };
1194
1195 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1196 {
1197 struct tegra_output *output = encoder_to_output(encoder);
1198 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1199 struct tegra_hdmi *hdmi = to_hdmi(output);
1200 u32 value;
1201
1202 /*
1203 * The following accesses registers of the display controller, so make
1204 * sure it's only executed when the output is attached to one.
1205 */
1206 if (dc) {
1207 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1208 value &= ~HDMI_ENABLE;
1209 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1210
1211 tegra_dc_commit(dc);
1212 }
1213
1214 if (!hdmi->dvi) {
1215 if (hdmi->stereo)
1216 tegra_hdmi_disable_stereo_infoframe(hdmi);
1217
1218 tegra_hdmi_disable_audio_infoframe(hdmi);
1219 tegra_hdmi_disable_avi_infoframe(hdmi);
1220 tegra_hdmi_disable_audio(hdmi);
1221 }
1222
1223 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1224 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1225
1226 pm_runtime_put(hdmi->dev);
1227 }
1228
1229 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1230 {
1231 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1232 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1233 struct tegra_output *output = encoder_to_output(encoder);
1234 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1235 struct tegra_hdmi *hdmi = to_hdmi(output);
1236 unsigned int pulse_start, div82;
1237 int retries = 1000;
1238 u32 value;
1239 int err;
1240
1241 pm_runtime_get_sync(hdmi->dev);
1242
1243 /*
1244 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1245 * is used for interoperability between the HDA codec driver and the
1246 * HDMI driver.
1247 */
1248 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1249 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1250
1251 hdmi->pixel_clock = mode->clock * 1000;
1252 h_sync_width = mode->hsync_end - mode->hsync_start;
1253 h_back_porch = mode->htotal - mode->hsync_end;
1254 h_front_porch = mode->hsync_start - mode->hdisplay;
1255
1256 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1257 if (err < 0) {
1258 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1259 err);
1260 }
1261
1262 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1263
1264 /* power up sequence */
1265 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1266 value &= ~SOR_PLL_PDBG;
1267 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1268
1269 usleep_range(10, 20);
1270
1271 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1272 value &= ~SOR_PLL_PWR;
1273 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1274
1275 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1276 DC_DISP_DISP_TIMING_OPTIONS);
1277 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1278 DC_DISP_DISP_COLOR_CONTROL);
1279
1280 /* video_preamble uses h_pulse2 */
1281 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1282
1283 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1284
1285 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1286 PULSE_LAST_END_A;
1287 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1288
1289 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1290 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1291
1292 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1293 VSYNC_WINDOW_ENABLE;
1294 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1295
1296 if (dc->pipe)
1297 value = HDMI_SRC_DISPLAYB;
1298 else
1299 value = HDMI_SRC_DISPLAYA;
1300
1301 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1302 (mode->vdisplay == 576)))
1303 tegra_hdmi_writel(hdmi,
1304 value | ARM_VIDEO_RANGE_FULL,
1305 HDMI_NV_PDISP_INPUT_CONTROL);
1306 else
1307 tegra_hdmi_writel(hdmi,
1308 value | ARM_VIDEO_RANGE_LIMITED,
1309 HDMI_NV_PDISP_INPUT_CONTROL);
1310
1311 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1312 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1313 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1314
1315 hdmi->dvi = !tegra_output_is_hdmi(output);
1316 if (!hdmi->dvi) {
1317 err = tegra_hdmi_setup_audio(hdmi);
1318 if (err < 0)
1319 hdmi->dvi = true;
1320 }
1321
1322 if (hdmi->config->has_hda)
1323 tegra_hdmi_write_eld(hdmi);
1324
1325 rekey = HDMI_REKEY_DEFAULT;
1326 value = HDMI_CTRL_REKEY(rekey);
1327 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1328 h_front_porch - rekey - 18) / 32);
1329
1330 if (!hdmi->dvi)
1331 value |= HDMI_CTRL_ENABLE;
1332
1333 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1334
1335 if (!hdmi->dvi) {
1336 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1337 tegra_hdmi_setup_audio_infoframe(hdmi);
1338
1339 if (hdmi->stereo)
1340 tegra_hdmi_setup_stereo_infoframe(hdmi);
1341 }
1342
1343 /* TMDS CONFIG */
1344 for (i = 0; i < hdmi->config->num_tmds; i++) {
1345 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1346 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1347 break;
1348 }
1349 }
1350
1351 tegra_hdmi_writel(hdmi,
1352 SOR_SEQ_PU_PC(0) |
1353 SOR_SEQ_PU_PC_ALT(0) |
1354 SOR_SEQ_PD_PC(8) |
1355 SOR_SEQ_PD_PC_ALT(8),
1356 HDMI_NV_PDISP_SOR_SEQ_CTL);
1357
1358 value = SOR_SEQ_INST_WAIT_TIME(1) |
1359 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1360 SOR_SEQ_INST_HALT |
1361 SOR_SEQ_INST_PIN_A_LOW |
1362 SOR_SEQ_INST_PIN_B_LOW |
1363 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1364
1365 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1366 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1367
1368 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1369 value &= ~SOR_CSTM_ROTCLK(~0);
1370 value |= SOR_CSTM_ROTCLK(2);
1371 value |= SOR_CSTM_PLLDIV;
1372 value &= ~SOR_CSTM_LVDS_ENABLE;
1373 value &= ~SOR_CSTM_MODE_MASK;
1374 value |= SOR_CSTM_MODE_TMDS;
1375 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1376
1377 /* start SOR */
1378 tegra_hdmi_writel(hdmi,
1379 SOR_PWR_NORMAL_STATE_PU |
1380 SOR_PWR_NORMAL_START_NORMAL |
1381 SOR_PWR_SAFE_STATE_PD |
1382 SOR_PWR_SETTING_NEW_TRIGGER,
1383 HDMI_NV_PDISP_SOR_PWR);
1384 tegra_hdmi_writel(hdmi,
1385 SOR_PWR_NORMAL_STATE_PU |
1386 SOR_PWR_NORMAL_START_NORMAL |
1387 SOR_PWR_SAFE_STATE_PD |
1388 SOR_PWR_SETTING_NEW_DONE,
1389 HDMI_NV_PDISP_SOR_PWR);
1390
1391 do {
1392 BUG_ON(--retries < 0);
1393 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1394 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1395
1396 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1397 SOR_STATE_ASY_OWNER_HEAD0 |
1398 SOR_STATE_ASY_SUBOWNER_BOTH |
1399 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1400 SOR_STATE_ASY_DEPOL_POS;
1401
1402 /* setup sync polarities */
1403 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1404 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1405
1406 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1407 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1408
1409 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1410 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1411
1412 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1413 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1414
1415 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1416
1417 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1418 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1419
1420 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1421 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1422 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1423 HDMI_NV_PDISP_SOR_STATE1);
1424 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1425
1426 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1427 value |= HDMI_ENABLE;
1428 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1429
1430 tegra_dc_commit(dc);
1431
1432 if (!hdmi->dvi) {
1433 tegra_hdmi_enable_avi_infoframe(hdmi);
1434 tegra_hdmi_enable_audio_infoframe(hdmi);
1435 tegra_hdmi_enable_audio(hdmi);
1436
1437 if (hdmi->stereo)
1438 tegra_hdmi_enable_stereo_infoframe(hdmi);
1439 }
1440
1441 /* TODO: add HDCP support */
1442 }
1443
1444 static int
1445 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1446 struct drm_crtc_state *crtc_state,
1447 struct drm_connector_state *conn_state)
1448 {
1449 struct tegra_output *output = encoder_to_output(encoder);
1450 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1451 unsigned long pclk = crtc_state->mode.clock * 1000;
1452 struct tegra_hdmi *hdmi = to_hdmi(output);
1453 int err;
1454
1455 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1456 pclk, 0);
1457 if (err < 0) {
1458 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1459 return err;
1460 }
1461
1462 return err;
1463 }
1464
1465 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1466 .disable = tegra_hdmi_encoder_disable,
1467 .enable = tegra_hdmi_encoder_enable,
1468 .atomic_check = tegra_hdmi_encoder_atomic_check,
1469 };
1470
1471 static int tegra_hdmi_init(struct host1x_client *client)
1472 {
1473 struct drm_device *drm = dev_get_drvdata(client->parent);
1474 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1475 int err;
1476
1477 hdmi->output.dev = client->dev;
1478
1479 drm_connector_init(drm, &hdmi->output.connector,
1480 &tegra_hdmi_connector_funcs,
1481 DRM_MODE_CONNECTOR_HDMIA);
1482 drm_connector_helper_add(&hdmi->output.connector,
1483 &tegra_hdmi_connector_helper_funcs);
1484 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1485
1486 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1487 DRM_MODE_ENCODER_TMDS, NULL);
1488 drm_encoder_helper_add(&hdmi->output.encoder,
1489 &tegra_hdmi_encoder_helper_funcs);
1490
1491 drm_connector_attach_encoder(&hdmi->output.connector,
1492 &hdmi->output.encoder);
1493 drm_connector_register(&hdmi->output.connector);
1494
1495 err = tegra_output_init(drm, &hdmi->output);
1496 if (err < 0) {
1497 dev_err(client->dev, "failed to initialize output: %d\n", err);
1498 return err;
1499 }
1500
1501 hdmi->output.encoder.possible_crtcs = 0x3;
1502
1503 err = regulator_enable(hdmi->hdmi);
1504 if (err < 0) {
1505 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1506 err);
1507 return err;
1508 }
1509
1510 err = regulator_enable(hdmi->pll);
1511 if (err < 0) {
1512 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1513 return err;
1514 }
1515
1516 err = regulator_enable(hdmi->vdd);
1517 if (err < 0) {
1518 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1519 return err;
1520 }
1521
1522 return 0;
1523 }
1524
1525 static int tegra_hdmi_exit(struct host1x_client *client)
1526 {
1527 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1528
1529 tegra_output_exit(&hdmi->output);
1530
1531 regulator_disable(hdmi->vdd);
1532 regulator_disable(hdmi->pll);
1533 regulator_disable(hdmi->hdmi);
1534
1535 return 0;
1536 }
1537
1538 static const struct host1x_client_ops hdmi_client_ops = {
1539 .init = tegra_hdmi_init,
1540 .exit = tegra_hdmi_exit,
1541 };
1542
1543 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1544 .tmds = tegra20_tmds_config,
1545 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1546 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1547 .fuse_override_value = 1 << 31,
1548 .has_sor_io_peak_current = false,
1549 .has_hda = false,
1550 .has_hbr = false,
1551 };
1552
1553 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1554 .tmds = tegra30_tmds_config,
1555 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1556 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1557 .fuse_override_value = 1 << 31,
1558 .has_sor_io_peak_current = false,
1559 .has_hda = true,
1560 .has_hbr = false,
1561 };
1562
1563 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1564 .tmds = tegra114_tmds_config,
1565 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1566 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1567 .fuse_override_value = 1 << 31,
1568 .has_sor_io_peak_current = true,
1569 .has_hda = true,
1570 .has_hbr = true,
1571 };
1572
1573 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1574 .tmds = tegra124_tmds_config,
1575 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1576 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1577 .fuse_override_value = 1 << 31,
1578 .has_sor_io_peak_current = true,
1579 .has_hda = true,
1580 .has_hbr = true,
1581 };
1582
1583 static const struct of_device_id tegra_hdmi_of_match[] = {
1584 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1585 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1586 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1587 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1588 { },
1589 };
1590 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1591
1592 static void hda_format_parse(unsigned int format, unsigned int *rate,
1593 unsigned int *channels)
1594 {
1595 unsigned int mul, div;
1596
1597 if (format & AC_FMT_BASE_44K)
1598 *rate = 44100;
1599 else
1600 *rate = 48000;
1601
1602 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
1603 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
1604
1605 *rate = *rate * (mul + 1) / (div + 1);
1606
1607 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
1608 }
1609
1610 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1611 {
1612 struct tegra_hdmi *hdmi = data;
1613 u32 value;
1614 int err;
1615
1616 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1617 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1618
1619 if (value & INT_CODEC_SCRATCH0) {
1620 unsigned int format;
1621 u32 value;
1622
1623 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1624
1625 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1626 unsigned int sample_rate, channels;
1627
1628 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1629
1630 hda_format_parse(format, &sample_rate, &channels);
1631
1632 hdmi->audio_sample_rate = sample_rate;
1633 hdmi->audio_channels = channels;
1634
1635 err = tegra_hdmi_setup_audio(hdmi);
1636 if (err < 0) {
1637 tegra_hdmi_disable_audio_infoframe(hdmi);
1638 tegra_hdmi_disable_audio(hdmi);
1639 } else {
1640 tegra_hdmi_setup_audio_infoframe(hdmi);
1641 tegra_hdmi_enable_audio_infoframe(hdmi);
1642 tegra_hdmi_enable_audio(hdmi);
1643 }
1644 } else {
1645 tegra_hdmi_disable_audio_infoframe(hdmi);
1646 tegra_hdmi_disable_audio(hdmi);
1647 }
1648 }
1649
1650 return IRQ_HANDLED;
1651 }
1652
1653 static int tegra_hdmi_probe(struct platform_device *pdev)
1654 {
1655 struct tegra_hdmi *hdmi;
1656 struct resource *regs;
1657 int err;
1658
1659 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1660 if (!hdmi)
1661 return -ENOMEM;
1662
1663 hdmi->config = of_device_get_match_data(&pdev->dev);
1664 hdmi->dev = &pdev->dev;
1665
1666 hdmi->audio_source = AUTO;
1667 hdmi->audio_sample_rate = 48000;
1668 hdmi->audio_channels = 2;
1669 hdmi->stereo = false;
1670 hdmi->dvi = false;
1671
1672 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1673 if (IS_ERR(hdmi->clk)) {
1674 dev_err(&pdev->dev, "failed to get clock\n");
1675 return PTR_ERR(hdmi->clk);
1676 }
1677
1678 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1679 if (IS_ERR(hdmi->rst)) {
1680 dev_err(&pdev->dev, "failed to get reset\n");
1681 return PTR_ERR(hdmi->rst);
1682 }
1683
1684 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1685 if (IS_ERR(hdmi->clk_parent))
1686 return PTR_ERR(hdmi->clk_parent);
1687
1688 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1689 if (err < 0) {
1690 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1691 return err;
1692 }
1693
1694 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1695 if (IS_ERR(hdmi->hdmi)) {
1696 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1697 return PTR_ERR(hdmi->hdmi);
1698 }
1699
1700 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1701 if (IS_ERR(hdmi->pll)) {
1702 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1703 return PTR_ERR(hdmi->pll);
1704 }
1705
1706 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1707 if (IS_ERR(hdmi->vdd)) {
1708 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1709 return PTR_ERR(hdmi->vdd);
1710 }
1711
1712 hdmi->output.notifier = cec_notifier_get(&pdev->dev);
1713 if (hdmi->output.notifier == NULL)
1714 return -ENOMEM;
1715
1716 hdmi->output.dev = &pdev->dev;
1717
1718 err = tegra_output_probe(&hdmi->output);
1719 if (err < 0)
1720 return err;
1721
1722 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1723 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1724 if (IS_ERR(hdmi->regs))
1725 return PTR_ERR(hdmi->regs);
1726
1727 err = platform_get_irq(pdev, 0);
1728 if (err < 0)
1729 return err;
1730
1731 hdmi->irq = err;
1732
1733 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1734 dev_name(hdmi->dev), hdmi);
1735 if (err < 0) {
1736 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1737 hdmi->irq, err);
1738 return err;
1739 }
1740
1741 platform_set_drvdata(pdev, hdmi);
1742 pm_runtime_enable(&pdev->dev);
1743
1744 INIT_LIST_HEAD(&hdmi->client.list);
1745 hdmi->client.ops = &hdmi_client_ops;
1746 hdmi->client.dev = &pdev->dev;
1747
1748 err = host1x_client_register(&hdmi->client);
1749 if (err < 0) {
1750 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1751 err);
1752 return err;
1753 }
1754
1755 return 0;
1756 }
1757
1758 static int tegra_hdmi_remove(struct platform_device *pdev)
1759 {
1760 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1761 int err;
1762
1763 pm_runtime_disable(&pdev->dev);
1764
1765 err = host1x_client_unregister(&hdmi->client);
1766 if (err < 0) {
1767 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1768 err);
1769 return err;
1770 }
1771
1772 tegra_output_remove(&hdmi->output);
1773
1774 if (hdmi->output.notifier)
1775 cec_notifier_put(hdmi->output.notifier);
1776
1777 return 0;
1778 }
1779
1780 #ifdef CONFIG_PM
1781 static int tegra_hdmi_suspend(struct device *dev)
1782 {
1783 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1784 int err;
1785
1786 err = reset_control_assert(hdmi->rst);
1787 if (err < 0) {
1788 dev_err(dev, "failed to assert reset: %d\n", err);
1789 return err;
1790 }
1791
1792 usleep_range(1000, 2000);
1793
1794 clk_disable_unprepare(hdmi->clk);
1795
1796 return 0;
1797 }
1798
1799 static int tegra_hdmi_resume(struct device *dev)
1800 {
1801 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1802 int err;
1803
1804 err = clk_prepare_enable(hdmi->clk);
1805 if (err < 0) {
1806 dev_err(dev, "failed to enable clock: %d\n", err);
1807 return err;
1808 }
1809
1810 usleep_range(1000, 2000);
1811
1812 err = reset_control_deassert(hdmi->rst);
1813 if (err < 0) {
1814 dev_err(dev, "failed to deassert reset: %d\n", err);
1815 clk_disable_unprepare(hdmi->clk);
1816 return err;
1817 }
1818
1819 return 0;
1820 }
1821 #endif
1822
1823 static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1824 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1825 };
1826
1827 struct platform_driver tegra_hdmi_driver = {
1828 .driver = {
1829 .name = "tegra-hdmi",
1830 .of_match_table = tegra_hdmi_of_match,
1831 .pm = &tegra_hdmi_pm_ops,
1832 },
1833 .probe = tegra_hdmi_probe,
1834 .remove = tegra_hdmi_remove,
1835 };
Linux with added FPC-III support