| blob | b69be5c499cfc69f8df1902fffd3d0d73eb47280 |
1 /*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
12 #include "skeleton.dtsi"
13 #include "imx27-pinfunc.h"
15 #include <dt-bindings/clock/imx27-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
20 / {
21 aliases {
22 ethernet0 = &fec;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 spi0 = &cspi1;
38 spi1 = &cspi2;
39 spi2 = &cspi3;
40 };
42 aitc: aitc-interrupt-controller@e0000000 {
43 compatible = "fsl,imx27-aitc", "fsl,avic";
44 interrupt-controller;
45 #interrupt-cells = <1>;
46 reg = <0x10040000 0x1000>;
47 };
49 clocks {
50 #address-cells = <1>;
51 #size-cells = <0>;
53 osc26m {
54 compatible = "fsl,imx-osc26m", "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <26000000>;
57 };
58 };
60 cpus {
61 #size-cells = <0>;
62 #address-cells = <1>;
64 cpu: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,arm926ej-s";
67 operating-points = <
68 /* kHz uV */
69 266000 1300000
70 399000 1450000
71 >;
72 clock-latency = <62500>;
73 clocks = <&clks IMX27_CLK_CPU_DIV>;
74 voltage-tolerance = <5>;
75 };
76 };
78 soc {
79 #address-cells = <1>;
80 #size-cells = <1>;
81 compatible = "simple-bus";
82 interrupt-parent = <&aitc>;
83 ranges;
85 aipi@10000000 { /* AIPI1 */
86 compatible = "fsl,aipi-bus", "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x10000000 0x20000>;
90 ranges;
92 dma: dma@10001000 {
93 compatible = "fsl,imx27-dma";
94 reg = <0x10001000 0x1000>;
95 interrupts = <32>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
98 clock-names = "ipg", "ahb";
99 #dma-cells = <1>;
100 #dma-channels = <16>;
101 };
103 wdog: wdog@10002000 {
104 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
105 reg = <0x10002000 0x1000>;
106 interrupts = <27>;
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
108 };
110 gpt1: timer@10003000 {
111 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
112 reg = <0x10003000 0x1000>;
113 interrupts = <26>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
116 clock-names = "ipg", "per";
117 };
119 gpt2: timer@10004000 {
120 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
121 reg = <0x10004000 0x1000>;
122 interrupts = <25>;
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
125 clock-names = "ipg", "per";
126 };
128 gpt3: timer@10005000 {
129 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
130 reg = <0x10005000 0x1000>;
131 interrupts = <24>;
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
134 clock-names = "ipg", "per";
135 };
137 pwm: pwm@10006000 {
138 #pwm-cells = <2>;
139 compatible = "fsl,imx27-pwm";
140 reg = <0x10006000 0x1000>;
141 interrupts = <23>;
142 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
143 <&clks IMX27_CLK_PER1_GATE>;
144 clock-names = "ipg", "per";
145 };
147 kpp: kpp@10008000 {
148 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
149 reg = <0x10008000 0x1000>;
150 interrupts = <21>;
151 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
152 status = "disabled";
153 };
155 owire: owire@10009000 {
156 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
157 reg = <0x10009000 0x1000>;
158 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
159 status = "disabled";
160 };
162 uart1: serial@1000a000 {
163 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
164 reg = <0x1000a000 0x1000>;
165 interrupts = <20>;
166 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
167 <&clks IMX27_CLK_PER1_GATE>;
168 clock-names = "ipg", "per";
169 status = "disabled";
170 };
172 uart2: serial@1000b000 {
173 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
174 reg = <0x1000b000 0x1000>;
175 interrupts = <19>;
176 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
177 <&clks IMX27_CLK_PER1_GATE>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
182 uart3: serial@1000c000 {
183 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
184 reg = <0x1000c000 0x1000>;
185 interrupts = <18>;
186 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
187 <&clks IMX27_CLK_PER1_GATE>;
188 clock-names = "ipg", "per";
189 status = "disabled";
190 };
192 uart4: serial@1000d000 {
193 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
194 reg = <0x1000d000 0x1000>;
195 interrupts = <17>;
196 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
197 <&clks IMX27_CLK_PER1_GATE>;
198 clock-names = "ipg", "per";
199 status = "disabled";
200 };
202 cspi1: cspi@1000e000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,imx27-cspi";
206 reg = <0x1000e000 0x1000>;
207 interrupts = <16>;
208 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
209 <&clks IMX27_CLK_PER2_GATE>;
210 clock-names = "ipg", "per";
211 status = "disabled";
212 };
214 cspi2: cspi@1000f000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,imx27-cspi";
218 reg = <0x1000f000 0x1000>;
219 interrupts = <15>;
220 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
221 <&clks IMX27_CLK_PER2_GATE>;
222 clock-names = "ipg", "per";
223 status = "disabled";
224 };
226 ssi1: ssi@10010000 {
227 #sound-dai-cells = <0>;
228 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
229 reg = <0x10010000 0x1000>;
230 interrupts = <14>;
231 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
232 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
233 dma-names = "rx0", "tx0", "rx1", "tx1";
234 fsl,fifo-depth = <8>;
235 status = "disabled";
236 };
238 ssi2: ssi@10011000 {
239 #sound-dai-cells = <0>;
240 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
241 reg = <0x10011000 0x1000>;
242 interrupts = <13>;
243 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
244 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
245 dma-names = "rx0", "tx0", "rx1", "tx1";
246 fsl,fifo-depth = <8>;
247 status = "disabled";
248 };
250 i2c1: i2c@10012000 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
254 reg = <0x10012000 0x1000>;
255 interrupts = <12>;
256 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
257 status = "disabled";
258 };
260 sdhci1: sdhci@10013000 {
261 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
262 reg = <0x10013000 0x1000>;
263 interrupts = <11>;
264 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
265 <&clks IMX27_CLK_PER2_GATE>;
266 clock-names = "ipg", "per";
267 dmas = <&dma 7>;
268 dma-names = "rx-tx";
269 status = "disabled";
270 };
272 sdhci2: sdhci@10014000 {
273 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
274 reg = <0x10014000 0x1000>;
275 interrupts = <10>;
276 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
277 <&clks IMX27_CLK_PER2_GATE>;
278 clock-names = "ipg", "per";
279 dmas = <&dma 6>;
280 dma-names = "rx-tx";
281 status = "disabled";
282 };
284 iomuxc: iomuxc@10015000 {
285 compatible = "fsl,imx27-iomuxc";
286 reg = <0x10015000 0x600>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
291 gpio1: gpio@10015000 {
292 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
293 reg = <0x10015000 0x100>;
294 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
295 interrupts = <8>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
302 gpio2: gpio@10015100 {
303 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
304 reg = <0x10015100 0x100>;
305 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
306 interrupts = <8>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
313 gpio3: gpio@10015200 {
314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
315 reg = <0x10015200 0x100>;
316 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
317 interrupts = <8>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
324 gpio4: gpio@10015300 {
325 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
326 reg = <0x10015300 0x100>;
327 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
328 interrupts = <8>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
335 gpio5: gpio@10015400 {
336 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
337 reg = <0x10015400 0x100>;
338 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
339 interrupts = <8>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 };
346 gpio6: gpio@10015500 {
347 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
348 reg = <0x10015500 0x100>;
349 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
350 interrupts = <8>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 };
356 };
358 audmux: audmux@10016000 {
359 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
360 reg = <0x10016000 0x1000>;
361 clocks = <&clks IMX27_CLK_DUMMY>;
362 clock-names = "audmux";
363 status = "disabled";
364 };
366 cspi3: cspi@10017000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "fsl,imx27-cspi";
370 reg = <0x10017000 0x1000>;
371 interrupts = <6>;
372 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
373 <&clks IMX27_CLK_PER2_GATE>;
374 clock-names = "ipg", "per";
375 status = "disabled";
376 };
378 gpt4: timer@10019000 {
379 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
380 reg = <0x10019000 0x1000>;
381 interrupts = <4>;
382 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
383 <&clks IMX27_CLK_PER1_GATE>;
384 clock-names = "ipg", "per";
385 };
387 gpt5: timer@1001a000 {
388 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
389 reg = <0x1001a000 0x1000>;
390 interrupts = <3>;
391 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
392 <&clks IMX27_CLK_PER1_GATE>;
393 clock-names = "ipg", "per";
394 };
396 uart5: serial@1001b000 {
397 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
398 reg = <0x1001b000 0x1000>;
399 interrupts = <49>;
400 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
401 <&clks IMX27_CLK_PER1_GATE>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
406 uart6: serial@1001c000 {
407 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
408 reg = <0x1001c000 0x1000>;
409 interrupts = <48>;
410 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
411 <&clks IMX27_CLK_PER1_GATE>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
416 i2c2: i2c@1001d000 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
420 reg = <0x1001d000 0x1000>;
421 interrupts = <1>;
422 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
423 status = "disabled";
424 };
426 sdhci3: sdhci@1001e000 {
427 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
428 reg = <0x1001e000 0x1000>;
429 interrupts = <9>;
430 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
431 <&clks IMX27_CLK_PER2_GATE>;
432 clock-names = "ipg", "per";
433 dmas = <&dma 36>;
434 dma-names = "rx-tx";
435 status = "disabled";
436 };
438 gpt6: timer@1001f000 {
439 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
440 reg = <0x1001f000 0x1000>;
441 interrupts = <2>;
442 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
443 <&clks IMX27_CLK_PER1_GATE>;
444 clock-names = "ipg", "per";
445 };
446 };
448 aipi@10020000 { /* AIPI2 */
449 compatible = "fsl,aipi-bus", "simple-bus";
450 #address-cells = <1>;
451 #size-cells = <1>;
452 reg = <0x10020000 0x20000>;
453 ranges;
455 fb: fb@10021000 {
456 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
457 interrupts = <61>;
458 reg = <0x10021000 0x1000>;
459 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
460 <&clks IMX27_CLK_LCDC_AHB_GATE>,
461 <&clks IMX27_CLK_PER3_GATE>;
462 clock-names = "ipg", "ahb", "per";
463 status = "disabled";
464 };
466 coda: coda@10023000 {
467 compatible = "fsl,imx27-vpu", "cnm,codadx6";
468 reg = <0x10023000 0x0200>;
469 interrupts = <53>;
470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
471 <&clks IMX27_CLK_VPU_AHB_GATE>;
472 clock-names = "per", "ahb";
473 iram = <&iram>;
474 };
476 usbotg: usb@10024000 {
477 compatible = "fsl,imx27-usb";
478 reg = <0x10024000 0x200>;
479 interrupts = <56>;
480 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
481 fsl,usbmisc = <&usbmisc 0>;
482 status = "disabled";
483 };
485 usbh1: usb@10024200 {
486 compatible = "fsl,imx27-usb";
487 reg = <0x10024200 0x200>;
488 interrupts = <54>;
489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
490 fsl,usbmisc = <&usbmisc 1>;
491 dr_mode = "host";
492 status = "disabled";
493 };
495 usbh2: usb@10024400 {
496 compatible = "fsl,imx27-usb";
497 reg = <0x10024400 0x200>;
498 interrupts = <55>;
499 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
500 fsl,usbmisc = <&usbmisc 2>;
501 dr_mode = "host";
502 status = "disabled";
503 };
505 usbmisc: usbmisc@10024600 {
506 #index-cells = <1>;
507 compatible = "fsl,imx27-usbmisc";
508 reg = <0x10024600 0x200>;
509 clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
510 };
512 sahara2: sahara@10025000 {
513 compatible = "fsl,imx27-sahara";
514 reg = <0x10025000 0x1000>;
515 interrupts = <59>;
516 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
517 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
518 clock-names = "ipg", "ahb";
519 };
521 clks: ccm@10027000{
522 compatible = "fsl,imx27-ccm";
523 reg = <0x10027000 0x1000>;
524 #clock-cells = <1>;
525 };
527 iim: iim@10028000 {
528 compatible = "fsl,imx27-iim";
529 reg = <0x10028000 0x1000>;
530 interrupts = <62>;
531 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
532 };
534 fec: ethernet@1002b000 {
535 compatible = "fsl,imx27-fec";
536 reg = <0x1002b000 0x1000>;
537 interrupts = <50>;
538 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
539 <&clks IMX27_CLK_FEC_AHB_GATE>;
540 clock-names = "ipg", "ahb";
541 status = "disabled";
542 };
543 };
545 nfc: nand@d8000000 {
546 #address-cells = <1>;
547 #size-cells = <1>;
548 compatible = "fsl,imx27-nand";
549 reg = <0xd8000000 0x1000>;
550 interrupts = <29>;
551 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
552 status = "disabled";
553 };
555 weim: weim@d8002000 {
556 #address-cells = <2>;
557 #size-cells = <1>;
558 compatible = "fsl,imx27-weim";
559 reg = <0xd8002000 0x1000>;
560 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
561 ranges = <
562 0 0 0xc0000000 0x08000000
563 1 0 0xc8000000 0x08000000
564 2 0 0xd0000000 0x02000000
565 3 0 0xd2000000 0x02000000
566 4 0 0xd4000000 0x02000000
567 5 0 0xd6000000 0x02000000
568 >;
569 status = "disabled";
570 };
572 iram: iram@ffff4c00 {
573 compatible = "mmio-sram";
574 reg = <0xffff4c00 0xb400>;
575 };
576 };
577 };