| blob | 01a9f742b08f4fe2bf3a4184dbf34dd46dd7ccf9 |
1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include "skeleton.dtsi"
11 / {
12 compatible = "nvidia,tegra124";
13 interrupt-parent = <&lic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 pcie-controller@0,01003000 {
18 compatible = "nvidia,tegra124-pcie";
19 device_type = "pci";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
33 #address-cells = <3>;
34 #size-cells = <2>;
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43 <&tegra_car TEGRA124_CLK_AFI>,
44 <&tegra_car TEGRA124_CLK_PLL_E>,
45 <&tegra_car TEGRA124_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
51 status = "disabled";
53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
54 phy-names = "pcie";
56 pci@1,0 {
57 device_type = "pci";
58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
59 reg = <0x000800 0 0 0 0>;
60 status = "disabled";
62 #address-cells = <3>;
63 #size-cells = <2>;
64 ranges;
66 nvidia,num-lanes = <2>;
67 };
69 pci@2,0 {
70 device_type = "pci";
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
73 status = "disabled";
75 #address-cells = <3>;
76 #size-cells = <2>;
77 ranges;
79 nvidia,num-lanes = <1>;
80 };
81 };
83 host1x@0,50000000 {
84 compatible = "nvidia,tegra124-host1x", "simple-bus";
85 reg = <0x0 0x50000000 0x0 0x00034000>;
86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
88 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
89 resets = <&tegra_car 28>;
90 reset-names = "host1x";
92 #address-cells = <2>;
93 #size-cells = <2>;
95 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
97 dc@0,54200000 {
98 compatible = "nvidia,tegra124-dc";
99 reg = <0x0 0x54200000 0x0 0x00040000>;
100 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
102 <&tegra_car TEGRA124_CLK_PLL_P>;
103 clock-names = "dc", "parent";
104 resets = <&tegra_car 27>;
105 reset-names = "dc";
107 iommus = <&mc TEGRA_SWGROUP_DC>;
109 nvidia,head = <0>;
110 };
112 dc@0,54240000 {
113 compatible = "nvidia,tegra124-dc";
114 reg = <0x0 0x54240000 0x0 0x00040000>;
115 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
117 <&tegra_car TEGRA124_CLK_PLL_P>;
118 clock-names = "dc", "parent";
119 resets = <&tegra_car 26>;
120 reset-names = "dc";
122 iommus = <&mc TEGRA_SWGROUP_DCB>;
124 nvidia,head = <1>;
125 };
127 hdmi@0,54280000 {
128 compatible = "nvidia,tegra124-hdmi";
129 reg = <0x0 0x54280000 0x0 0x00040000>;
130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
133 clock-names = "hdmi", "parent";
134 resets = <&tegra_car 51>;
135 reset-names = "hdmi";
136 status = "disabled";
137 };
139 sor@0,54540000 {
140 compatible = "nvidia,tegra124-sor";
141 reg = <0x0 0x54540000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
144 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
145 <&tegra_car TEGRA124_CLK_PLL_DP>,
146 <&tegra_car TEGRA124_CLK_CLK_M>;
147 clock-names = "sor", "parent", "dp", "safe";
148 resets = <&tegra_car 182>;
149 reset-names = "sor";
150 status = "disabled";
151 };
153 dpaux: dpaux@0,545c0000 {
154 compatible = "nvidia,tegra124-dpaux";
155 reg = <0x0 0x545c0000 0x0 0x00040000>;
156 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
158 <&tegra_car TEGRA124_CLK_PLL_DP>;
159 clock-names = "dpaux", "parent";
160 resets = <&tegra_car 181>;
161 reset-names = "dpaux";
162 status = "disabled";
163 };
164 };
166 gic: interrupt-controller@0,50041000 {
167 compatible = "arm,cortex-a15-gic";
168 #interrupt-cells = <3>;
169 interrupt-controller;
170 reg = <0x0 0x50041000 0x0 0x1000>,
171 <0x0 0x50042000 0x0 0x1000>,
172 <0x0 0x50044000 0x0 0x2000>,
173 <0x0 0x50046000 0x0 0x2000>;
174 interrupts = <GIC_PPI 9
175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
176 interrupt-parent = <&gic>;
177 };
179 gpu@0,57000000 {
180 compatible = "nvidia,gk20a";
181 reg = <0x0 0x57000000 0x0 0x01000000>,
182 <0x0 0x58000000 0x0 0x01000000>;
183 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "stall", "nonstall";
186 clocks = <&tegra_car TEGRA124_CLK_GPU>,
187 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
188 clock-names = "gpu", "pwr";
189 resets = <&tegra_car 184>;
190 reset-names = "gpu";
191 status = "disabled";
192 };
194 lic: interrupt-controller@60004000 {
195 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
196 reg = <0x0 0x60004000 0x0 0x100>,
197 <0x0 0x60004100 0x0 0x100>,
198 <0x0 0x60004200 0x0 0x100>,
199 <0x0 0x60004300 0x0 0x100>,
200 <0x0 0x60004400 0x0 0x100>;
201 interrupt-controller;
202 #interrupt-cells = <3>;
203 interrupt-parent = <&gic>;
204 };
206 timer@0,60005000 {
207 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
208 reg = <0x0 0x60005000 0x0 0x400>;
209 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
216 };
218 tegra_car: clock@0,60006000 {
219 compatible = "nvidia,tegra124-car";
220 reg = <0x0 0x60006000 0x0 0x1000>;
221 #clock-cells = <1>;
222 #reset-cells = <1>;
223 nvidia,external-memory-controller = <&emc>;
224 };
226 flow-controller@0,60007000 {
227 compatible = "nvidia,tegra124-flowctrl";
228 reg = <0x0 0x60007000 0x0 0x1000>;
229 };
231 actmon@0,6000c800 {
232 compatible = "nvidia,tegra124-actmon";
233 reg = <0x0 0x6000c800 0x0 0x400>;
234 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
236 <&tegra_car TEGRA124_CLK_EMC>;
237 clock-names = "actmon", "emc";
238 resets = <&tegra_car 119>;
239 reset-names = "actmon";
240 };
242 gpio: gpio@0,6000d000 {
243 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
244 reg = <0x0 0x6000d000 0x0 0x1000>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 #interrupt-cells = <2>;
256 interrupt-controller;
257 };
259 apbdma: dma@0,60020000 {
260 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
261 reg = <0x0 0x60020000 0x0 0x1400>;
262 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
295 resets = <&tegra_car 34>;
296 reset-names = "dma";
297 #dma-cells = <1>;
298 };
300 apbmisc@0,70000800 {
301 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
302 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
303 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
304 };
306 pinmux: pinmux@0,70000868 {
307 compatible = "nvidia,tegra124-pinmux";
308 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
309 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
310 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
311 };
313 /*
314 * There are two serial driver i.e. 8250 based simple serial
315 * driver and APB DMA based serial driver for higher baudrate
316 * and performace. To enable the 8250 based driver, the compatible
317 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
318 * the APB DMA based serial driver, the comptible is
319 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
320 */
321 uarta: serial@0,70006000 {
322 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
323 reg = <0x0 0x70006000 0x0 0x40>;
324 reg-shift = <2>;
325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
327 resets = <&tegra_car 6>;
328 reset-names = "serial";
329 dmas = <&apbdma 8>, <&apbdma 8>;
330 dma-names = "rx", "tx";
331 status = "disabled";
332 };
334 uartb: serial@0,70006040 {
335 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
336 reg = <0x0 0x70006040 0x0 0x40>;
337 reg-shift = <2>;
338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
340 resets = <&tegra_car 7>;
341 reset-names = "serial";
342 dmas = <&apbdma 9>, <&apbdma 9>;
343 dma-names = "rx", "tx";
344 status = "disabled";
345 };
347 uartc: serial@0,70006200 {
348 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
349 reg = <0x0 0x70006200 0x0 0x40>;
350 reg-shift = <2>;
351 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
353 resets = <&tegra_car 55>;
354 reset-names = "serial";
355 dmas = <&apbdma 10>, <&apbdma 10>;
356 dma-names = "rx", "tx";
357 status = "disabled";
358 };
360 uartd: serial@0,70006300 {
361 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
362 reg = <0x0 0x70006300 0x0 0x40>;
363 reg-shift = <2>;
364 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
366 resets = <&tegra_car 65>;
367 reset-names = "serial";
368 dmas = <&apbdma 19>, <&apbdma 19>;
369 dma-names = "rx", "tx";
370 status = "disabled";
371 };
373 pwm: pwm@0,7000a000 {
374 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
375 reg = <0x0 0x7000a000 0x0 0x100>;
376 #pwm-cells = <2>;
377 clocks = <&tegra_car TEGRA124_CLK_PWM>;
378 resets = <&tegra_car 17>;
379 reset-names = "pwm";
380 status = "disabled";
381 };
383 i2c@0,7000c000 {
384 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
385 reg = <0x0 0x7000c000 0x0 0x100>;
386 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
390 clock-names = "div-clk";
391 resets = <&tegra_car 12>;
392 reset-names = "i2c";
393 dmas = <&apbdma 21>, <&apbdma 21>;
394 dma-names = "rx", "tx";
395 status = "disabled";
396 };
398 i2c@0,7000c400 {
399 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
400 reg = <0x0 0x7000c400 0x0 0x100>;
401 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
405 clock-names = "div-clk";
406 resets = <&tegra_car 54>;
407 reset-names = "i2c";
408 dmas = <&apbdma 22>, <&apbdma 22>;
409 dma-names = "rx", "tx";
410 status = "disabled";
411 };
413 i2c@0,7000c500 {
414 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
415 reg = <0x0 0x7000c500 0x0 0x100>;
416 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
420 clock-names = "div-clk";
421 resets = <&tegra_car 67>;
422 reset-names = "i2c";
423 dmas = <&apbdma 23>, <&apbdma 23>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
428 i2c@0,7000c700 {
429 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
430 reg = <0x0 0x7000c700 0x0 0x100>;
431 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
435 clock-names = "div-clk";
436 resets = <&tegra_car 103>;
437 reset-names = "i2c";
438 dmas = <&apbdma 26>, <&apbdma 26>;
439 dma-names = "rx", "tx";
440 status = "disabled";
441 };
443 i2c@0,7000d000 {
444 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
445 reg = <0x0 0x7000d000 0x0 0x100>;
446 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
450 clock-names = "div-clk";
451 resets = <&tegra_car 47>;
452 reset-names = "i2c";
453 dmas = <&apbdma 24>, <&apbdma 24>;
454 dma-names = "rx", "tx";
455 status = "disabled";
456 };
458 i2c@0,7000d100 {
459 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
460 reg = <0x0 0x7000d100 0x0 0x100>;
461 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
465 clock-names = "div-clk";
466 resets = <&tegra_car 166>;
467 reset-names = "i2c";
468 dmas = <&apbdma 30>, <&apbdma 30>;
469 dma-names = "rx", "tx";
470 status = "disabled";
471 };
473 spi@0,7000d400 {
474 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
475 reg = <0x0 0x7000d400 0x0 0x200>;
476 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
480 clock-names = "spi";
481 resets = <&tegra_car 41>;
482 reset-names = "spi";
483 dmas = <&apbdma 15>, <&apbdma 15>;
484 dma-names = "rx", "tx";
485 status = "disabled";
486 };
488 spi@0,7000d600 {
489 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
490 reg = <0x0 0x7000d600 0x0 0x200>;
491 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
495 clock-names = "spi";
496 resets = <&tegra_car 44>;
497 reset-names = "spi";
498 dmas = <&apbdma 16>, <&apbdma 16>;
499 dma-names = "rx", "tx";
500 status = "disabled";
501 };
503 spi@0,7000d800 {
504 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
505 reg = <0x0 0x7000d800 0x0 0x200>;
506 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
510 clock-names = "spi";
511 resets = <&tegra_car 46>;
512 reset-names = "spi";
513 dmas = <&apbdma 17>, <&apbdma 17>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
518 spi@0,7000da00 {
519 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
520 reg = <0x0 0x7000da00 0x0 0x200>;
521 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
525 clock-names = "spi";
526 resets = <&tegra_car 68>;
527 reset-names = "spi";
528 dmas = <&apbdma 18>, <&apbdma 18>;
529 dma-names = "rx", "tx";
530 status = "disabled";
531 };
533 spi@0,7000dc00 {
534 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
535 reg = <0x0 0x7000dc00 0x0 0x200>;
536 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
540 clock-names = "spi";
541 resets = <&tegra_car 104>;
542 reset-names = "spi";
543 dmas = <&apbdma 27>, <&apbdma 27>;
544 dma-names = "rx", "tx";
545 status = "disabled";
546 };
548 spi@0,7000de00 {
549 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
550 reg = <0x0 0x7000de00 0x0 0x200>;
551 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
555 clock-names = "spi";
556 resets = <&tegra_car 105>;
557 reset-names = "spi";
558 dmas = <&apbdma 28>, <&apbdma 28>;
559 dma-names = "rx", "tx";
560 status = "disabled";
561 };
563 rtc@0,7000e000 {
564 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
565 reg = <0x0 0x7000e000 0x0 0x100>;
566 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&tegra_car TEGRA124_CLK_RTC>;
568 };
570 pmc@0,7000e400 {
571 compatible = "nvidia,tegra124-pmc";
572 reg = <0x0 0x7000e400 0x0 0x400>;
573 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
574 clock-names = "pclk", "clk32k_in";
575 };
577 fuse@0,7000f800 {
578 compatible = "nvidia,tegra124-efuse";
579 reg = <0x0 0x7000f800 0x0 0x400>;
580 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
581 clock-names = "fuse";
582 resets = <&tegra_car 39>;
583 reset-names = "fuse";
584 };
586 mc: memory-controller@0,70019000 {
587 compatible = "nvidia,tegra124-mc";
588 reg = <0x0 0x70019000 0x0 0x1000>;
589 clocks = <&tegra_car TEGRA124_CLK_MC>;
590 clock-names = "mc";
592 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
594 #iommu-cells = <1>;
595 };
597 emc: emc@0,7001b000 {
598 compatible = "nvidia,tegra124-emc";
599 reg = <0x0 0x7001b000 0x0 0x1000>;
601 nvidia,memory-controller = <&mc>;
602 };
604 sata@0,70020000 {
605 compatible = "nvidia,tegra124-ahci";
607 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
608 <0x0 0x70020000 0x0 0x7000>; /* SATA */
610 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&tegra_car TEGRA124_CLK_SATA>,
613 <&tegra_car TEGRA124_CLK_SATA_OOB>,
614 <&tegra_car TEGRA124_CLK_CML1>,
615 <&tegra_car TEGRA124_CLK_PLL_E>;
616 clock-names = "sata", "sata-oob", "cml1", "pll_e";
618 resets = <&tegra_car 124>,
619 <&tegra_car 123>,
620 <&tegra_car 129>;
621 reset-names = "sata", "sata-oob", "sata-cold";
623 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
624 phy-names = "sata-phy";
626 status = "disabled";
627 };
629 hda@0,70030000 {
630 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
631 reg = <0x0 0x70030000 0x0 0x10000>;
632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&tegra_car TEGRA124_CLK_HDA>,
634 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
635 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
636 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
637 resets = <&tegra_car 125>, /* hda */
638 <&tegra_car 128>, /* hda2hdmi */
639 <&tegra_car 111>; /* hda2codec_2x */
640 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
641 status = "disabled";
642 };
644 padctl: padctl@0,7009f000 {
645 compatible = "nvidia,tegra124-xusb-padctl";
646 reg = <0x0 0x7009f000 0x0 0x1000>;
647 resets = <&tegra_car 142>;
648 reset-names = "padctl";
650 #phy-cells = <1>;
651 };
653 sdhci@0,700b0000 {
654 compatible = "nvidia,tegra124-sdhci";
655 reg = <0x0 0x700b0000 0x0 0x200>;
656 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
658 resets = <&tegra_car 14>;
659 reset-names = "sdhci";
660 status = "disabled";
661 };
663 sdhci@0,700b0200 {
664 compatible = "nvidia,tegra124-sdhci";
665 reg = <0x0 0x700b0200 0x0 0x200>;
666 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
668 resets = <&tegra_car 9>;
669 reset-names = "sdhci";
670 status = "disabled";
671 };
673 sdhci@0,700b0400 {
674 compatible = "nvidia,tegra124-sdhci";
675 reg = <0x0 0x700b0400 0x0 0x200>;
676 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
678 resets = <&tegra_car 69>;
679 reset-names = "sdhci";
680 status = "disabled";
681 };
683 sdhci@0,700b0600 {
684 compatible = "nvidia,tegra124-sdhci";
685 reg = <0x0 0x700b0600 0x0 0x200>;
686 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
688 resets = <&tegra_car 15>;
689 reset-names = "sdhci";
690 status = "disabled";
691 };
693 soctherm: thermal-sensor@0,700e2000 {
694 compatible = "nvidia,tegra124-soctherm";
695 reg = <0x0 0x700e2000 0x0 0x1000>;
696 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
698 <&tegra_car TEGRA124_CLK_SOC_THERM>;
699 clock-names = "tsensor", "soctherm";
700 resets = <&tegra_car 78>;
701 reset-names = "soctherm";
702 #thermal-sensor-cells = <1>;
703 };
705 ahub@0,70300000 {
706 compatible = "nvidia,tegra124-ahub";
707 reg = <0x0 0x70300000 0x0 0x200>,
708 <0x0 0x70300800 0x0 0x800>,
709 <0x0 0x70300200 0x0 0x600>;
710 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
712 <&tegra_car TEGRA124_CLK_APBIF>;
713 clock-names = "d_audio", "apbif";
714 resets = <&tegra_car 106>, /* d_audio */
715 <&tegra_car 107>, /* apbif */
716 <&tegra_car 30>, /* i2s0 */
717 <&tegra_car 11>, /* i2s1 */
718 <&tegra_car 18>, /* i2s2 */
719 <&tegra_car 101>, /* i2s3 */
720 <&tegra_car 102>, /* i2s4 */
721 <&tegra_car 108>, /* dam0 */
722 <&tegra_car 109>, /* dam1 */
723 <&tegra_car 110>, /* dam2 */
724 <&tegra_car 10>, /* spdif */
725 <&tegra_car 153>, /* amx */
726 <&tegra_car 185>, /* amx1 */
727 <&tegra_car 154>, /* adx */
728 <&tegra_car 180>, /* adx1 */
729 <&tegra_car 186>, /* afc0 */
730 <&tegra_car 187>, /* afc1 */
731 <&tegra_car 188>, /* afc2 */
732 <&tegra_car 189>, /* afc3 */
733 <&tegra_car 190>, /* afc4 */
734 <&tegra_car 191>; /* afc5 */
735 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
736 "i2s3", "i2s4", "dam0", "dam1", "dam2",
737 "spdif", "amx", "amx1", "adx", "adx1",
738 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
739 dmas = <&apbdma 1>, <&apbdma 1>,
740 <&apbdma 2>, <&apbdma 2>,
741 <&apbdma 3>, <&apbdma 3>,
742 <&apbdma 4>, <&apbdma 4>,
743 <&apbdma 6>, <&apbdma 6>,
744 <&apbdma 7>, <&apbdma 7>,
745 <&apbdma 12>, <&apbdma 12>,
746 <&apbdma 13>, <&apbdma 13>,
747 <&apbdma 14>, <&apbdma 14>,
748 <&apbdma 29>, <&apbdma 29>;
749 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
750 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
751 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
752 "rx9", "tx9";
753 ranges;
754 #address-cells = <2>;
755 #size-cells = <2>;
757 tegra_i2s0: i2s@0,70301000 {
758 compatible = "nvidia,tegra124-i2s";
759 reg = <0x0 0x70301000 0x0 0x100>;
760 nvidia,ahub-cif-ids = <4 4>;
761 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
762 resets = <&tegra_car 30>;
763 reset-names = "i2s";
764 status = "disabled";
765 };
767 tegra_i2s1: i2s@0,70301100 {
768 compatible = "nvidia,tegra124-i2s";
769 reg = <0x0 0x70301100 0x0 0x100>;
770 nvidia,ahub-cif-ids = <5 5>;
771 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
772 resets = <&tegra_car 11>;
773 reset-names = "i2s";
774 status = "disabled";
775 };
777 tegra_i2s2: i2s@0,70301200 {
778 compatible = "nvidia,tegra124-i2s";
779 reg = <0x0 0x70301200 0x0 0x100>;
780 nvidia,ahub-cif-ids = <6 6>;
781 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
782 resets = <&tegra_car 18>;
783 reset-names = "i2s";
784 status = "disabled";
785 };
787 tegra_i2s3: i2s@0,70301300 {
788 compatible = "nvidia,tegra124-i2s";
789 reg = <0x0 0x70301300 0x0 0x100>;
790 nvidia,ahub-cif-ids = <7 7>;
791 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
792 resets = <&tegra_car 101>;
793 reset-names = "i2s";
794 status = "disabled";
795 };
797 tegra_i2s4: i2s@0,70301400 {
798 compatible = "nvidia,tegra124-i2s";
799 reg = <0x0 0x70301400 0x0 0x100>;
800 nvidia,ahub-cif-ids = <8 8>;
801 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
802 resets = <&tegra_car 102>;
803 reset-names = "i2s";
804 status = "disabled";
805 };
806 };
808 usb@0,7d000000 {
809 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
810 reg = <0x0 0x7d000000 0x0 0x4000>;
811 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
812 phy_type = "utmi";
813 clocks = <&tegra_car TEGRA124_CLK_USBD>;
814 resets = <&tegra_car 22>;
815 reset-names = "usb";
816 nvidia,phy = <&phy1>;
817 status = "disabled";
818 };
820 phy1: usb-phy@0,7d000000 {
821 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
822 reg = <0x0 0x7d000000 0x0 0x4000>,
823 <0x0 0x7d000000 0x0 0x4000>;
824 phy_type = "utmi";
825 clocks = <&tegra_car TEGRA124_CLK_USBD>,
826 <&tegra_car TEGRA124_CLK_PLL_U>,
827 <&tegra_car TEGRA124_CLK_USBD>;
828 clock-names = "reg", "pll_u", "utmi-pads";
829 resets = <&tegra_car 22>, <&tegra_car 22>;
830 reset-names = "usb", "utmi-pads";
831 nvidia,hssync-start-delay = <0>;
832 nvidia,idle-wait-delay = <17>;
833 nvidia,elastic-limit = <16>;
834 nvidia,term-range-adj = <6>;
835 nvidia,xcvr-setup = <9>;
836 nvidia,xcvr-lsfslew = <0>;
837 nvidia,xcvr-lsrslew = <3>;
838 nvidia,hssquelch-level = <2>;
839 nvidia,hsdiscon-level = <5>;
840 nvidia,xcvr-hsslew = <12>;
841 nvidia,has-utmi-pad-registers;
842 status = "disabled";
843 };
845 usb@0,7d004000 {
846 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
847 reg = <0x0 0x7d004000 0x0 0x4000>;
848 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
849 phy_type = "utmi";
850 clocks = <&tegra_car TEGRA124_CLK_USB2>;
851 resets = <&tegra_car 58>;
852 reset-names = "usb";
853 nvidia,phy = <&phy2>;
854 status = "disabled";
855 };
857 phy2: usb-phy@0,7d004000 {
858 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
859 reg = <0x0 0x7d004000 0x0 0x4000>,
860 <0x0 0x7d000000 0x0 0x4000>;
861 phy_type = "utmi";
862 clocks = <&tegra_car TEGRA124_CLK_USB2>,
863 <&tegra_car TEGRA124_CLK_PLL_U>,
864 <&tegra_car TEGRA124_CLK_USBD>;
865 clock-names = "reg", "pll_u", "utmi-pads";
866 resets = <&tegra_car 58>, <&tegra_car 22>;
867 reset-names = "usb", "utmi-pads";
868 nvidia,hssync-start-delay = <0>;
869 nvidia,idle-wait-delay = <17>;
870 nvidia,elastic-limit = <16>;
871 nvidia,term-range-adj = <6>;
872 nvidia,xcvr-setup = <9>;
873 nvidia,xcvr-lsfslew = <0>;
874 nvidia,xcvr-lsrslew = <3>;
875 nvidia,hssquelch-level = <2>;
876 nvidia,hsdiscon-level = <5>;
877 nvidia,xcvr-hsslew = <12>;
878 status = "disabled";
879 };
881 usb@0,7d008000 {
882 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
883 reg = <0x0 0x7d008000 0x0 0x4000>;
884 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
885 phy_type = "utmi";
886 clocks = <&tegra_car TEGRA124_CLK_USB3>;
887 resets = <&tegra_car 59>;
888 reset-names = "usb";
889 nvidia,phy = <&phy3>;
890 status = "disabled";
891 };
893 phy3: usb-phy@0,7d008000 {
894 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
895 reg = <0x0 0x7d008000 0x0 0x4000>,
896 <0x0 0x7d000000 0x0 0x4000>;
897 phy_type = "utmi";
898 clocks = <&tegra_car TEGRA124_CLK_USB3>,
899 <&tegra_car TEGRA124_CLK_PLL_U>,
900 <&tegra_car TEGRA124_CLK_USBD>;
901 clock-names = "reg", "pll_u", "utmi-pads";
902 resets = <&tegra_car 59>, <&tegra_car 22>;
903 reset-names = "usb", "utmi-pads";
904 nvidia,hssync-start-delay = <0>;
905 nvidia,idle-wait-delay = <17>;
906 nvidia,elastic-limit = <16>;
907 nvidia,term-range-adj = <6>;
908 nvidia,xcvr-setup = <9>;
909 nvidia,xcvr-lsfslew = <0>;
910 nvidia,xcvr-lsrslew = <3>;
911 nvidia,hssquelch-level = <2>;
912 nvidia,hsdiscon-level = <5>;
913 nvidia,xcvr-hsslew = <12>;
914 status = "disabled";
915 };
917 cpus {
918 #address-cells = <1>;
919 #size-cells = <0>;
921 cpu@0 {
922 device_type = "cpu";
923 compatible = "arm,cortex-a15";
924 reg = <0>;
925 };
927 cpu@1 {
928 device_type = "cpu";
929 compatible = "arm,cortex-a15";
930 reg = <1>;
931 };
933 cpu@2 {
934 device_type = "cpu";
935 compatible = "arm,cortex-a15";
936 reg = <2>;
937 };
939 cpu@3 {
940 device_type = "cpu";
941 compatible = "arm,cortex-a15";
942 reg = <3>;
943 };
944 };
946 thermal-zones {
947 cpu {
948 polling-delay-passive = <1000>;
949 polling-delay = <1000>;
951 thermal-sensors =
952 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
953 };
955 mem {
956 polling-delay-passive = <1000>;
957 polling-delay = <1000>;
959 thermal-sensors =
960 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
961 };
963 gpu {
964 polling-delay-passive = <1000>;
965 polling-delay = <1000>;
967 thermal-sensors =
968 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
969 };
971 pllx {
972 polling-delay-passive = <1000>;
973 polling-delay = <1000>;
975 thermal-sensors =
976 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
977 };
978 };
980 timer {
981 compatible = "arm,armv7-timer";
982 interrupts = <GIC_PPI 13
983 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
984 <GIC_PPI 14
985 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 11
987 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 10
989 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
990 interrupt-parent = <&gic>;
991 };
992 };