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perf record: Fix segfault with --no-mmap-pages
[linux/fpc-iii.git] / drivers / iommu / arm-smmu.c
blob181c9ba929cdfa131123639862cdefb2587c8cf6
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 39-bit addressing
28 * - Context fault reporting
29 */
30
31 #define pr_fmt(fmt) "arm-smmu: " fmt
32
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iommu.h>
39 #include <linux/mm.h>
40 #include <linux/module.h>
41 #include <linux/of.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45
46 #include <linux/amba/bus.h>
47
48 #include <asm/pgalloc.h>
49
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS 8
52
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
55
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
58
59 /* SMMU global address space */
60 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
61 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
62
63 /* Page table bits */
64 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
65 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
66 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
67 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
68 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
69 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
70
71 #if PAGE_SIZE == SZ_4K
72 #define ARM_SMMU_PTE_CONT_ENTRIES 16
73 #elif PAGE_SIZE == SZ_64K
74 #define ARM_SMMU_PTE_CONT_ENTRIES 32
75 #else
76 #define ARM_SMMU_PTE_CONT_ENTRIES 1
77 #endif
78
79 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
80 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
81 #define ARM_SMMU_PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(pte_t))
82
83 /* Stage-1 PTE */
84 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
85 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
86 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
87 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
88
89 /* Stage-2 PTE */
90 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
91 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
92 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
93 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
94 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
95 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
96
97 /* Configuration registers */
98 #define ARM_SMMU_GR0_sCR0 0x0
99 #define sCR0_CLIENTPD (1 << 0)
100 #define sCR0_GFRE (1 << 1)
101 #define sCR0_GFIE (1 << 2)
102 #define sCR0_GCFGFRE (1 << 4)
103 #define sCR0_GCFGFIE (1 << 5)
104 #define sCR0_USFCFG (1 << 10)
105 #define sCR0_VMIDPNE (1 << 11)
106 #define sCR0_PTM (1 << 12)
107 #define sCR0_FB (1 << 13)
108 #define sCR0_BSU_SHIFT 14
109 #define sCR0_BSU_MASK 0x3
110
111 /* Identification registers */
112 #define ARM_SMMU_GR0_ID0 0x20
113 #define ARM_SMMU_GR0_ID1 0x24
114 #define ARM_SMMU_GR0_ID2 0x28
115 #define ARM_SMMU_GR0_ID3 0x2c
116 #define ARM_SMMU_GR0_ID4 0x30
117 #define ARM_SMMU_GR0_ID5 0x34
118 #define ARM_SMMU_GR0_ID6 0x38
119 #define ARM_SMMU_GR0_ID7 0x3c
120 #define ARM_SMMU_GR0_sGFSR 0x48
121 #define ARM_SMMU_GR0_sGFSYNR0 0x50
122 #define ARM_SMMU_GR0_sGFSYNR1 0x54
123 #define ARM_SMMU_GR0_sGFSYNR2 0x58
124 #define ARM_SMMU_GR0_PIDR0 0xfe0
125 #define ARM_SMMU_GR0_PIDR1 0xfe4
126 #define ARM_SMMU_GR0_PIDR2 0xfe8
127
128 #define ID0_S1TS (1 << 30)
129 #define ID0_S2TS (1 << 29)
130 #define ID0_NTS (1 << 28)
131 #define ID0_SMS (1 << 27)
132 #define ID0_PTFS_SHIFT 24
133 #define ID0_PTFS_MASK 0x2
134 #define ID0_PTFS_V8_ONLY 0x2
135 #define ID0_CTTW (1 << 14)
136 #define ID0_NUMIRPT_SHIFT 16
137 #define ID0_NUMIRPT_MASK 0xff
138 #define ID0_NUMSMRG_SHIFT 0
139 #define ID0_NUMSMRG_MASK 0xff
140
141 #define ID1_PAGESIZE (1 << 31)
142 #define ID1_NUMPAGENDXB_SHIFT 28
143 #define ID1_NUMPAGENDXB_MASK 7
144 #define ID1_NUMS2CB_SHIFT 16
145 #define ID1_NUMS2CB_MASK 0xff
146 #define ID1_NUMCB_SHIFT 0
147 #define ID1_NUMCB_MASK 0xff
148
149 #define ID2_OAS_SHIFT 4
150 #define ID2_OAS_MASK 0xf
151 #define ID2_IAS_SHIFT 0
152 #define ID2_IAS_MASK 0xf
153 #define ID2_UBS_SHIFT 8
154 #define ID2_UBS_MASK 0xf
155 #define ID2_PTFS_4K (1 << 12)
156 #define ID2_PTFS_16K (1 << 13)
157 #define ID2_PTFS_64K (1 << 14)
158
159 #define PIDR2_ARCH_SHIFT 4
160 #define PIDR2_ARCH_MASK 0xf
161
162 /* Global TLB invalidation */
163 #define ARM_SMMU_GR0_STLBIALL 0x60
164 #define ARM_SMMU_GR0_TLBIVMID 0x64
165 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
166 #define ARM_SMMU_GR0_TLBIALLH 0x6c
167 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
168 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
169 #define sTLBGSTATUS_GSACTIVE (1 << 0)
170 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
171
172 /* Stream mapping registers */
173 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
174 #define SMR_VALID (1 << 31)
175 #define SMR_MASK_SHIFT 16
176 #define SMR_MASK_MASK 0x7fff
177 #define SMR_ID_SHIFT 0
178 #define SMR_ID_MASK 0x7fff
179
180 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
181 #define S2CR_CBNDX_SHIFT 0
182 #define S2CR_CBNDX_MASK 0xff
183 #define S2CR_TYPE_SHIFT 16
184 #define S2CR_TYPE_MASK 0x3
185 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
186 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
187 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
188
189 /* Context bank attribute registers */
190 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
191 #define CBAR_VMID_SHIFT 0
192 #define CBAR_VMID_MASK 0xff
193 #define CBAR_S1_MEMATTR_SHIFT 12
194 #define CBAR_S1_MEMATTR_MASK 0xf
195 #define CBAR_S1_MEMATTR_WB 0xf
196 #define CBAR_TYPE_SHIFT 16
197 #define CBAR_TYPE_MASK 0x3
198 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
199 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
200 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
201 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
202 #define CBAR_IRPTNDX_SHIFT 24
203 #define CBAR_IRPTNDX_MASK 0xff
204
205 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
206 #define CBA2R_RW64_32BIT (0 << 0)
207 #define CBA2R_RW64_64BIT (1 << 0)
208
209 /* Translation context bank */
210 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
211 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
212
213 #define ARM_SMMU_CB_SCTLR 0x0
214 #define ARM_SMMU_CB_RESUME 0x8
215 #define ARM_SMMU_CB_TTBCR2 0x10
216 #define ARM_SMMU_CB_TTBR0_LO 0x20
217 #define ARM_SMMU_CB_TTBR0_HI 0x24
218 #define ARM_SMMU_CB_TTBCR 0x30
219 #define ARM_SMMU_CB_S1_MAIR0 0x38
220 #define ARM_SMMU_CB_FSR 0x58
221 #define ARM_SMMU_CB_FAR_LO 0x60
222 #define ARM_SMMU_CB_FAR_HI 0x64
223 #define ARM_SMMU_CB_FSYNR0 0x68
224 #define ARM_SMMU_CB_S1_TLBIASID 0x610
225
226 #define SCTLR_S1_ASIDPNE (1 << 12)
227 #define SCTLR_CFCFG (1 << 7)
228 #define SCTLR_CFIE (1 << 6)
229 #define SCTLR_CFRE (1 << 5)
230 #define SCTLR_E (1 << 4)
231 #define SCTLR_AFE (1 << 2)
232 #define SCTLR_TRE (1 << 1)
233 #define SCTLR_M (1 << 0)
234 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
235
236 #define RESUME_RETRY (0 << 0)
237 #define RESUME_TERMINATE (1 << 0)
238
239 #define TTBCR_EAE (1 << 31)
240
241 #define TTBCR_PASIZE_SHIFT 16
242 #define TTBCR_PASIZE_MASK 0x7
243
244 #define TTBCR_TG0_4K (0 << 14)
245 #define TTBCR_TG0_64K (1 << 14)
246
247 #define TTBCR_SH0_SHIFT 12
248 #define TTBCR_SH0_MASK 0x3
249 #define TTBCR_SH_NS 0
250 #define TTBCR_SH_OS 2
251 #define TTBCR_SH_IS 3
252
253 #define TTBCR_ORGN0_SHIFT 10
254 #define TTBCR_IRGN0_SHIFT 8
255 #define TTBCR_RGN_MASK 0x3
256 #define TTBCR_RGN_NC 0
257 #define TTBCR_RGN_WBWA 1
258 #define TTBCR_RGN_WT 2
259 #define TTBCR_RGN_WB 3
260
261 #define TTBCR_SL0_SHIFT 6
262 #define TTBCR_SL0_MASK 0x3
263 #define TTBCR_SL0_LVL_2 0
264 #define TTBCR_SL0_LVL_1 1
265
266 #define TTBCR_T1SZ_SHIFT 16
267 #define TTBCR_T0SZ_SHIFT 0
268 #define TTBCR_SZ_MASK 0xf
269
270 #define TTBCR2_SEP_SHIFT 15
271 #define TTBCR2_SEP_MASK 0x7
272
273 #define TTBCR2_PASIZE_SHIFT 0
274 #define TTBCR2_PASIZE_MASK 0x7
275
276 /* Common definitions for PASize and SEP fields */
277 #define TTBCR2_ADDR_32 0
278 #define TTBCR2_ADDR_36 1
279 #define TTBCR2_ADDR_40 2
280 #define TTBCR2_ADDR_42 3
281 #define TTBCR2_ADDR_44 4
282 #define TTBCR2_ADDR_48 5
283
284 #define TTBRn_HI_ASID_SHIFT 16
285
286 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
287 #define MAIR_ATTR_MASK 0xff
288 #define MAIR_ATTR_DEVICE 0x04
289 #define MAIR_ATTR_NC 0x44
290 #define MAIR_ATTR_WBRWA 0xff
291 #define MAIR_ATTR_IDX_NC 0
292 #define MAIR_ATTR_IDX_CACHE 1
293 #define MAIR_ATTR_IDX_DEV 2
294
295 #define FSR_MULTI (1 << 31)
296 #define FSR_SS (1 << 30)
297 #define FSR_UUT (1 << 8)
298 #define FSR_ASF (1 << 7)
299 #define FSR_TLBLKF (1 << 6)
300 #define FSR_TLBMCF (1 << 5)
301 #define FSR_EF (1 << 4)
302 #define FSR_PF (1 << 3)
303 #define FSR_AFF (1 << 2)
304 #define FSR_TF (1 << 1)
305
306 #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \
307 FSR_TLBLKF)
308 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
309 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
310
311 #define FSYNR0_WNR (1 << 4)
312
313 struct arm_smmu_smr {
314 u8 idx;
315 u16 mask;
316 u16 id;
317 };
318
319 struct arm_smmu_master {
320 struct device_node *of_node;
321
322 /*
323 * The following is specific to the master's position in the
324 * SMMU chain.
325 */
326 struct rb_node node;
327 int num_streamids;
328 u16 streamids[MAX_MASTER_STREAMIDS];
329
330 /*
331 * We only need to allocate these on the root SMMU, as we
332 * configure unmatched streams to bypass translation.
333 */
334 struct arm_smmu_smr *smrs;
335 };
336
337 struct arm_smmu_device {
338 struct device *dev;
339 struct device_node *parent_of_node;
340
341 void __iomem *base;
342 unsigned long size;
343 unsigned long pagesize;
344
345 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
346 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
347 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
348 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
349 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
350 u32 features;
351 int version;
352
353 u32 num_context_banks;
354 u32 num_s2_context_banks;
355 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
356 atomic_t irptndx;
357
358 u32 num_mapping_groups;
359 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
360
361 unsigned long input_size;
362 unsigned long s1_output_size;
363 unsigned long s2_output_size;
364
365 u32 num_global_irqs;
366 u32 num_context_irqs;
367 unsigned int *irqs;
368
369 struct list_head list;
370 struct rb_root masters;
371 };
372
373 struct arm_smmu_cfg {
374 struct arm_smmu_device *smmu;
375 u8 cbndx;
376 u8 irptndx;
377 u32 cbar;
378 pgd_t *pgd;
379 };
380 #define INVALID_IRPTNDX 0xff
381
382 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
383 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
384
385 struct arm_smmu_domain {
386 /*
387 * A domain can span across multiple, chained SMMUs and requires
388 * all devices within the domain to follow the same translation
389 * path.
390 */
391 struct arm_smmu_device *leaf_smmu;
392 struct arm_smmu_cfg root_cfg;
393 phys_addr_t output_mask;
394
395 spinlock_t lock;
396 };
397
398 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
399 static LIST_HEAD(arm_smmu_devices);
400
401 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
402 struct device_node *dev_node)
403 {
404 struct rb_node *node = smmu->masters.rb_node;
405
406 while (node) {
407 struct arm_smmu_master *master;
408 master = container_of(node, struct arm_smmu_master, node);
409
410 if (dev_node < master->of_node)
411 node = node->rb_left;
412 else if (dev_node > master->of_node)
413 node = node->rb_right;
414 else
415 return master;
416 }
417
418 return NULL;
419 }
420
421 static int insert_smmu_master(struct arm_smmu_device *smmu,
422 struct arm_smmu_master *master)
423 {
424 struct rb_node **new, *parent;
425
426 new = &smmu->masters.rb_node;
427 parent = NULL;
428 while (*new) {
429 struct arm_smmu_master *this;
430 this = container_of(*new, struct arm_smmu_master, node);
431
432 parent = *new;
433 if (master->of_node < this->of_node)
434 new = &((*new)->rb_left);
435 else if (master->of_node > this->of_node)
436 new = &((*new)->rb_right);
437 else
438 return -EEXIST;
439 }
440
441 rb_link_node(&master->node, parent, new);
442 rb_insert_color(&master->node, &smmu->masters);
443 return 0;
444 }
445
446 static int register_smmu_master(struct arm_smmu_device *smmu,
447 struct device *dev,
448 struct of_phandle_args *masterspec)
449 {
450 int i;
451 struct arm_smmu_master *master;
452
453 master = find_smmu_master(smmu, masterspec->np);
454 if (master) {
455 dev_err(dev,
456 "rejecting multiple registrations for master device %s\n",
457 masterspec->np->name);
458 return -EBUSY;
459 }
460
461 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
462 dev_err(dev,
463 "reached maximum number (%d) of stream IDs for master device %s\n",
464 MAX_MASTER_STREAMIDS, masterspec->np->name);
465 return -ENOSPC;
466 }
467
468 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
469 if (!master)
470 return -ENOMEM;
471
472 master->of_node = masterspec->np;
473 master->num_streamids = masterspec->args_count;
474
475 for (i = 0; i < master->num_streamids; ++i)
476 master->streamids[i] = masterspec->args[i];
477
478 return insert_smmu_master(smmu, master);
479 }
480
481 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
482 {
483 struct arm_smmu_device *parent;
484
485 if (!smmu->parent_of_node)
486 return NULL;
487
488 spin_lock(&arm_smmu_devices_lock);
489 list_for_each_entry(parent, &arm_smmu_devices, list)
490 if (parent->dev->of_node == smmu->parent_of_node)
491 goto out_unlock;
492
493 parent = NULL;
494 dev_warn(smmu->dev,
495 "Failed to find SMMU parent despite parent in DT\n");
496 out_unlock:
497 spin_unlock(&arm_smmu_devices_lock);
498 return parent;
499 }
500
501 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
502 {
503 int idx;
504
505 do {
506 idx = find_next_zero_bit(map, end, start);
507 if (idx == end)
508 return -ENOSPC;
509 } while (test_and_set_bit(idx, map));
510
511 return idx;
512 }
513
514 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
515 {
516 clear_bit(idx, map);
517 }
518
519 /* Wait for any pending TLB invalidations to complete */
520 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
521 {
522 int count = 0;
523 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
524
525 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
526 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
527 & sTLBGSTATUS_GSACTIVE) {
528 cpu_relax();
529 if (++count == TLB_LOOP_TIMEOUT) {
530 dev_err_ratelimited(smmu->dev,
531 "TLB sync timed out -- SMMU may be deadlocked\n");
532 return;
533 }
534 udelay(1);
535 }
536 }
537
538 static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg)
539 {
540 struct arm_smmu_device *smmu = cfg->smmu;
541 void __iomem *base = ARM_SMMU_GR0(smmu);
542 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
543
544 if (stage1) {
545 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
546 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
547 base + ARM_SMMU_CB_S1_TLBIASID);
548 } else {
549 base = ARM_SMMU_GR0(smmu);
550 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
551 base + ARM_SMMU_GR0_TLBIVMID);
552 }
553
554 arm_smmu_tlb_sync(smmu);
555 }
556
557 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
558 {
559 int flags, ret;
560 u32 fsr, far, fsynr, resume;
561 unsigned long iova;
562 struct iommu_domain *domain = dev;
563 struct arm_smmu_domain *smmu_domain = domain->priv;
564 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
565 struct arm_smmu_device *smmu = root_cfg->smmu;
566 void __iomem *cb_base;
567
568 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
569 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
570
571 if (!(fsr & FSR_FAULT))
572 return IRQ_NONE;
573
574 if (fsr & FSR_IGN)
575 dev_err_ratelimited(smmu->dev,
576 "Unexpected context fault (fsr 0x%u)\n",
577 fsr);
578
579 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
580 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
581
582 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
583 iova = far;
584 #ifdef CONFIG_64BIT
585 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
586 iova |= ((unsigned long)far << 32);
587 #endif
588
589 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
590 ret = IRQ_HANDLED;
591 resume = RESUME_RETRY;
592 } else {
593 ret = IRQ_NONE;
594 resume = RESUME_TERMINATE;
595 }
596
597 /* Clear the faulting FSR */
598 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
599
600 /* Retry or terminate any stalled transactions */
601 if (fsr & FSR_SS)
602 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
603
604 return ret;
605 }
606
607 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
608 {
609 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
610 struct arm_smmu_device *smmu = dev;
611 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
612
613 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
614 if (!gfsr)
615 return IRQ_NONE;
616
617 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
618 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
619 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
620
621 dev_err_ratelimited(smmu->dev,
622 "Unexpected global fault, this could be serious\n");
623 dev_err_ratelimited(smmu->dev,
624 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
625 gfsr, gfsynr0, gfsynr1, gfsynr2);
626
627 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
628 return IRQ_HANDLED;
629 }
630
631 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
632 {
633 u32 reg;
634 bool stage1;
635 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
636 struct arm_smmu_device *smmu = root_cfg->smmu;
637 void __iomem *cb_base, *gr0_base, *gr1_base;
638
639 gr0_base = ARM_SMMU_GR0(smmu);
640 gr1_base = ARM_SMMU_GR1(smmu);
641 stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
642 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
643
644 /* CBAR */
645 reg = root_cfg->cbar;
646 if (smmu->version == 1)
647 reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
648
649 /* Use the weakest memory type, so it is overridden by the pte */
650 if (stage1)
651 reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
652 else
653 reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT;
654 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
655
656 if (smmu->version > 1) {
657 /* CBA2R */
658 #ifdef CONFIG_64BIT
659 reg = CBA2R_RW64_64BIT;
660 #else
661 reg = CBA2R_RW64_32BIT;
662 #endif
663 writel_relaxed(reg,
664 gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
665
666 /* TTBCR2 */
667 switch (smmu->input_size) {
668 case 32:
669 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
670 break;
671 case 36:
672 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
673 break;
674 case 39:
675 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
676 break;
677 case 42:
678 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
679 break;
680 case 44:
681 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
682 break;
683 case 48:
684 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
685 break;
686 }
687
688 switch (smmu->s1_output_size) {
689 case 32:
690 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
691 break;
692 case 36:
693 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
694 break;
695 case 39:
696 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
697 break;
698 case 42:
699 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
700 break;
701 case 44:
702 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
703 break;
704 case 48:
705 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
706 break;
707 }
708
709 if (stage1)
710 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
711 }
712
713 /* TTBR0 */
714 reg = __pa(root_cfg->pgd);
715 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
716 reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
717 if (stage1)
718 reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT;
719 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
720
721 /*
722 * TTBCR
723 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
724 */
725 if (smmu->version > 1) {
726 if (PAGE_SIZE == SZ_4K)
727 reg = TTBCR_TG0_4K;
728 else
729 reg = TTBCR_TG0_64K;
730
731 if (!stage1) {
732 switch (smmu->s2_output_size) {
733 case 32:
734 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
735 break;
736 case 36:
737 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
738 break;
739 case 40:
740 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
741 break;
742 case 42:
743 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
744 break;
745 case 44:
746 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
747 break;
748 case 48:
749 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
750 break;
751 }
752 } else {
753 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
754 }
755 } else {
756 reg = 0;
757 }
758
759 reg |= TTBCR_EAE |
760 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
761 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
762 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
763 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
764 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
765
766 /* MAIR0 (stage-1 only) */
767 if (stage1) {
768 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
769 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
770 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
771 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
772 }
773
774 /* SCTLR */
775 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
776 if (stage1)
777 reg |= SCTLR_S1_ASIDPNE;
778 #ifdef __BIG_ENDIAN
779 reg |= SCTLR_E;
780 #endif
781 writel(reg, cb_base + ARM_SMMU_CB_SCTLR);
782 }
783
784 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
785 struct device *dev)
786 {
787 int irq, ret, start;
788 struct arm_smmu_domain *smmu_domain = domain->priv;
789 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
790 struct arm_smmu_device *smmu, *parent;
791
792 /*
793 * Walk the SMMU chain to find the root device for this chain.
794 * We assume that no masters have translations which terminate
795 * early, and therefore check that the root SMMU does indeed have
796 * a StreamID for the master in question.
797 */
798 parent = dev->archdata.iommu;
799 smmu_domain->output_mask = -1;
800 do {
801 smmu = parent;
802 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
803 } while ((parent = find_parent_smmu(smmu)));
804
805 if (!find_smmu_master(smmu, dev->of_node)) {
806 dev_err(dev, "unable to find root SMMU for device\n");
807 return -ENODEV;
808 }
809
810 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
811 /*
812 * We will likely want to change this if/when KVM gets
813 * involved.
814 */
815 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
816 start = smmu->num_s2_context_banks;
817 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
818 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
819 start = 0;
820 } else {
821 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
822 start = smmu->num_s2_context_banks;
823 }
824
825 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
826 smmu->num_context_banks);
827 if (IS_ERR_VALUE(ret))
828 return ret;
829
830 root_cfg->cbndx = ret;
831 if (smmu->version == 1) {
832 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
833 root_cfg->irptndx %= smmu->num_context_irqs;
834 } else {
835 root_cfg->irptndx = root_cfg->cbndx;
836 }
837
838 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
839 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
840 "arm-smmu-context-fault", domain);
841 if (IS_ERR_VALUE(ret)) {
842 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
843 root_cfg->irptndx, irq);
844 root_cfg->irptndx = INVALID_IRPTNDX;
845 goto out_free_context;
846 }
847
848 root_cfg->smmu = smmu;
849 arm_smmu_init_context_bank(smmu_domain);
850 return ret;
851
852 out_free_context:
853 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
854 return ret;
855 }
856
857 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
858 {
859 struct arm_smmu_domain *smmu_domain = domain->priv;
860 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
861 struct arm_smmu_device *smmu = root_cfg->smmu;
862 void __iomem *cb_base;
863 int irq;
864
865 if (!smmu)
866 return;
867
868 /* Disable the context bank and nuke the TLB before freeing it. */
869 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
870 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
871 arm_smmu_tlb_inv_context(root_cfg);
872
873 if (root_cfg->irptndx != INVALID_IRPTNDX) {
874 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
875 free_irq(irq, domain);
876 }
877
878 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
879 }
880
881 static int arm_smmu_domain_init(struct iommu_domain *domain)
882 {
883 struct arm_smmu_domain *smmu_domain;
884 pgd_t *pgd;
885
886 /*
887 * Allocate the domain and initialise some of its data structures.
888 * We can't really do anything meaningful until we've added a
889 * master.
890 */
891 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
892 if (!smmu_domain)
893 return -ENOMEM;
894
895 pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
896 if (!pgd)
897 goto out_free_domain;
898 smmu_domain->root_cfg.pgd = pgd;
899
900 spin_lock_init(&smmu_domain->lock);
901 domain->priv = smmu_domain;
902 return 0;
903
904 out_free_domain:
905 kfree(smmu_domain);
906 return -ENOMEM;
907 }
908
909 static void arm_smmu_free_ptes(pmd_t *pmd)
910 {
911 pgtable_t table = pmd_pgtable(*pmd);
912 pgtable_page_dtor(table);
913 __free_page(table);
914 }
915
916 static void arm_smmu_free_pmds(pud_t *pud)
917 {
918 int i;
919 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
920
921 pmd = pmd_base;
922 for (i = 0; i < PTRS_PER_PMD; ++i) {
923 if (pmd_none(*pmd))
924 continue;
925
926 arm_smmu_free_ptes(pmd);
927 pmd++;
928 }
929
930 pmd_free(NULL, pmd_base);
931 }
932
933 static void arm_smmu_free_puds(pgd_t *pgd)
934 {
935 int i;
936 pud_t *pud, *pud_base = pud_offset(pgd, 0);
937
938 pud = pud_base;
939 for (i = 0; i < PTRS_PER_PUD; ++i) {
940 if (pud_none(*pud))
941 continue;
942
943 arm_smmu_free_pmds(pud);
944 pud++;
945 }
946
947 pud_free(NULL, pud_base);
948 }
949
950 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
951 {
952 int i;
953 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
954 pgd_t *pgd, *pgd_base = root_cfg->pgd;
955
956 /*
957 * Recursively free the page tables for this domain. We don't
958 * care about speculative TLB filling, because the TLB will be
959 * nuked next time this context bank is re-allocated and no devices
960 * currently map to these tables.
961 */
962 pgd = pgd_base;
963 for (i = 0; i < PTRS_PER_PGD; ++i) {
964 if (pgd_none(*pgd))
965 continue;
966 arm_smmu_free_puds(pgd);
967 pgd++;
968 }
969
970 kfree(pgd_base);
971 }
972
973 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
974 {
975 struct arm_smmu_domain *smmu_domain = domain->priv;
976
977 /*
978 * Free the domain resources. We assume that all devices have
979 * already been detached.
980 */
981 arm_smmu_destroy_domain_context(domain);
982 arm_smmu_free_pgtables(smmu_domain);
983 kfree(smmu_domain);
984 }
985
986 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
987 struct arm_smmu_master *master)
988 {
989 int i;
990 struct arm_smmu_smr *smrs;
991 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
992
993 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
994 return 0;
995
996 if (master->smrs)
997 return -EEXIST;
998
999 smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
1000 if (!smrs) {
1001 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
1002 master->num_streamids, master->of_node->name);
1003 return -ENOMEM;
1004 }
1005
1006 /* Allocate the SMRs on the root SMMU */
1007 for (i = 0; i < master->num_streamids; ++i) {
1008 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1009 smmu->num_mapping_groups);
1010 if (IS_ERR_VALUE(idx)) {
1011 dev_err(smmu->dev, "failed to allocate free SMR\n");
1012 goto err_free_smrs;
1013 }
1014
1015 smrs[i] = (struct arm_smmu_smr) {
1016 .idx = idx,
1017 .mask = 0, /* We don't currently share SMRs */
1018 .id = master->streamids[i],
1019 };
1020 }
1021
1022 /* It worked! Now, poke the actual hardware */
1023 for (i = 0; i < master->num_streamids; ++i) {
1024 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1025 smrs[i].mask << SMR_MASK_SHIFT;
1026 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1027 }
1028
1029 master->smrs = smrs;
1030 return 0;
1031
1032 err_free_smrs:
1033 while (--i >= 0)
1034 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1035 kfree(smrs);
1036 return -ENOSPC;
1037 }
1038
1039 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1040 struct arm_smmu_master *master)
1041 {
1042 int i;
1043 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1044 struct arm_smmu_smr *smrs = master->smrs;
1045
1046 /* Invalidate the SMRs before freeing back to the allocator */
1047 for (i = 0; i < master->num_streamids; ++i) {
1048 u8 idx = smrs[i].idx;
1049 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1050 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1051 }
1052
1053 master->smrs = NULL;
1054 kfree(smrs);
1055 }
1056
1057 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1058 struct arm_smmu_master *master)
1059 {
1060 int i;
1061 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1062
1063 for (i = 0; i < master->num_streamids; ++i) {
1064 u16 sid = master->streamids[i];
1065 writel_relaxed(S2CR_TYPE_BYPASS,
1066 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1067 }
1068 }
1069
1070 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1071 struct arm_smmu_master *master)
1072 {
1073 int i, ret;
1074 struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1075 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1076
1077 ret = arm_smmu_master_configure_smrs(smmu, master);
1078 if (ret)
1079 return ret;
1080
1081 /* Bypass the leaves */
1082 smmu = smmu_domain->leaf_smmu;
1083 while ((parent = find_parent_smmu(smmu))) {
1084 /*
1085 * We won't have a StreamID match for anything but the root
1086 * smmu, so we only need to worry about StreamID indexing,
1087 * where we must install bypass entries in the S2CRs.
1088 */
1089 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1090 continue;
1091
1092 arm_smmu_bypass_stream_mapping(smmu, master);
1093 smmu = parent;
1094 }
1095
1096 /* Now we're at the root, time to point at our context bank */
1097 for (i = 0; i < master->num_streamids; ++i) {
1098 u32 idx, s2cr;
1099 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1100 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1101 (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1102 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1103 }
1104
1105 return 0;
1106 }
1107
1108 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1109 struct arm_smmu_master *master)
1110 {
1111 struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1112
1113 /*
1114 * We *must* clear the S2CR first, because freeing the SMR means
1115 * that it can be re-allocated immediately.
1116 */
1117 arm_smmu_bypass_stream_mapping(smmu, master);
1118 arm_smmu_master_free_smrs(smmu, master);
1119 }
1120
1121 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1122 {
1123 int ret = -EINVAL;
1124 struct arm_smmu_domain *smmu_domain = domain->priv;
1125 struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1126 struct arm_smmu_master *master;
1127
1128 if (!device_smmu) {
1129 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1130 return -ENXIO;
1131 }
1132
1133 /*
1134 * Sanity check the domain. We don't currently support domains
1135 * that cross between different SMMU chains.
1136 */
1137 spin_lock(&smmu_domain->lock);
1138 if (!smmu_domain->leaf_smmu) {
1139 /* Now that we have a master, we can finalise the domain */
1140 ret = arm_smmu_init_domain_context(domain, dev);
1141 if (IS_ERR_VALUE(ret))
1142 goto err_unlock;
1143
1144 smmu_domain->leaf_smmu = device_smmu;
1145 } else if (smmu_domain->leaf_smmu != device_smmu) {
1146 dev_err(dev,
1147 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1148 dev_name(smmu_domain->leaf_smmu->dev),
1149 dev_name(device_smmu->dev));
1150 goto err_unlock;
1151 }
1152 spin_unlock(&smmu_domain->lock);
1153
1154 /* Looks ok, so add the device to the domain */
1155 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1156 if (!master)
1157 return -ENODEV;
1158
1159 return arm_smmu_domain_add_master(smmu_domain, master);
1160
1161 err_unlock:
1162 spin_unlock(&smmu_domain->lock);
1163 return ret;
1164 }
1165
1166 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1167 {
1168 struct arm_smmu_domain *smmu_domain = domain->priv;
1169 struct arm_smmu_master *master;
1170
1171 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1172 if (master)
1173 arm_smmu_domain_remove_master(smmu_domain, master);
1174 }
1175
1176 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
1177 size_t size)
1178 {
1179 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
1180
1181 /*
1182 * If the SMMU can't walk tables in the CPU caches, treat them
1183 * like non-coherent DMA since we need to flush the new entries
1184 * all the way out to memory. There's no possibility of recursion
1185 * here as the SMMU table walker will not be wired through another
1186 * SMMU.
1187 */
1188 if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK))
1189 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
1190 DMA_TO_DEVICE);
1191 }
1192
1193 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1194 unsigned long end)
1195 {
1196 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1197 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1198 }
1199
1200 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1201 unsigned long addr, unsigned long end,
1202 unsigned long pfn, int flags, int stage)
1203 {
1204 pte_t *pte, *start;
1205 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF;
1206
1207 if (pmd_none(*pmd)) {
1208 /* Allocate a new set of tables */
1209 pgtable_t table = alloc_page(PGALLOC_GFP);
1210 if (!table)
1211 return -ENOMEM;
1212
1213 arm_smmu_flush_pgtable(smmu, page_address(table),
1214 ARM_SMMU_PTE_HWTABLE_SIZE);
1215 pgtable_page_ctor(table);
1216 pmd_populate(NULL, pmd, table);
1217 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1218 }
1219
1220 if (stage == 1) {
1221 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1222 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
1223 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1224
1225 if (flags & IOMMU_CACHE)
1226 pteval |= (MAIR_ATTR_IDX_CACHE <<
1227 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1228 } else {
1229 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1230 if (flags & IOMMU_READ)
1231 pteval |= ARM_SMMU_PTE_HAP_READ;
1232 if (flags & IOMMU_WRITE)
1233 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1234 if (flags & IOMMU_CACHE)
1235 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1236 else
1237 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1238 }
1239
1240 /* If no access, create a faulting entry to avoid TLB fills */
1241 if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1242 pteval &= ~ARM_SMMU_PTE_PAGE;
1243
1244 pteval |= ARM_SMMU_PTE_SH_IS;
1245 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1246 pte = start;
1247
1248 /*
1249 * Install the page table entries. This is fairly complicated
1250 * since we attempt to make use of the contiguous hint in the
1251 * ptes where possible. The contiguous hint indicates a series
1252 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1253 * contiguous region with the following constraints:
1254 *
1255 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1256 * - Each pte in the region has the contiguous hint bit set
1257 *
1258 * This complicates unmapping (also handled by this code, when
1259 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1260 * possible, yet highly unlikely, that a client may unmap only
1261 * part of a contiguous range. This requires clearing of the
1262 * contiguous hint bits in the range before installing the new
1263 * faulting entries.
1264 *
1265 * Note that re-mapping an address range without first unmapping
1266 * it is not supported, so TLB invalidation is not required here
1267 * and is instead performed at unmap and domain-init time.
1268 */
1269 do {
1270 int i = 1;
1271 pteval &= ~ARM_SMMU_PTE_CONT;
1272
1273 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1274 i = ARM_SMMU_PTE_CONT_ENTRIES;
1275 pteval |= ARM_SMMU_PTE_CONT;
1276 } else if (pte_val(*pte) &
1277 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1278 int j;
1279 pte_t *cont_start;
1280 unsigned long idx = pte_index(addr);
1281
1282 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1283 cont_start = pmd_page_vaddr(*pmd) + idx;
1284 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1285 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1286
1287 arm_smmu_flush_pgtable(smmu, cont_start,
1288 sizeof(*pte) *
1289 ARM_SMMU_PTE_CONT_ENTRIES);
1290 }
1291
1292 do {
1293 *pte = pfn_pte(pfn, __pgprot(pteval));
1294 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1295 } while (addr != end);
1296
1297 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1298 return 0;
1299 }
1300
1301 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1302 unsigned long addr, unsigned long end,
1303 phys_addr_t phys, int flags, int stage)
1304 {
1305 int ret;
1306 pmd_t *pmd;
1307 unsigned long next, pfn = __phys_to_pfn(phys);
1308
1309 #ifndef __PAGETABLE_PMD_FOLDED
1310 if (pud_none(*pud)) {
1311 pmd = pmd_alloc_one(NULL, addr);
1312 if (!pmd)
1313 return -ENOMEM;
1314 } else
1315 #endif
1316 pmd = pmd_offset(pud, addr);
1317
1318 do {
1319 next = pmd_addr_end(addr, end);
1320 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1321 flags, stage);
1322 pud_populate(NULL, pud, pmd);
1323 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1324 phys += next - addr;
1325 } while (pmd++, addr = next, addr < end);
1326
1327 return ret;
1328 }
1329
1330 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1331 unsigned long addr, unsigned long end,
1332 phys_addr_t phys, int flags, int stage)
1333 {
1334 int ret = 0;
1335 pud_t *pud;
1336 unsigned long next;
1337
1338 #ifndef __PAGETABLE_PUD_FOLDED
1339 if (pgd_none(*pgd)) {
1340 pud = pud_alloc_one(NULL, addr);
1341 if (!pud)
1342 return -ENOMEM;
1343 } else
1344 #endif
1345 pud = pud_offset(pgd, addr);
1346
1347 do {
1348 next = pud_addr_end(addr, end);
1349 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1350 flags, stage);
1351 pgd_populate(NULL, pud, pgd);
1352 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1353 phys += next - addr;
1354 } while (pud++, addr = next, addr < end);
1355
1356 return ret;
1357 }
1358
1359 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1360 unsigned long iova, phys_addr_t paddr,
1361 size_t size, int flags)
1362 {
1363 int ret, stage;
1364 unsigned long end;
1365 phys_addr_t input_mask, output_mask;
1366 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1367 pgd_t *pgd = root_cfg->pgd;
1368 struct arm_smmu_device *smmu = root_cfg->smmu;
1369
1370 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1371 stage = 2;
1372 output_mask = (1ULL << smmu->s2_output_size) - 1;
1373 } else {
1374 stage = 1;
1375 output_mask = (1ULL << smmu->s1_output_size) - 1;
1376 }
1377
1378 if (!pgd)
1379 return -EINVAL;
1380
1381 if (size & ~PAGE_MASK)
1382 return -EINVAL;
1383
1384 input_mask = (1ULL << smmu->input_size) - 1;
1385 if ((phys_addr_t)iova & ~input_mask)
1386 return -ERANGE;
1387
1388 if (paddr & ~output_mask)
1389 return -ERANGE;
1390
1391 spin_lock(&smmu_domain->lock);
1392 pgd += pgd_index(iova);
1393 end = iova + size;
1394 do {
1395 unsigned long next = pgd_addr_end(iova, end);
1396
1397 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1398 flags, stage);
1399 if (ret)
1400 goto out_unlock;
1401
1402 paddr += next - iova;
1403 iova = next;
1404 } while (pgd++, iova != end);
1405
1406 out_unlock:
1407 spin_unlock(&smmu_domain->lock);
1408
1409 /* Ensure new page tables are visible to the hardware walker */
1410 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1411 dsb();
1412
1413 return ret;
1414 }
1415
1416 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1417 phys_addr_t paddr, size_t size, int flags)
1418 {
1419 struct arm_smmu_domain *smmu_domain = domain->priv;
1420 struct arm_smmu_device *smmu = smmu_domain->leaf_smmu;
1421
1422 if (!smmu_domain || !smmu)
1423 return -ENODEV;
1424
1425 /* Check for silent address truncation up the SMMU chain. */
1426 if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1427 return -ERANGE;
1428
1429 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
1430 }
1431
1432 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1433 size_t size)
1434 {
1435 int ret;
1436 struct arm_smmu_domain *smmu_domain = domain->priv;
1437
1438 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1439 arm_smmu_tlb_inv_context(&smmu_domain->root_cfg);
1440 return ret ? ret : size;
1441 }
1442
1443 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1444 dma_addr_t iova)
1445 {
1446 pgd_t *pgd;
1447 pud_t *pud;
1448 pmd_t *pmd;
1449 pte_t *pte;
1450 struct arm_smmu_domain *smmu_domain = domain->priv;
1451 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1452 struct arm_smmu_device *smmu = root_cfg->smmu;
1453
1454 spin_lock(&smmu_domain->lock);
1455 pgd = root_cfg->pgd;
1456 if (!pgd)
1457 goto err_unlock;
1458
1459 pgd += pgd_index(iova);
1460 if (pgd_none_or_clear_bad(pgd))
1461 goto err_unlock;
1462
1463 pud = pud_offset(pgd, iova);
1464 if (pud_none_or_clear_bad(pud))
1465 goto err_unlock;
1466
1467 pmd = pmd_offset(pud, iova);
1468 if (pmd_none_or_clear_bad(pmd))
1469 goto err_unlock;
1470
1471 pte = pmd_page_vaddr(*pmd) + pte_index(iova);
1472 if (pte_none(pte))
1473 goto err_unlock;
1474
1475 spin_unlock(&smmu_domain->lock);
1476 return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK);
1477
1478 err_unlock:
1479 spin_unlock(&smmu_domain->lock);
1480 dev_warn(smmu->dev,
1481 "invalid (corrupt?) page tables detected for iova 0x%llx\n",
1482 (unsigned long long)iova);
1483 return -EINVAL;
1484 }
1485
1486 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1487 unsigned long cap)
1488 {
1489 unsigned long caps = 0;
1490 struct arm_smmu_domain *smmu_domain = domain->priv;
1491
1492 if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1493 caps |= IOMMU_CAP_CACHE_COHERENCY;
1494
1495 return !!(cap & caps);
1496 }
1497
1498 static int arm_smmu_add_device(struct device *dev)
1499 {
1500 struct arm_smmu_device *child, *parent, *smmu;
1501 struct arm_smmu_master *master = NULL;
1502
1503 spin_lock(&arm_smmu_devices_lock);
1504 list_for_each_entry(parent, &arm_smmu_devices, list) {
1505 smmu = parent;
1506
1507 /* Try to find a child of the current SMMU. */
1508 list_for_each_entry(child, &arm_smmu_devices, list) {
1509 if (child->parent_of_node == parent->dev->of_node) {
1510 /* Does the child sit above our master? */
1511 master = find_smmu_master(child, dev->of_node);
1512 if (master) {
1513 smmu = NULL;
1514 break;
1515 }
1516 }
1517 }
1518
1519 /* We found some children, so keep searching. */
1520 if (!smmu) {
1521 master = NULL;
1522 continue;
1523 }
1524
1525 master = find_smmu_master(smmu, dev->of_node);
1526 if (master)
1527 break;
1528 }
1529 spin_unlock(&arm_smmu_devices_lock);
1530
1531 if (!master)
1532 return -ENODEV;
1533
1534 dev->archdata.iommu = smmu;
1535 return 0;
1536 }
1537
1538 static void arm_smmu_remove_device(struct device *dev)
1539 {
1540 dev->archdata.iommu = NULL;
1541 }
1542
1543 static struct iommu_ops arm_smmu_ops = {
1544 .domain_init = arm_smmu_domain_init,
1545 .domain_destroy = arm_smmu_domain_destroy,
1546 .attach_dev = arm_smmu_attach_dev,
1547 .detach_dev = arm_smmu_detach_dev,
1548 .map = arm_smmu_map,
1549 .unmap = arm_smmu_unmap,
1550 .iova_to_phys = arm_smmu_iova_to_phys,
1551 .domain_has_cap = arm_smmu_domain_has_cap,
1552 .add_device = arm_smmu_add_device,
1553 .remove_device = arm_smmu_remove_device,
1554 .pgsize_bitmap = (SECTION_SIZE |
1555 ARM_SMMU_PTE_CONT_SIZE |
1556 PAGE_SIZE),
1557 };
1558
1559 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1560 {
1561 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1562 void __iomem *sctlr_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB_SCTLR;
1563 int i = 0;
1564 u32 scr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
1565
1566 /* Mark all SMRn as invalid and all S2CRn as bypass */
1567 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1568 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1569 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1570 }
1571
1572 /* Make sure all context banks are disabled */
1573 for (i = 0; i < smmu->num_context_banks; ++i)
1574 writel_relaxed(0, sctlr_base + ARM_SMMU_CB(smmu, i));
1575
1576 /* Invalidate the TLB, just in case */
1577 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1578 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1579 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1580
1581 /* Enable fault reporting */
1582 scr0 |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1583
1584 /* Disable TLB broadcasting. */
1585 scr0 |= (sCR0_VMIDPNE | sCR0_PTM);
1586
1587 /* Enable client access, but bypass when no mapping is found */
1588 scr0 &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1589
1590 /* Disable forced broadcasting */
1591 scr0 &= ~sCR0_FB;
1592
1593 /* Don't upgrade barriers */
1594 scr0 &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1595
1596 /* Push the button */
1597 arm_smmu_tlb_sync(smmu);
1598 writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
1599 }
1600
1601 static int arm_smmu_id_size_to_bits(int size)
1602 {
1603 switch (size) {
1604 case 0:
1605 return 32;
1606 case 1:
1607 return 36;
1608 case 2:
1609 return 40;
1610 case 3:
1611 return 42;
1612 case 4:
1613 return 44;
1614 case 5:
1615 default:
1616 return 48;
1617 }
1618 }
1619
1620 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1621 {
1622 unsigned long size;
1623 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1624 u32 id;
1625
1626 dev_notice(smmu->dev, "probing hardware configuration...\n");
1627
1628 /* Primecell ID */
1629 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1630 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1631 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1632
1633 /* ID0 */
1634 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1635 #ifndef CONFIG_64BIT
1636 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1637 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1638 return -ENODEV;
1639 }
1640 #endif
1641 if (id & ID0_S1TS) {
1642 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1643 dev_notice(smmu->dev, "\tstage 1 translation\n");
1644 }
1645
1646 if (id & ID0_S2TS) {
1647 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1648 dev_notice(smmu->dev, "\tstage 2 translation\n");
1649 }
1650
1651 if (id & ID0_NTS) {
1652 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1653 dev_notice(smmu->dev, "\tnested translation\n");
1654 }
1655
1656 if (!(smmu->features &
1657 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1658 ARM_SMMU_FEAT_TRANS_NESTED))) {
1659 dev_err(smmu->dev, "\tno translation support!\n");
1660 return -ENODEV;
1661 }
1662
1663 if (id & ID0_CTTW) {
1664 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1665 dev_notice(smmu->dev, "\tcoherent table walk\n");
1666 }
1667
1668 if (id & ID0_SMS) {
1669 u32 smr, sid, mask;
1670
1671 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1672 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1673 ID0_NUMSMRG_MASK;
1674 if (smmu->num_mapping_groups == 0) {
1675 dev_err(smmu->dev,
1676 "stream-matching supported, but no SMRs present!\n");
1677 return -ENODEV;
1678 }
1679
1680 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1681 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1682 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1683 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1684
1685 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1686 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1687 if ((mask & sid) != sid) {
1688 dev_err(smmu->dev,
1689 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1690 mask, sid);
1691 return -ENODEV;
1692 }
1693
1694 dev_notice(smmu->dev,
1695 "\tstream matching with %u register groups, mask 0x%x",
1696 smmu->num_mapping_groups, mask);
1697 }
1698
1699 /* ID1 */
1700 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1701 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1702
1703 /* Check that we ioremapped enough */
1704 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1705 size *= (smmu->pagesize << 1);
1706 if (smmu->size < size)
1707 dev_warn(smmu->dev,
1708 "device is 0x%lx bytes but only mapped 0x%lx!\n",
1709 size, smmu->size);
1710
1711 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1712 ID1_NUMS2CB_MASK;
1713 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1714 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1715 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1716 return -ENODEV;
1717 }
1718 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1719 smmu->num_context_banks, smmu->num_s2_context_banks);
1720
1721 /* ID2 */
1722 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1723 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1724
1725 /*
1726 * Stage-1 output limited by stage-2 input size due to pgd
1727 * allocation (PTRS_PER_PGD).
1728 */
1729 #ifdef CONFIG_64BIT
1730 /* Current maximum output size of 39 bits */
1731 smmu->s1_output_size = min(39UL, size);
1732 #else
1733 smmu->s1_output_size = min(32UL, size);
1734 #endif
1735
1736 /* The stage-2 output mask is also applied for bypass */
1737 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1738 smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1739
1740 if (smmu->version == 1) {
1741 smmu->input_size = 32;
1742 } else {
1743 #ifdef CONFIG_64BIT
1744 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1745 size = min(39, arm_smmu_id_size_to_bits(size));
1746 #else
1747 size = 32;
1748 #endif
1749 smmu->input_size = size;
1750
1751 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1752 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1753 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1754 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1755 PAGE_SIZE);
1756 return -ENODEV;
1757 }
1758 }
1759
1760 dev_notice(smmu->dev,
1761 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1762 smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1763 return 0;
1764 }
1765
1766 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1767 {
1768 struct resource *res;
1769 struct arm_smmu_device *smmu;
1770 struct device_node *dev_node;
1771 struct device *dev = &pdev->dev;
1772 struct rb_node *node;
1773 struct of_phandle_args masterspec;
1774 int num_irqs, i, err;
1775
1776 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1777 if (!smmu) {
1778 dev_err(dev, "failed to allocate arm_smmu_device\n");
1779 return -ENOMEM;
1780 }
1781 smmu->dev = dev;
1782
1783 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1784 if (!res) {
1785 dev_err(dev, "missing base address/size\n");
1786 return -ENODEV;
1787 }
1788
1789 smmu->size = resource_size(res);
1790 smmu->base = devm_request_and_ioremap(dev, res);
1791 if (!smmu->base)
1792 return -EADDRNOTAVAIL;
1793
1794 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1795 &smmu->num_global_irqs)) {
1796 dev_err(dev, "missing #global-interrupts property\n");
1797 return -ENODEV;
1798 }
1799
1800 num_irqs = 0;
1801 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1802 num_irqs++;
1803 if (num_irqs > smmu->num_global_irqs)
1804 smmu->num_context_irqs++;
1805 }
1806
1807 if (num_irqs < smmu->num_global_irqs) {
1808 dev_warn(dev, "found %d interrupts but expected at least %d\n",
1809 num_irqs, smmu->num_global_irqs);
1810 smmu->num_global_irqs = num_irqs;
1811 }
1812 smmu->num_context_irqs = num_irqs - smmu->num_global_irqs;
1813
1814 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1815 GFP_KERNEL);
1816 if (!smmu->irqs) {
1817 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1818 return -ENOMEM;
1819 }
1820
1821 for (i = 0; i < num_irqs; ++i) {
1822 int irq = platform_get_irq(pdev, i);
1823 if (irq < 0) {
1824 dev_err(dev, "failed to get irq index %d\n", i);
1825 return -ENODEV;
1826 }
1827 smmu->irqs[i] = irq;
1828 }
1829
1830 i = 0;
1831 smmu->masters = RB_ROOT;
1832 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1833 "#stream-id-cells", i,
1834 &masterspec)) {
1835 err = register_smmu_master(smmu, dev, &masterspec);
1836 if (err) {
1837 dev_err(dev, "failed to add master %s\n",
1838 masterspec.np->name);
1839 goto out_put_masters;
1840 }
1841
1842 i++;
1843 }
1844 dev_notice(dev, "registered %d master devices\n", i);
1845
1846 if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1847 smmu->parent_of_node = dev_node;
1848
1849 err = arm_smmu_device_cfg_probe(smmu);
1850 if (err)
1851 goto out_put_parent;
1852
1853 if (smmu->version > 1 &&
1854 smmu->num_context_banks != smmu->num_context_irqs) {
1855 dev_err(dev,
1856 "found only %d context interrupt(s) but %d required\n",
1857 smmu->num_context_irqs, smmu->num_context_banks);
1858 goto out_put_parent;
1859 }
1860
1861 for (i = 0; i < smmu->num_global_irqs; ++i) {
1862 err = request_irq(smmu->irqs[i],
1863 arm_smmu_global_fault,
1864 IRQF_SHARED,
1865 "arm-smmu global fault",
1866 smmu);
1867 if (err) {
1868 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1869 i, smmu->irqs[i]);
1870 goto out_free_irqs;
1871 }
1872 }
1873
1874 INIT_LIST_HEAD(&smmu->list);
1875 spin_lock(&arm_smmu_devices_lock);
1876 list_add(&smmu->list, &arm_smmu_devices);
1877 spin_unlock(&arm_smmu_devices_lock);
1878
1879 arm_smmu_device_reset(smmu);
1880 return 0;
1881
1882 out_free_irqs:
1883 while (i--)
1884 free_irq(smmu->irqs[i], smmu);
1885
1886 out_put_parent:
1887 if (smmu->parent_of_node)
1888 of_node_put(smmu->parent_of_node);
1889
1890 out_put_masters:
1891 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1892 struct arm_smmu_master *master;
1893 master = container_of(node, struct arm_smmu_master, node);
1894 of_node_put(master->of_node);
1895 }
1896
1897 return err;
1898 }
1899
1900 static int arm_smmu_device_remove(struct platform_device *pdev)
1901 {
1902 int i;
1903 struct device *dev = &pdev->dev;
1904 struct arm_smmu_device *curr, *smmu = NULL;
1905 struct rb_node *node;
1906
1907 spin_lock(&arm_smmu_devices_lock);
1908 list_for_each_entry(curr, &arm_smmu_devices, list) {
1909 if (curr->dev == dev) {
1910 smmu = curr;
1911 list_del(&smmu->list);
1912 break;
1913 }
1914 }
1915 spin_unlock(&arm_smmu_devices_lock);
1916
1917 if (!smmu)
1918 return -ENODEV;
1919
1920 if (smmu->parent_of_node)
1921 of_node_put(smmu->parent_of_node);
1922
1923 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1924 struct arm_smmu_master *master;
1925 master = container_of(node, struct arm_smmu_master, node);
1926 of_node_put(master->of_node);
1927 }
1928
1929 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1930 dev_err(dev, "removing device with active domains!\n");
1931
1932 for (i = 0; i < smmu->num_global_irqs; ++i)
1933 free_irq(smmu->irqs[i], smmu);
1934
1935 /* Turn the thing off */
1936 writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
1937 return 0;
1938 }
1939
1940 #ifdef CONFIG_OF
1941 static struct of_device_id arm_smmu_of_match[] = {
1942 { .compatible = "arm,smmu-v1", },
1943 { .compatible = "arm,smmu-v2", },
1944 { .compatible = "arm,mmu-400", },
1945 { .compatible = "arm,mmu-500", },
1946 { },
1947 };
1948 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1949 #endif
1950
1951 static struct platform_driver arm_smmu_driver = {
1952 .driver = {
1953 .owner = THIS_MODULE,
1954 .name = "arm-smmu",
1955 .of_match_table = of_match_ptr(arm_smmu_of_match),
1956 },
1957 .probe = arm_smmu_device_dt_probe,
1958 .remove = arm_smmu_device_remove,
1959 };
1960
1961 static int __init arm_smmu_init(void)
1962 {
1963 int ret;
1964
1965 ret = platform_driver_register(&arm_smmu_driver);
1966 if (ret)
1967 return ret;
1968
1969 /* Oh, for a proper bus abstraction */
1970 if (!iommu_present(&platform_bus_type))
1971 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1972
1973 if (!iommu_present(&amba_bustype))
1974 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1975
1976 return 0;
1977 }
1978
1979 static void __exit arm_smmu_exit(void)
1980 {
1981 return platform_driver_unregister(&arm_smmu_driver);
1982 }
1983
1984 module_init(arm_smmu_init);
1985 module_exit(arm_smmu_exit);
1986
1987 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1988 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1989 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support