mwl8k: increase firmware loading timeouts
[linux/fpc-iii.git] / arch / arm / mach-omap2 / clock.h
blob9ae7540f8af2c078e35ea661d759683414ad2664
1 /*
2 * linux/arch/arm/mach-omap2/clock.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 #include <mach/clock.h>
21 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
22 #define DEFAULT_DPLL_RATE_TOLERANCE 50000
24 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25 #define CORE_CLK_SRC_32K 0x0
26 #define CORE_CLK_SRC_DPLL 0x1
27 #define CORE_CLK_SRC_DPLL_X2 0x2
29 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
34 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
39 int omap2_clk_init(void);
40 int omap2_clk_enable(struct clk *clk);
41 void omap2_clk_disable(struct clk *clk);
42 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
43 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
44 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
45 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
46 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
48 #ifdef CONFIG_OMAP_RESET_CLOCKS
49 void omap2_clk_disable_unused(struct clk *clk);
50 #else
51 #define omap2_clk_disable_unused NULL
52 #endif
54 unsigned long omap2_clksel_recalc(struct clk *clk);
55 void omap2_init_clk_clkdm(struct clk *clk);
56 void omap2_init_clksel_parent(struct clk *clk);
57 u32 omap2_clksel_get_divisor(struct clk *clk);
58 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
59 u32 *new_div);
60 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
61 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
62 unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
63 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
64 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
65 u32 omap2_get_dpll_rate(struct clk *clk);
66 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
67 void omap2_clk_prepare_for_reboot(void);
68 int omap2_dflt_clk_enable(struct clk *clk);
69 void omap2_dflt_clk_disable(struct clk *clk);
70 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
71 u8 *other_bit);
72 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
73 u8 *idlest_bit);
75 extern const struct clkops clkops_omap2_dflt_wait;
76 extern const struct clkops clkops_omap2_dflt;
78 extern u8 cpu_mask;
80 /* clksel_rate data common to 24xx/343x */
81 static const struct clksel_rate gpt_32k_rates[] = {
82 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
83 { .div = 0 }
86 static const struct clksel_rate gpt_sys_rates[] = {
87 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
88 { .div = 0 }
91 static const struct clksel_rate gfx_l3_rates[] = {
92 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
93 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
94 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
95 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
96 { .div = 0 }
100 #endif