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objtool: Allow AR to be overridden with HOSTAR
[linux/fpc-iii.git] / drivers / ata / sata_dwc_460ex.c
blob6f142aa54f5f93a42d273b7ca20714124a39ea7c
1 /*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21 #ifdef CONFIG_SATA_DWC_DEBUG
22 #define DEBUG
23 #endif
24
25 #ifdef CONFIG_SATA_DWC_VDEBUG
26 #define VERBOSE_DEBUG
27 #define DEBUG_NCQ
28 #endif
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/device.h>
33 #include <linux/dmaengine.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/platform_device.h>
38 #include <linux/phy/phy.h>
39 #include <linux/libata.h>
40 #include <linux/slab.h>
41
42 #include "libata.h"
43
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46
47 /* These two are defined in "libata.h" */
48 #undef DRV_NAME
49 #undef DRV_VERSION
50
51 #define DRV_NAME "sata-dwc"
52 #define DRV_VERSION "1.3"
53
54 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
55 #define sata_dwc_readl(a) readl_relaxed(a)
56
57 #ifndef NO_IRQ
58 #define NO_IRQ 0
59 #endif
60
61 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
62
63 enum {
64 SATA_DWC_MAX_PORTS = 1,
65
66 SATA_DWC_SCR_OFFSET = 0x24,
67 SATA_DWC_REG_OFFSET = 0x64,
68 };
69
70 /* DWC SATA Registers */
71 struct sata_dwc_regs {
72 u32 fptagr; /* 1st party DMA tag */
73 u32 fpbor; /* 1st party DMA buffer offset */
74 u32 fptcr; /* 1st party DMA Xfr count */
75 u32 dmacr; /* DMA Control */
76 u32 dbtsr; /* DMA Burst Transac size */
77 u32 intpr; /* Interrupt Pending */
78 u32 intmr; /* Interrupt Mask */
79 u32 errmr; /* Error Mask */
80 u32 llcr; /* Link Layer Control */
81 u32 phycr; /* PHY Control */
82 u32 physr; /* PHY Status */
83 u32 rxbistpd; /* Recvd BIST pattern def register */
84 u32 rxbistpd1; /* Recvd BIST data dword1 */
85 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
86 u32 txbistpd; /* Trans BIST pattern def register */
87 u32 txbistpd1; /* Trans BIST data dword1 */
88 u32 txbistpd2; /* Trans BIST data dword2 */
89 u32 bistcr; /* BIST Control Register */
90 u32 bistfctr; /* BIST FIS Count Register */
91 u32 bistsr; /* BIST Status Register */
92 u32 bistdecr; /* BIST Dword Error count register */
93 u32 res[15]; /* Reserved locations */
94 u32 testr; /* Test Register */
95 u32 versionr; /* Version Register */
96 u32 idr; /* ID Register */
97 u32 unimpl[192]; /* Unimplemented */
98 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
99 };
100
101 enum {
102 SCR_SCONTROL_DET_ENABLE = 0x00000001,
103 SCR_SSTATUS_DET_PRESENT = 0x00000001,
104 SCR_SERROR_DIAG_X = 0x04000000,
105 /* DWC SATA Register Operations */
106 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
107 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
108 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
109 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
110 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
111 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
112 SATA_DWC_INTPR_DMAT = 0x00000001,
113 SATA_DWC_INTPR_NEWFP = 0x00000002,
114 SATA_DWC_INTPR_PMABRT = 0x00000004,
115 SATA_DWC_INTPR_ERR = 0x00000008,
116 SATA_DWC_INTPR_NEWBIST = 0x00000010,
117 SATA_DWC_INTPR_IPF = 0x10000000,
118 SATA_DWC_INTMR_DMATM = 0x00000001,
119 SATA_DWC_INTMR_NEWFPM = 0x00000002,
120 SATA_DWC_INTMR_PMABRTM = 0x00000004,
121 SATA_DWC_INTMR_ERRM = 0x00000008,
122 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
123 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
124 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
125 SATA_DWC_LLCR_RPDEN = 0x00000004,
126 /* This is all error bits, zero's are reserved fields. */
127 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
128 };
129
130 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
131 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132 SATA_DWC_DMACR_TMOD_TXCHEN)
133 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134 SATA_DWC_DMACR_TMOD_TXCHEN)
135 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
137 << 16)
138 struct sata_dwc_device {
139 struct device *dev; /* generic device struct */
140 struct ata_probe_ent *pe; /* ptr to probe-ent */
141 struct ata_host *host;
142 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
143 u32 sactive_issued;
144 u32 sactive_queued;
145 struct phy *phy;
146 phys_addr_t dmadr;
147 #ifdef CONFIG_SATA_DWC_OLD_DMA
148 struct dw_dma_chip *dma;
149 #endif
150 };
151
152 #define SATA_DWC_QCMD_MAX 32
153
154 struct sata_dwc_device_port {
155 struct sata_dwc_device *hsdev;
156 int cmd_issued[SATA_DWC_QCMD_MAX];
157 int dma_pending[SATA_DWC_QCMD_MAX];
158
159 /* DMA info */
160 struct dma_chan *chan;
161 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
162 u32 dma_interrupt_count;
163 };
164
165 /*
166 * Commonly used DWC SATA driver macros
167 */
168 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
173
174 enum {
175 SATA_DWC_CMD_ISSUED_NOT = 0,
176 SATA_DWC_CMD_ISSUED_PEND = 1,
177 SATA_DWC_CMD_ISSUED_EXEC = 2,
178 SATA_DWC_CMD_ISSUED_NODATA = 3,
179
180 SATA_DWC_DMA_PENDING_NONE = 0,
181 SATA_DWC_DMA_PENDING_TX = 1,
182 SATA_DWC_DMA_PENDING_RX = 2,
183 };
184
185 /*
186 * Prototypes
187 */
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
190 u32 check_status);
191 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192 static void sata_dwc_port_stop(struct ata_port *ap);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
194
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
196
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
199
200 static struct dw_dma_slave sata_dwc_dma_dws = {
201 .src_id = 0,
202 .dst_id = 0,
203 .m_master = 1,
204 .p_master = 0,
205 };
206
207 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
208 {
209 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
210
211 if (dws->dma_dev != chan->device->dev)
212 return false;
213
214 chan->private = dws;
215 return true;
216 }
217
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
219 {
220 struct sata_dwc_device *hsdev = hsdevp->hsdev;
221 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
222 dma_cap_mask_t mask;
223
224 dws->dma_dev = hsdev->dev;
225
226 dma_cap_zero(mask);
227 dma_cap_set(DMA_SLAVE, mask);
228
229 /* Acquire DMA channel */
230 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
231 if (!hsdevp->chan) {
232 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
233 __func__);
234 return -EAGAIN;
235 }
236
237 return 0;
238 }
239
240 static int sata_dwc_dma_init_old(struct platform_device *pdev,
241 struct sata_dwc_device *hsdev)
242 {
243 struct device_node *np = pdev->dev.of_node;
244 struct resource *res;
245
246 hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
247 if (!hsdev->dma)
248 return -ENOMEM;
249
250 hsdev->dma->dev = &pdev->dev;
251 hsdev->dma->id = pdev->id;
252
253 /* Get SATA DMA interrupt number */
254 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
255 if (hsdev->dma->irq == NO_IRQ) {
256 dev_err(&pdev->dev, "no SATA DMA irq\n");
257 return -ENODEV;
258 }
259
260 /* Get physical SATA DMA register base address */
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
262 hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
263 if (IS_ERR(hsdev->dma->regs))
264 return PTR_ERR(hsdev->dma->regs);
265
266 /* Initialize AHB DMAC */
267 return dw_dma_probe(hsdev->dma);
268 }
269
270 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
271 {
272 if (!hsdev->dma)
273 return;
274
275 dw_dma_remove(hsdev->dma);
276 }
277
278 #endif
279
280 static const char *get_prot_descript(u8 protocol)
281 {
282 switch (protocol) {
283 case ATA_PROT_NODATA:
284 return "ATA no data";
285 case ATA_PROT_PIO:
286 return "ATA PIO";
287 case ATA_PROT_DMA:
288 return "ATA DMA";
289 case ATA_PROT_NCQ:
290 return "ATA NCQ";
291 case ATA_PROT_NCQ_NODATA:
292 return "ATA NCQ no data";
293 case ATAPI_PROT_NODATA:
294 return "ATAPI no data";
295 case ATAPI_PROT_PIO:
296 return "ATAPI PIO";
297 case ATAPI_PROT_DMA:
298 return "ATAPI DMA";
299 default:
300 return "unknown";
301 }
302 }
303
304 static const char *get_dma_dir_descript(int dma_dir)
305 {
306 switch ((enum dma_data_direction)dma_dir) {
307 case DMA_BIDIRECTIONAL:
308 return "bidirectional";
309 case DMA_TO_DEVICE:
310 return "to device";
311 case DMA_FROM_DEVICE:
312 return "from device";
313 default:
314 return "none";
315 }
316 }
317
318 static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
319 {
320 dev_vdbg(ap->dev,
321 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
322 tf->command, get_prot_descript(tf->protocol), tf->flags,
323 tf->device);
324 dev_vdbg(ap->dev,
325 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
326 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
327 dev_vdbg(ap->dev,
328 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
329 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
330 tf->hob_lbah);
331 }
332
333 static void dma_dwc_xfer_done(void *hsdev_instance)
334 {
335 unsigned long flags;
336 struct sata_dwc_device *hsdev = hsdev_instance;
337 struct ata_host *host = (struct ata_host *)hsdev->host;
338 struct ata_port *ap;
339 struct sata_dwc_device_port *hsdevp;
340 u8 tag = 0;
341 unsigned int port = 0;
342
343 spin_lock_irqsave(&host->lock, flags);
344 ap = host->ports[port];
345 hsdevp = HSDEVP_FROM_AP(ap);
346 tag = ap->link.active_tag;
347
348 /*
349 * Each DMA command produces 2 interrupts. Only
350 * complete the command after both interrupts have been
351 * seen. (See sata_dwc_isr())
352 */
353 hsdevp->dma_interrupt_count++;
354 sata_dwc_clear_dmacr(hsdevp, tag);
355
356 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
357 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
358 tag, hsdevp->dma_pending[tag]);
359 }
360
361 if ((hsdevp->dma_interrupt_count % 2) == 0)
362 sata_dwc_dma_xfer_complete(ap, 1);
363
364 spin_unlock_irqrestore(&host->lock, flags);
365 }
366
367 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
368 {
369 struct ata_port *ap = qc->ap;
370 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
371 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
372 struct dma_slave_config sconf;
373 struct dma_async_tx_descriptor *desc;
374
375 if (qc->dma_dir == DMA_DEV_TO_MEM) {
376 sconf.src_addr = hsdev->dmadr;
377 sconf.device_fc = false;
378 } else { /* DMA_MEM_TO_DEV */
379 sconf.dst_addr = hsdev->dmadr;
380 sconf.device_fc = false;
381 }
382
383 sconf.direction = qc->dma_dir;
384 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
385 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
386 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
387 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
388
389 dmaengine_slave_config(hsdevp->chan, &sconf);
390
391 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
392 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
393 qc->dma_dir,
394 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
395
396 if (!desc)
397 return NULL;
398
399 desc->callback = dma_dwc_xfer_done;
400 desc->callback_param = hsdev;
401
402 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
403 qc->sg, qc->n_elem, &hsdev->dmadr);
404
405 return desc;
406 }
407
408 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
409 {
410 if (scr > SCR_NOTIFICATION) {
411 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
412 __func__, scr);
413 return -EINVAL;
414 }
415
416 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
417 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
418 link->ap->print_id, scr, *val);
419
420 return 0;
421 }
422
423 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
424 {
425 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
426 link->ap->print_id, scr, val);
427 if (scr > SCR_NOTIFICATION) {
428 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
429 __func__, scr);
430 return -EINVAL;
431 }
432 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
433
434 return 0;
435 }
436
437 static void clear_serror(struct ata_port *ap)
438 {
439 u32 val;
440 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
441 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
442 }
443
444 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
445 {
446 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
447 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
448 }
449
450 static u32 qcmd_tag_to_mask(u8 tag)
451 {
452 return 0x00000001 << (tag & 0x1f);
453 }
454
455 /* See ahci.c */
456 static void sata_dwc_error_intr(struct ata_port *ap,
457 struct sata_dwc_device *hsdev, uint intpr)
458 {
459 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
460 struct ata_eh_info *ehi = &ap->link.eh_info;
461 unsigned int err_mask = 0, action = 0;
462 struct ata_queued_cmd *qc;
463 u32 serror;
464 u8 status, tag;
465
466 ata_ehi_clear_desc(ehi);
467
468 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
469 status = ap->ops->sff_check_status(ap);
470
471 tag = ap->link.active_tag;
472
473 dev_err(ap->dev,
474 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
475 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
476 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
477
478 /* Clear error register and interrupt bit */
479 clear_serror(ap);
480 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
481
482 /* This is the only error happening now. TODO check for exact error */
483
484 err_mask |= AC_ERR_HOST_BUS;
485 action |= ATA_EH_RESET;
486
487 /* Pass this on to EH */
488 ehi->serror |= serror;
489 ehi->action |= action;
490
491 qc = ata_qc_from_tag(ap, tag);
492 if (qc)
493 qc->err_mask |= err_mask;
494 else
495 ehi->err_mask |= err_mask;
496
497 ata_port_abort(ap);
498 }
499
500 /*
501 * Function : sata_dwc_isr
502 * arguments : irq, void *dev_instance, struct pt_regs *regs
503 * Return value : irqreturn_t - status of IRQ
504 * This Interrupt handler called via port ops registered function.
505 * .irq_handler = sata_dwc_isr
506 */
507 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
508 {
509 struct ata_host *host = (struct ata_host *)dev_instance;
510 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
511 struct ata_port *ap;
512 struct ata_queued_cmd *qc;
513 unsigned long flags;
514 u8 status, tag;
515 int handled, num_processed, port = 0;
516 uint intpr, sactive, sactive2, tag_mask;
517 struct sata_dwc_device_port *hsdevp;
518 hsdev->sactive_issued = 0;
519
520 spin_lock_irqsave(&host->lock, flags);
521
522 /* Read the interrupt register */
523 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
524
525 ap = host->ports[port];
526 hsdevp = HSDEVP_FROM_AP(ap);
527
528 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
529 ap->link.active_tag);
530
531 /* Check for error interrupt */
532 if (intpr & SATA_DWC_INTPR_ERR) {
533 sata_dwc_error_intr(ap, hsdev, intpr);
534 handled = 1;
535 goto DONE;
536 }
537
538 /* Check for DMA SETUP FIS (FP DMA) interrupt */
539 if (intpr & SATA_DWC_INTPR_NEWFP) {
540 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
541
542 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
543 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
544 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
545 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
546
547 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
548
549 qc = ata_qc_from_tag(ap, tag);
550 /*
551 * Start FP DMA for NCQ command. At this point the tag is the
552 * active tag. It is the tag that matches the command about to
553 * be completed.
554 */
555 qc->ap->link.active_tag = tag;
556 sata_dwc_bmdma_start_by_tag(qc, tag);
557
558 handled = 1;
559 goto DONE;
560 }
561 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
562 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
563
564 /* If no sactive issued and tag_mask is zero then this is not NCQ */
565 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
566 if (ap->link.active_tag == ATA_TAG_POISON)
567 tag = 0;
568 else
569 tag = ap->link.active_tag;
570 qc = ata_qc_from_tag(ap, tag);
571
572 /* DEV interrupt w/ no active qc? */
573 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
574 dev_err(ap->dev,
575 "%s interrupt with no active qc qc=%p\n",
576 __func__, qc);
577 ap->ops->sff_check_status(ap);
578 handled = 1;
579 goto DONE;
580 }
581 status = ap->ops->sff_check_status(ap);
582
583 qc->ap->link.active_tag = tag;
584 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
585
586 if (status & ATA_ERR) {
587 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
588 sata_dwc_qc_complete(ap, qc, 1);
589 handled = 1;
590 goto DONE;
591 }
592
593 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
594 __func__, get_prot_descript(qc->tf.protocol));
595 DRVSTILLBUSY:
596 if (ata_is_dma(qc->tf.protocol)) {
597 /*
598 * Each DMA transaction produces 2 interrupts. The DMAC
599 * transfer complete interrupt and the SATA controller
600 * operation done interrupt. The command should be
601 * completed only after both interrupts are seen.
602 */
603 hsdevp->dma_interrupt_count++;
604 if (hsdevp->dma_pending[tag] == \
605 SATA_DWC_DMA_PENDING_NONE) {
606 dev_err(ap->dev,
607 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
608 __func__, intpr, status,
609 hsdevp->dma_pending[tag]);
610 }
611
612 if ((hsdevp->dma_interrupt_count % 2) == 0)
613 sata_dwc_dma_xfer_complete(ap, 1);
614 } else if (ata_is_pio(qc->tf.protocol)) {
615 ata_sff_hsm_move(ap, qc, status, 0);
616 handled = 1;
617 goto DONE;
618 } else {
619 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
620 goto DRVSTILLBUSY;
621 }
622
623 handled = 1;
624 goto DONE;
625 }
626
627 /*
628 * This is a NCQ command. At this point we need to figure out for which
629 * tags we have gotten a completion interrupt. One interrupt may serve
630 * as completion for more than one operation when commands are queued
631 * (NCQ). We need to process each completed command.
632 */
633
634 /* process completed commands */
635 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
636 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
637
638 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
639 dev_dbg(ap->dev,
640 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
641 __func__, sactive, hsdev->sactive_issued, tag_mask);
642 }
643
644 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
645 dev_warn(ap->dev,
646 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
647 sactive, hsdev->sactive_issued, tag_mask);
648 }
649
650 /* read just to clear ... not bad if currently still busy */
651 status = ap->ops->sff_check_status(ap);
652 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
653
654 tag = 0;
655 num_processed = 0;
656 while (tag_mask) {
657 num_processed++;
658 while (!(tag_mask & 0x00000001)) {
659 tag++;
660 tag_mask <<= 1;
661 }
662
663 tag_mask &= (~0x00000001);
664 qc = ata_qc_from_tag(ap, tag);
665
666 /* To be picked up by completion functions */
667 qc->ap->link.active_tag = tag;
668 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
669
670 /* Let libata/scsi layers handle error */
671 if (status & ATA_ERR) {
672 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
673 status);
674 sata_dwc_qc_complete(ap, qc, 1);
675 handled = 1;
676 goto DONE;
677 }
678
679 /* Process completed command */
680 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
681 get_prot_descript(qc->tf.protocol));
682 if (ata_is_dma(qc->tf.protocol)) {
683 hsdevp->dma_interrupt_count++;
684 if (hsdevp->dma_pending[tag] == \
685 SATA_DWC_DMA_PENDING_NONE)
686 dev_warn(ap->dev, "%s: DMA not pending?\n",
687 __func__);
688 if ((hsdevp->dma_interrupt_count % 2) == 0)
689 sata_dwc_dma_xfer_complete(ap, 1);
690 } else {
691 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
692 goto STILLBUSY;
693 }
694 continue;
695
696 STILLBUSY:
697 ap->stats.idle_irq++;
698 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
699 ap->print_id);
700 } /* while tag_mask */
701
702 /*
703 * Check to see if any commands completed while we were processing our
704 * initial set of completed commands (read status clears interrupts,
705 * so we might miss a completed command interrupt if one came in while
706 * we were processing --we read status as part of processing a completed
707 * command).
708 */
709 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
710 if (sactive2 != sactive) {
711 dev_dbg(ap->dev,
712 "More completed - sactive=0x%x sactive2=0x%x\n",
713 sactive, sactive2);
714 }
715 handled = 1;
716
717 DONE:
718 spin_unlock_irqrestore(&host->lock, flags);
719 return IRQ_RETVAL(handled);
720 }
721
722 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
723 {
724 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
725 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
726
727 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
728 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
729 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
730 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
731 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
732 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
733 } else {
734 /*
735 * This should not happen, it indicates the driver is out of
736 * sync. If it does happen, clear dmacr anyway.
737 */
738 dev_err(hsdev->dev,
739 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
740 __func__, tag, hsdevp->dma_pending[tag], dmacr);
741 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
742 SATA_DWC_DMACR_TXRXCH_CLEAR);
743 }
744 }
745
746 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
747 {
748 struct ata_queued_cmd *qc;
749 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
750 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
751 u8 tag = 0;
752
753 tag = ap->link.active_tag;
754 qc = ata_qc_from_tag(ap, tag);
755 if (!qc) {
756 dev_err(ap->dev, "failed to get qc");
757 return;
758 }
759
760 #ifdef DEBUG_NCQ
761 if (tag > 0) {
762 dev_info(ap->dev,
763 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
764 __func__, qc->hw_tag, qc->tf.command,
765 get_dma_dir_descript(qc->dma_dir),
766 get_prot_descript(qc->tf.protocol),
767 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
768 }
769 #endif
770
771 if (ata_is_dma(qc->tf.protocol)) {
772 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
773 dev_err(ap->dev,
774 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
775 __func__,
776 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
777 }
778
779 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
780 sata_dwc_qc_complete(ap, qc, check_status);
781 ap->link.active_tag = ATA_TAG_POISON;
782 } else {
783 sata_dwc_qc_complete(ap, qc, check_status);
784 }
785 }
786
787 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
788 u32 check_status)
789 {
790 u8 status = 0;
791 u32 mask = 0x0;
792 u8 tag = qc->hw_tag;
793 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
794 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
795 hsdev->sactive_queued = 0;
796 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
797
798 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
799 dev_err(ap->dev, "TX DMA PENDING\n");
800 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
801 dev_err(ap->dev, "RX DMA PENDING\n");
802 dev_dbg(ap->dev,
803 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
804 qc->tf.command, status, ap->print_id, qc->tf.protocol);
805
806 /* clear active bit */
807 mask = (~(qcmd_tag_to_mask(tag)));
808 hsdev->sactive_queued = hsdev->sactive_queued & mask;
809 hsdev->sactive_issued = hsdev->sactive_issued & mask;
810 ata_qc_complete(qc);
811 return 0;
812 }
813
814 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
815 {
816 /* Enable selective interrupts by setting the interrupt maskregister*/
817 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
818 SATA_DWC_INTMR_ERRM |
819 SATA_DWC_INTMR_NEWFPM |
820 SATA_DWC_INTMR_PMABRTM |
821 SATA_DWC_INTMR_DMATM);
822 /*
823 * Unmask the error bits that should trigger an error interrupt by
824 * setting the error mask register.
825 */
826 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
827
828 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
829 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
830 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
831 }
832
833 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
834 {
835 port->cmd_addr = base + 0x00;
836 port->data_addr = base + 0x00;
837
838 port->error_addr = base + 0x04;
839 port->feature_addr = base + 0x04;
840
841 port->nsect_addr = base + 0x08;
842
843 port->lbal_addr = base + 0x0c;
844 port->lbam_addr = base + 0x10;
845 port->lbah_addr = base + 0x14;
846
847 port->device_addr = base + 0x18;
848 port->command_addr = base + 0x1c;
849 port->status_addr = base + 0x1c;
850
851 port->altstatus_addr = base + 0x20;
852 port->ctl_addr = base + 0x20;
853 }
854
855 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
856 {
857 struct sata_dwc_device *hsdev = hsdevp->hsdev;
858 struct device *dev = hsdev->dev;
859
860 #ifdef CONFIG_SATA_DWC_OLD_DMA
861 if (!of_find_property(dev->of_node, "dmas", NULL))
862 return sata_dwc_dma_get_channel_old(hsdevp);
863 #endif
864
865 hsdevp->chan = dma_request_chan(dev, "sata-dma");
866 if (IS_ERR(hsdevp->chan)) {
867 dev_err(dev, "failed to allocate dma channel: %ld\n",
868 PTR_ERR(hsdevp->chan));
869 return PTR_ERR(hsdevp->chan);
870 }
871
872 return 0;
873 }
874
875 /*
876 * Function : sata_dwc_port_start
877 * arguments : struct ata_ioports *port
878 * Return value : returns 0 if success, error code otherwise
879 * This function allocates the scatter gather LLI table for AHB DMA
880 */
881 static int sata_dwc_port_start(struct ata_port *ap)
882 {
883 int err = 0;
884 struct sata_dwc_device *hsdev;
885 struct sata_dwc_device_port *hsdevp = NULL;
886 struct device *pdev;
887 int i;
888
889 hsdev = HSDEV_FROM_AP(ap);
890
891 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
892
893 hsdev->host = ap->host;
894 pdev = ap->host->dev;
895 if (!pdev) {
896 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
897 err = -ENODEV;
898 goto CLEANUP;
899 }
900
901 /* Allocate Port Struct */
902 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
903 if (!hsdevp) {
904 err = -ENOMEM;
905 goto CLEANUP;
906 }
907 hsdevp->hsdev = hsdev;
908
909 err = sata_dwc_dma_get_channel(hsdevp);
910 if (err)
911 goto CLEANUP_ALLOC;
912
913 err = phy_power_on(hsdev->phy);
914 if (err)
915 goto CLEANUP_ALLOC;
916
917 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
918 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
919
920 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
921 ap->bmdma_prd_dma = 0;
922
923 if (ap->port_no == 0) {
924 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
925 __func__);
926 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
927 SATA_DWC_DMACR_TXRXCH_CLEAR);
928
929 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
930 __func__);
931 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
932 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
933 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
934 }
935
936 /* Clear any error bits before libata starts issuing commands */
937 clear_serror(ap);
938 ap->private_data = hsdevp;
939 dev_dbg(ap->dev, "%s: done\n", __func__);
940 return 0;
941
942 CLEANUP_ALLOC:
943 kfree(hsdevp);
944 CLEANUP:
945 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
946 return err;
947 }
948
949 static void sata_dwc_port_stop(struct ata_port *ap)
950 {
951 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
952 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
953
954 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
955
956 dmaengine_terminate_sync(hsdevp->chan);
957 dma_release_channel(hsdevp->chan);
958 phy_power_off(hsdev->phy);
959
960 kfree(hsdevp);
961 ap->private_data = NULL;
962 }
963
964 /*
965 * Function : sata_dwc_exec_command_by_tag
966 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
967 * Return value : None
968 * This function keeps track of individual command tag ids and calls
969 * ata_exec_command in libata
970 */
971 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
972 struct ata_taskfile *tf,
973 u8 tag, u32 cmd_issued)
974 {
975 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
976
977 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
978 ata_get_cmd_descript(tf->command), tag);
979
980 hsdevp->cmd_issued[tag] = cmd_issued;
981
982 /*
983 * Clear SError before executing a new command.
984 * sata_dwc_scr_write and read can not be used here. Clearing the PM
985 * managed SError register for the disk needs to be done before the
986 * task file is loaded.
987 */
988 clear_serror(ap);
989 ata_sff_exec_command(ap, tf);
990 }
991
992 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
993 {
994 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
995 SATA_DWC_CMD_ISSUED_PEND);
996 }
997
998 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
999 {
1000 u8 tag = qc->hw_tag;
1001
1002 if (ata_is_ncq(qc->tf.protocol)) {
1003 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1004 __func__, qc->ap->link.sactive, tag);
1005 } else {
1006 tag = 0;
1007 }
1008 sata_dwc_bmdma_setup_by_tag(qc, tag);
1009 }
1010
1011 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1012 {
1013 int start_dma;
1014 u32 reg;
1015 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1016 struct ata_port *ap = qc->ap;
1017 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1018 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
1019 int dir = qc->dma_dir;
1020
1021 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1022 start_dma = 1;
1023 if (dir == DMA_TO_DEVICE)
1024 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1025 else
1026 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1027 } else {
1028 dev_err(ap->dev,
1029 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1030 __func__, hsdevp->cmd_issued[tag], tag);
1031 start_dma = 0;
1032 }
1033
1034 dev_dbg(ap->dev,
1035 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1036 __func__, qc, tag, qc->tf.command,
1037 get_dma_dir_descript(qc->dma_dir), start_dma);
1038 sata_dwc_tf_dump(ap, &qc->tf);
1039
1040 if (start_dma) {
1041 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
1042 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1043 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1044 __func__, reg);
1045 }
1046
1047 if (dir == DMA_TO_DEVICE)
1048 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1049 SATA_DWC_DMACR_TXCHEN);
1050 else
1051 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1052 SATA_DWC_DMACR_RXCHEN);
1053
1054 /* Enable AHB DMA transfer on the specified channel */
1055 dmaengine_submit(desc);
1056 dma_async_issue_pending(hsdevp->chan);
1057 }
1058 }
1059
1060 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1061 {
1062 u8 tag = qc->hw_tag;
1063
1064 if (ata_is_ncq(qc->tf.protocol)) {
1065 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1066 __func__, qc->ap->link.sactive, tag);
1067 } else {
1068 tag = 0;
1069 }
1070 dev_dbg(qc->ap->dev, "%s\n", __func__);
1071 sata_dwc_bmdma_start_by_tag(qc, tag);
1072 }
1073
1074 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1075 {
1076 u32 sactive;
1077 u8 tag = qc->hw_tag;
1078 struct ata_port *ap = qc->ap;
1079 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1080
1081 #ifdef DEBUG_NCQ
1082 if (qc->hw_tag > 0 || ap->link.sactive > 1)
1083 dev_info(ap->dev,
1084 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1085 __func__, ap->print_id, qc->tf.command,
1086 ata_get_cmd_descript(qc->tf.command),
1087 qc->hw_tag, get_prot_descript(qc->tf.protocol),
1088 ap->link.active_tag, ap->link.sactive);
1089 #endif
1090
1091 if (!ata_is_ncq(qc->tf.protocol))
1092 tag = 0;
1093
1094 if (ata_is_dma(qc->tf.protocol)) {
1095 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1096 if (!hsdevp->desc[tag])
1097 return AC_ERR_SYSTEM;
1098 } else {
1099 hsdevp->desc[tag] = NULL;
1100 }
1101
1102 if (ata_is_ncq(qc->tf.protocol)) {
1103 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1104 sactive |= (0x00000001 << tag);
1105 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1106
1107 dev_dbg(qc->ap->dev,
1108 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1109 __func__, tag, qc->ap->link.sactive, sactive);
1110
1111 ap->ops->sff_tf_load(ap, &qc->tf);
1112 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1113 SATA_DWC_CMD_ISSUED_PEND);
1114 } else {
1115 return ata_bmdma_qc_issue(qc);
1116 }
1117 return 0;
1118 }
1119
1120 static void sata_dwc_error_handler(struct ata_port *ap)
1121 {
1122 ata_sff_error_handler(ap);
1123 }
1124
1125 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1126 unsigned long deadline)
1127 {
1128 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1129 int ret;
1130
1131 ret = sata_sff_hardreset(link, class, deadline);
1132
1133 sata_dwc_enable_interrupts(hsdev);
1134
1135 /* Reconfigure the DMA control register */
1136 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1137 SATA_DWC_DMACR_TXRXCH_CLEAR);
1138
1139 /* Reconfigure the DMA Burst Transaction Size register */
1140 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1141 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1142 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1143
1144 return ret;
1145 }
1146
1147 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1148 {
1149 /* SATA DWC is master only */
1150 }
1151
1152 /*
1153 * scsi mid-layer and libata interface structures
1154 */
1155 static struct scsi_host_template sata_dwc_sht = {
1156 ATA_NCQ_SHT(DRV_NAME),
1157 /*
1158 * test-only: Currently this driver doesn't handle NCQ
1159 * correctly. We enable NCQ but set the queue depth to a
1160 * max of 1. This will get fixed in in a future release.
1161 */
1162 .sg_tablesize = LIBATA_MAX_PRD,
1163 /* .can_queue = ATA_MAX_QUEUE, */
1164 /*
1165 * Make sure a LLI block is not created that will span 8K max FIS
1166 * boundary. If the block spans such a FIS boundary, there is a chance
1167 * that a DMA burst will cross that boundary -- this results in an
1168 * error in the host controller.
1169 */
1170 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1171 };
1172
1173 static struct ata_port_operations sata_dwc_ops = {
1174 .inherits = &ata_sff_port_ops,
1175
1176 .error_handler = sata_dwc_error_handler,
1177 .hardreset = sata_dwc_hardreset,
1178
1179 .qc_issue = sata_dwc_qc_issue,
1180
1181 .scr_read = sata_dwc_scr_read,
1182 .scr_write = sata_dwc_scr_write,
1183
1184 .port_start = sata_dwc_port_start,
1185 .port_stop = sata_dwc_port_stop,
1186
1187 .sff_dev_select = sata_dwc_dev_select,
1188
1189 .bmdma_setup = sata_dwc_bmdma_setup,
1190 .bmdma_start = sata_dwc_bmdma_start,
1191 };
1192
1193 static const struct ata_port_info sata_dwc_port_info[] = {
1194 {
1195 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1196 .pio_mask = ATA_PIO4,
1197 .udma_mask = ATA_UDMA6,
1198 .port_ops = &sata_dwc_ops,
1199 },
1200 };
1201
1202 static int sata_dwc_probe(struct platform_device *ofdev)
1203 {
1204 struct sata_dwc_device *hsdev;
1205 u32 idr, versionr;
1206 char *ver = (char *)&versionr;
1207 void __iomem *base;
1208 int err = 0;
1209 int irq;
1210 struct ata_host *host;
1211 struct ata_port_info pi = sata_dwc_port_info[0];
1212 const struct ata_port_info *ppi[] = { &pi, NULL };
1213 struct device_node *np = ofdev->dev.of_node;
1214 struct resource *res;
1215
1216 /* Allocate DWC SATA device */
1217 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1218 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1219 if (!host || !hsdev)
1220 return -ENOMEM;
1221
1222 host->private_data = hsdev;
1223
1224 /* Ioremap SATA registers */
1225 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1226 base = devm_ioremap_resource(&ofdev->dev, res);
1227 if (IS_ERR(base))
1228 return PTR_ERR(base);
1229 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1230
1231 /* Synopsys DWC SATA specific Registers */
1232 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1233 hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1234
1235 /* Setup port */
1236 host->ports[0]->ioaddr.cmd_addr = base;
1237 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1238 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1239
1240 /* Read the ID and Version Registers */
1241 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1242 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1243 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1244 idr, ver[0], ver[1], ver[2]);
1245
1246 /* Save dev for later use in dev_xxx() routines */
1247 hsdev->dev = &ofdev->dev;
1248
1249 /* Enable SATA Interrupts */
1250 sata_dwc_enable_interrupts(hsdev);
1251
1252 /* Get SATA interrupt number */
1253 irq = irq_of_parse_and_map(np, 0);
1254 if (irq == NO_IRQ) {
1255 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1256 err = -ENODEV;
1257 goto error_out;
1258 }
1259
1260 #ifdef CONFIG_SATA_DWC_OLD_DMA
1261 if (!of_find_property(np, "dmas", NULL)) {
1262 err = sata_dwc_dma_init_old(ofdev, hsdev);
1263 if (err)
1264 goto error_out;
1265 }
1266 #endif
1267
1268 hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1269 if (IS_ERR(hsdev->phy)) {
1270 err = PTR_ERR(hsdev->phy);
1271 hsdev->phy = NULL;
1272 goto error_out;
1273 }
1274
1275 err = phy_init(hsdev->phy);
1276 if (err)
1277 goto error_out;
1278
1279 /*
1280 * Now, register with libATA core, this will also initiate the
1281 * device discovery process, invoking our port_start() handler &
1282 * error_handler() to execute a dummy Softreset EH session
1283 */
1284 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1285 if (err)
1286 dev_err(&ofdev->dev, "failed to activate host");
1287
1288 return 0;
1289
1290 error_out:
1291 phy_exit(hsdev->phy);
1292 return err;
1293 }
1294
1295 static int sata_dwc_remove(struct platform_device *ofdev)
1296 {
1297 struct device *dev = &ofdev->dev;
1298 struct ata_host *host = dev_get_drvdata(dev);
1299 struct sata_dwc_device *hsdev = host->private_data;
1300
1301 ata_host_detach(host);
1302
1303 phy_exit(hsdev->phy);
1304
1305 #ifdef CONFIG_SATA_DWC_OLD_DMA
1306 /* Free SATA DMA resources */
1307 sata_dwc_dma_exit_old(hsdev);
1308 #endif
1309
1310 dev_dbg(&ofdev->dev, "done\n");
1311 return 0;
1312 }
1313
1314 static const struct of_device_id sata_dwc_match[] = {
1315 { .compatible = "amcc,sata-460ex", },
1316 {}
1317 };
1318 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1319
1320 static struct platform_driver sata_dwc_driver = {
1321 .driver = {
1322 .name = DRV_NAME,
1323 .of_match_table = sata_dwc_match,
1324 },
1325 .probe = sata_dwc_probe,
1326 .remove = sata_dwc_remove,
1327 };
1328
1329 module_platform_driver(sata_dwc_driver);
1330
1331 MODULE_LICENSE("GPL");
1332 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1333 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1334 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support