2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
28 /* EXYNOS5440 GPIO and Pinctrl register offsets */
32 #define GPIO_TYPE 0x0C
42 #define EXYNOS5440_MAX_PINS 23
43 #define EXYNOS5440_MAX_GPIO_INT 8
44 #define PIN_NAME_LENGTH 10
46 #define GROUP_SUFFIX "-grp"
47 #define FUNCTION_SUFFIX "-mux"
50 * pin configuration type and its value are packed together into a 16-bits.
51 * The upper 8-bits represent the configuration type and the lower 8-bits
52 * hold the value of the configuration type.
54 #define PINCFG_TYPE_MASK 0xFF
55 #define PINCFG_VALUE_SHIFT 8
56 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
57 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
58 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
59 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
63 * enum pincfg_type - possible pin configuration types supported.
64 * @PINCFG_TYPE_PUD: Pull up/down configuration.
65 * @PINCFG_TYPE_DRV: Drive strength configuration.
66 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
67 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
72 PINCFG_TYPE_SKEW_RATE
,
73 PINCFG_TYPE_INPUT_TYPE
77 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
78 * @name: name of the pin group, used to lookup the group.
79 * @pins: the pins included in this group.
80 * @num_pins: number of pins included in this group.
82 struct exynos5440_pin_group
{
84 const unsigned int *pins
;
89 * struct exynos5440_pmx_func: represent a pin function.
90 * @name: name of the pin function, used to lookup the function.
91 * @groups: one or more names of pin groups that provide this function.
92 * @num_groups: number of groups included in @groups.
93 * @function: the function number to be programmed when selected.
95 struct exynos5440_pmx_func
{
99 unsigned long function
;
103 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
104 * @reg_base: ioremapped based address of the register space.
105 * @gc: gpio chip registered with gpiolib.
106 * @pin_groups: list of pin groups parsed from device tree.
107 * @nr_groups: number of pin groups available.
108 * @pmx_functions: list of pin functions parsed from device tree.
109 * @nr_functions: number of pin functions available.
110 * @range: gpio range to register with pinctrl
112 struct exynos5440_pinctrl_priv_data
{
113 void __iomem
*reg_base
;
114 struct gpio_chip
*gc
;
115 struct irq_domain
*irq_domain
;
117 const struct exynos5440_pin_group
*pin_groups
;
118 unsigned int nr_groups
;
119 const struct exynos5440_pmx_func
*pmx_functions
;
120 unsigned int nr_functions
;
121 struct pinctrl_gpio_range range
;
125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126 * @priv: driver's private runtime data.
127 * @gpio_int: gpio interrupt number.
129 struct exynos5440_gpio_intr_data
{
130 struct exynos5440_pinctrl_priv_data
*priv
;
131 unsigned int gpio_int
;
134 /* list of all possible config options supported */
135 static struct pin_config
{
137 unsigned int cfg_type
;
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD
},
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV
},
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE
},
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE
},
145 /* check if the selector is a valid pin group selector */
146 static int exynos5440_get_group_count(struct pinctrl_dev
*pctldev
)
148 struct exynos5440_pinctrl_priv_data
*priv
;
150 priv
= pinctrl_dev_get_drvdata(pctldev
);
151 return priv
->nr_groups
;
154 /* return the name of the group selected by the group selector */
155 static const char *exynos5440_get_group_name(struct pinctrl_dev
*pctldev
,
158 struct exynos5440_pinctrl_priv_data
*priv
;
160 priv
= pinctrl_dev_get_drvdata(pctldev
);
161 return priv
->pin_groups
[selector
].name
;
164 /* return the pin numbers associated with the specified group */
165 static int exynos5440_get_group_pins(struct pinctrl_dev
*pctldev
,
166 unsigned selector
, const unsigned **pins
, unsigned *num_pins
)
168 struct exynos5440_pinctrl_priv_data
*priv
;
170 priv
= pinctrl_dev_get_drvdata(pctldev
);
171 *pins
= priv
->pin_groups
[selector
].pins
;
172 *num_pins
= priv
->pin_groups
[selector
].num_pins
;
176 /* create pinctrl_map entries by parsing device tree nodes */
177 static int exynos5440_dt_node_to_map(struct pinctrl_dev
*pctldev
,
178 struct device_node
*np
, struct pinctrl_map
**maps
,
181 struct device
*dev
= pctldev
->dev
;
182 struct pinctrl_map
*map
;
183 unsigned long *cfg
= NULL
;
185 int cfg_cnt
= 0, map_cnt
= 0, idx
= 0;
187 /* count the number of config options specfied in the node */
188 for (idx
= 0; idx
< ARRAY_SIZE(pcfgs
); idx
++)
189 if (of_find_property(np
, pcfgs
[idx
].prop_cfg
, NULL
))
193 * Find out the number of map entries to create. All the config options
194 * can be accomadated into a single config map entry.
198 if (of_find_property(np
, "samsung,exynos5440-pin-function", NULL
))
201 dev_err(dev
, "node %s does not have either config or function "
202 "configurations\n", np
->name
);
206 /* Allocate memory for pin-map entries */
207 map
= kzalloc(sizeof(*map
) * map_cnt
, GFP_KERNEL
);
213 * Allocate memory for pin group name. The pin group name is derived
214 * from the node name from which these map entries are be created.
216 gname
= kasprintf(GFP_KERNEL
, "%s%s", np
->name
, GROUP_SUFFIX
);
221 * don't have config options? then skip over to creating function
227 /* Allocate memory for config entries */
228 cfg
= kzalloc(sizeof(*cfg
) * cfg_cnt
, GFP_KERNEL
);
232 /* Prepare a list of config settings */
233 for (idx
= 0, cfg_cnt
= 0; idx
< ARRAY_SIZE(pcfgs
); idx
++) {
235 if (!of_property_read_u32(np
, pcfgs
[idx
].prop_cfg
, &value
))
237 PINCFG_PACK(pcfgs
[idx
].cfg_type
, value
);
240 /* create the config map entry */
241 map
[*nmaps
].data
.configs
.group_or_pin
= gname
;
242 map
[*nmaps
].data
.configs
.configs
= cfg
;
243 map
[*nmaps
].data
.configs
.num_configs
= cfg_cnt
;
244 map
[*nmaps
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
248 /* create the function map entry */
249 if (of_find_property(np
, "samsung,exynos5440-pin-function", NULL
)) {
250 fname
= kasprintf(GFP_KERNEL
,
251 "%s%s", np
->name
, FUNCTION_SUFFIX
);
255 map
[*nmaps
].data
.mux
.group
= gname
;
256 map
[*nmaps
].data
.mux
.function
= fname
;
257 map
[*nmaps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
273 /* free the memory allocated to hold the pin-map table */
274 static void exynos5440_dt_free_map(struct pinctrl_dev
*pctldev
,
275 struct pinctrl_map
*map
, unsigned num_maps
)
279 for (idx
= 0; idx
< num_maps
; idx
++) {
280 if (map
[idx
].type
== PIN_MAP_TYPE_MUX_GROUP
) {
281 kfree(map
[idx
].data
.mux
.function
);
283 kfree(map
[idx
].data
.mux
.group
);
284 } else if (map
->type
== PIN_MAP_TYPE_CONFIGS_GROUP
) {
285 kfree(map
[idx
].data
.configs
.configs
);
287 kfree(map
[idx
].data
.configs
.group_or_pin
);
294 /* list of pinctrl callbacks for the pinctrl core */
295 static const struct pinctrl_ops exynos5440_pctrl_ops
= {
296 .get_groups_count
= exynos5440_get_group_count
,
297 .get_group_name
= exynos5440_get_group_name
,
298 .get_group_pins
= exynos5440_get_group_pins
,
299 .dt_node_to_map
= exynos5440_dt_node_to_map
,
300 .dt_free_map
= exynos5440_dt_free_map
,
303 /* check if the selector is a valid pin function selector */
304 static int exynos5440_get_functions_count(struct pinctrl_dev
*pctldev
)
306 struct exynos5440_pinctrl_priv_data
*priv
;
308 priv
= pinctrl_dev_get_drvdata(pctldev
);
309 return priv
->nr_functions
;
312 /* return the name of the pin function specified */
313 static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev
*pctldev
,
316 struct exynos5440_pinctrl_priv_data
*priv
;
318 priv
= pinctrl_dev_get_drvdata(pctldev
);
319 return priv
->pmx_functions
[selector
].name
;
322 /* return the groups associated for the specified function selector */
323 static int exynos5440_pinmux_get_groups(struct pinctrl_dev
*pctldev
,
324 unsigned selector
, const char * const **groups
,
325 unsigned * const num_groups
)
327 struct exynos5440_pinctrl_priv_data
*priv
;
329 priv
= pinctrl_dev_get_drvdata(pctldev
);
330 *groups
= priv
->pmx_functions
[selector
].groups
;
331 *num_groups
= priv
->pmx_functions
[selector
].num_groups
;
335 /* enable or disable a pinmux function */
336 static void exynos5440_pinmux_setup(struct pinctrl_dev
*pctldev
, unsigned selector
,
337 unsigned group
, bool enable
)
339 struct exynos5440_pinctrl_priv_data
*priv
;
344 priv
= pinctrl_dev_get_drvdata(pctldev
);
345 base
= priv
->reg_base
;
346 function
= priv
->pmx_functions
[selector
].function
;
348 data
= readl(base
+ GPIO_MUX
);
350 data
|= (1 << function
);
352 data
&= ~(1 << function
);
353 writel(data
, base
+ GPIO_MUX
);
356 /* enable a specified pinmux by writing to registers */
357 static int exynos5440_pinmux_set_mux(struct pinctrl_dev
*pctldev
,
361 exynos5440_pinmux_setup(pctldev
, selector
, group
, true);
366 * The calls to gpio_direction_output() and gpio_direction_input()
367 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
368 * function called from the gpiolib interface).
370 static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev
*pctldev
,
371 struct pinctrl_gpio_range
*range
, unsigned offset
, bool input
)
376 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
377 static const struct pinmux_ops exynos5440_pinmux_ops
= {
378 .get_functions_count
= exynos5440_get_functions_count
,
379 .get_function_name
= exynos5440_pinmux_get_fname
,
380 .get_function_groups
= exynos5440_pinmux_get_groups
,
381 .set_mux
= exynos5440_pinmux_set_mux
,
382 .gpio_set_direction
= exynos5440_pinmux_gpio_set_direction
,
385 /* set the pin config settings for a specified pin */
386 static int exynos5440_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
387 unsigned long *configs
,
388 unsigned num_configs
)
390 struct exynos5440_pinctrl_priv_data
*priv
;
392 enum pincfg_type cfg_type
;
397 priv
= pinctrl_dev_get_drvdata(pctldev
);
398 base
= priv
->reg_base
;
400 for (i
= 0; i
< num_configs
; i
++) {
401 cfg_type
= PINCFG_UNPACK_TYPE(configs
[i
]);
402 cfg_value
= PINCFG_UNPACK_VALUE(configs
[i
]);
405 case PINCFG_TYPE_PUD
:
406 /* first set pull enable/disable bit */
407 data
= readl(base
+ GPIO_PE
);
411 writel(data
, base
+ GPIO_PE
);
413 /* then set pull up/down bit */
414 data
= readl(base
+ GPIO_PS
);
418 writel(data
, base
+ GPIO_PS
);
421 case PINCFG_TYPE_DRV
:
422 /* set the first bit of the drive strength */
423 data
= readl(base
+ GPIO_DS0
);
425 data
|= ((cfg_value
& 1) << pin
);
426 writel(data
, base
+ GPIO_DS0
);
429 /* set the second bit of the driver strength */
430 data
= readl(base
+ GPIO_DS1
);
432 data
|= ((cfg_value
& 1) << pin
);
433 writel(data
, base
+ GPIO_DS1
);
435 case PINCFG_TYPE_SKEW_RATE
:
436 data
= readl(base
+ GPIO_SR
);
438 data
|= ((cfg_value
& 1) << pin
);
439 writel(data
, base
+ GPIO_SR
);
441 case PINCFG_TYPE_INPUT_TYPE
:
442 data
= readl(base
+ GPIO_TYPE
);
444 data
|= ((cfg_value
& 1) << pin
);
445 writel(data
, base
+ GPIO_TYPE
);
451 } /* for each config */
456 /* get the pin config settings for a specified pin */
457 static int exynos5440_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned int pin
,
458 unsigned long *config
)
460 struct exynos5440_pinctrl_priv_data
*priv
;
462 enum pincfg_type cfg_type
= PINCFG_UNPACK_TYPE(*config
);
465 priv
= pinctrl_dev_get_drvdata(pctldev
);
466 base
= priv
->reg_base
;
469 case PINCFG_TYPE_PUD
:
470 data
= readl(base
+ GPIO_PE
);
471 data
= (data
>> pin
) & 1;
475 *config
= ((readl(base
+ GPIO_PS
) >> pin
) & 1) + 1;
477 case PINCFG_TYPE_DRV
:
478 data
= readl(base
+ GPIO_DS0
);
479 data
= (data
>> pin
) & 1;
481 data
= readl(base
+ GPIO_DS1
);
482 data
= (data
>> pin
) & 1;
483 *config
|= (data
<< 1);
485 case PINCFG_TYPE_SKEW_RATE
:
486 data
= readl(base
+ GPIO_SR
);
487 *config
= (data
>> pin
) & 1;
489 case PINCFG_TYPE_INPUT_TYPE
:
490 data
= readl(base
+ GPIO_TYPE
);
491 *config
= (data
>> pin
) & 1;
501 /* set the pin config settings for a specified pin group */
502 static int exynos5440_pinconf_group_set(struct pinctrl_dev
*pctldev
,
503 unsigned group
, unsigned long *configs
,
504 unsigned num_configs
)
506 struct exynos5440_pinctrl_priv_data
*priv
;
507 const unsigned int *pins
;
510 priv
= pinctrl_dev_get_drvdata(pctldev
);
511 pins
= priv
->pin_groups
[group
].pins
;
513 for (cnt
= 0; cnt
< priv
->pin_groups
[group
].num_pins
; cnt
++)
514 exynos5440_pinconf_set(pctldev
, pins
[cnt
], configs
,
520 /* get the pin config settings for a specified pin group */
521 static int exynos5440_pinconf_group_get(struct pinctrl_dev
*pctldev
,
522 unsigned int group
, unsigned long *config
)
524 struct exynos5440_pinctrl_priv_data
*priv
;
525 const unsigned int *pins
;
527 priv
= pinctrl_dev_get_drvdata(pctldev
);
528 pins
= priv
->pin_groups
[group
].pins
;
529 exynos5440_pinconf_get(pctldev
, pins
[0], config
);
533 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
534 static const struct pinconf_ops exynos5440_pinconf_ops
= {
535 .pin_config_get
= exynos5440_pinconf_get
,
536 .pin_config_set
= exynos5440_pinconf_set
,
537 .pin_config_group_get
= exynos5440_pinconf_group_get
,
538 .pin_config_group_set
= exynos5440_pinconf_group_set
,
541 /* gpiolib gpio_set callback function */
542 static void exynos5440_gpio_set(struct gpio_chip
*gc
, unsigned offset
, int value
)
544 struct exynos5440_pinctrl_priv_data
*priv
= gpiochip_get_data(gc
);
545 void __iomem
*base
= priv
->reg_base
;
548 data
= readl(base
+ GPIO_VAL
);
549 data
&= ~(1 << offset
);
552 writel(data
, base
+ GPIO_VAL
);
555 /* gpiolib gpio_get callback function */
556 static int exynos5440_gpio_get(struct gpio_chip
*gc
, unsigned offset
)
558 struct exynos5440_pinctrl_priv_data
*priv
= gpiochip_get_data(gc
);
559 void __iomem
*base
= priv
->reg_base
;
562 data
= readl(base
+ GPIO_IN
);
568 /* gpiolib gpio_direction_input callback function */
569 static int exynos5440_gpio_direction_input(struct gpio_chip
*gc
, unsigned offset
)
571 struct exynos5440_pinctrl_priv_data
*priv
= gpiochip_get_data(gc
);
572 void __iomem
*base
= priv
->reg_base
;
575 /* first disable the data output enable on this pin */
576 data
= readl(base
+ GPIO_OE
);
577 data
&= ~(1 << offset
);
578 writel(data
, base
+ GPIO_OE
);
580 /* now enable input on this pin */
581 data
= readl(base
+ GPIO_IE
);
583 writel(data
, base
+ GPIO_IE
);
587 /* gpiolib gpio_direction_output callback function */
588 static int exynos5440_gpio_direction_output(struct gpio_chip
*gc
, unsigned offset
,
591 struct exynos5440_pinctrl_priv_data
*priv
= gpiochip_get_data(gc
);
592 void __iomem
*base
= priv
->reg_base
;
595 exynos5440_gpio_set(gc
, offset
, value
);
597 /* first disable the data input enable on this pin */
598 data
= readl(base
+ GPIO_IE
);
599 data
&= ~(1 << offset
);
600 writel(data
, base
+ GPIO_IE
);
602 /* now enable output on this pin */
603 data
= readl(base
+ GPIO_OE
);
605 writel(data
, base
+ GPIO_OE
);
609 /* gpiolib gpio_to_irq callback function */
610 static int exynos5440_gpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
612 struct exynos5440_pinctrl_priv_data
*priv
= gpiochip_get_data(gc
);
615 if (offset
< 16 || offset
> 23)
618 if (!priv
->irq_domain
)
621 virq
= irq_create_mapping(priv
->irq_domain
, offset
- 16);
622 return virq
? : -ENXIO
;
625 /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
626 static int exynos5440_pinctrl_parse_dt_pins(struct platform_device
*pdev
,
627 struct device_node
*cfg_np
, unsigned int **pin_list
,
630 struct device
*dev
= &pdev
->dev
;
631 struct property
*prop
;
633 prop
= of_find_property(cfg_np
, "samsung,exynos5440-pins", NULL
);
637 *npins
= prop
->length
/ sizeof(unsigned long);
639 dev_err(dev
, "invalid pin list in %s node", cfg_np
->name
);
643 *pin_list
= devm_kzalloc(dev
, *npins
* sizeof(**pin_list
), GFP_KERNEL
);
647 return of_property_read_u32_array(cfg_np
, "samsung,exynos5440-pins",
652 * Parse the information about all the available pin groups and pin functions
653 * from device node of the pin-controller.
655 static int exynos5440_pinctrl_parse_dt(struct platform_device
*pdev
,
656 struct exynos5440_pinctrl_priv_data
*priv
)
658 struct device
*dev
= &pdev
->dev
;
659 struct device_node
*dev_np
= dev
->of_node
;
660 struct device_node
*cfg_np
;
661 struct exynos5440_pin_group
*groups
, *grp
;
662 struct exynos5440_pmx_func
*functions
, *func
;
664 unsigned int npins
, grp_cnt
, func_idx
= 0;
668 grp_cnt
= of_get_child_count(dev_np
);
672 groups
= devm_kzalloc(dev
, grp_cnt
* sizeof(*groups
), GFP_KERNEL
);
678 functions
= devm_kzalloc(dev
, grp_cnt
* sizeof(*functions
), GFP_KERNEL
);
685 * Iterate over all the child nodes of the pin controller node
686 * and create pin groups and pin function lists.
688 for_each_child_of_node(dev_np
, cfg_np
) {
691 ret
= exynos5440_pinctrl_parse_dt_pins(pdev
, cfg_np
,
695 goto skip_to_pin_function
;
698 /* derive pin group name from the node name */
699 gname
= devm_kasprintf(dev
, GFP_KERNEL
,
700 "%s%s", cfg_np
->name
, GROUP_SUFFIX
);
705 grp
->pins
= pin_list
;
706 grp
->num_pins
= npins
;
709 skip_to_pin_function
:
710 ret
= of_property_read_u32(cfg_np
, "samsung,exynos5440-pin-function",
715 /* derive function name from the node name */
716 fname
= devm_kasprintf(dev
, GFP_KERNEL
,
717 "%s%s", cfg_np
->name
, FUNCTION_SUFFIX
);
722 func
->groups
= devm_kzalloc(dev
, sizeof(char *), GFP_KERNEL
);
725 func
->groups
[0] = gname
;
726 func
->num_groups
= gname
? 1 : 0;
727 func
->function
= function
;
732 priv
->pin_groups
= groups
;
733 priv
->nr_groups
= grp_cnt
;
734 priv
->pmx_functions
= functions
;
735 priv
->nr_functions
= func_idx
;
739 /* register the pinctrl interface with the pinctrl subsystem */
740 static int exynos5440_pinctrl_register(struct platform_device
*pdev
,
741 struct exynos5440_pinctrl_priv_data
*priv
)
743 struct device
*dev
= &pdev
->dev
;
744 struct pinctrl_desc
*ctrldesc
;
745 struct pinctrl_dev
*pctl_dev
;
746 struct pinctrl_pin_desc
*pindesc
, *pdesc
;
750 ctrldesc
= devm_kzalloc(dev
, sizeof(*ctrldesc
), GFP_KERNEL
);
754 ctrldesc
->name
= "exynos5440-pinctrl";
755 ctrldesc
->owner
= THIS_MODULE
;
756 ctrldesc
->pctlops
= &exynos5440_pctrl_ops
;
757 ctrldesc
->pmxops
= &exynos5440_pinmux_ops
;
758 ctrldesc
->confops
= &exynos5440_pinconf_ops
;
760 pindesc
= devm_kzalloc(&pdev
->dev
, sizeof(*pindesc
) *
761 EXYNOS5440_MAX_PINS
, GFP_KERNEL
);
764 ctrldesc
->pins
= pindesc
;
765 ctrldesc
->npins
= EXYNOS5440_MAX_PINS
;
767 /* dynamically populate the pin number and pin name for pindesc */
768 for (pin
= 0, pdesc
= pindesc
; pin
< ctrldesc
->npins
; pin
++, pdesc
++)
772 * allocate space for storing the dynamically generated names for all
773 * the pins which belong to this pin-controller.
775 pin_names
= devm_kzalloc(&pdev
->dev
, sizeof(char) * PIN_NAME_LENGTH
*
776 ctrldesc
->npins
, GFP_KERNEL
);
780 /* for each pin, set the name of the pin */
781 for (pin
= 0; pin
< ctrldesc
->npins
; pin
++) {
782 snprintf(pin_names
, 6, "gpio%02d", pin
);
783 pdesc
= pindesc
+ pin
;
784 pdesc
->name
= pin_names
;
785 pin_names
+= PIN_NAME_LENGTH
;
788 ret
= exynos5440_pinctrl_parse_dt(pdev
, priv
);
792 pctl_dev
= devm_pinctrl_register(&pdev
->dev
, ctrldesc
, priv
);
793 if (IS_ERR(pctl_dev
)) {
794 dev_err(&pdev
->dev
, "could not register pinctrl driver\n");
795 return PTR_ERR(pctl_dev
);
798 priv
->range
.name
= "exynos5440-pctrl-gpio-range";
800 priv
->range
.base
= 0;
801 priv
->range
.npins
= EXYNOS5440_MAX_PINS
;
802 priv
->range
.gc
= priv
->gc
;
803 pinctrl_add_gpio_range(pctl_dev
, &priv
->range
);
807 /* register the gpiolib interface with the gpiolib subsystem */
808 static int exynos5440_gpiolib_register(struct platform_device
*pdev
,
809 struct exynos5440_pinctrl_priv_data
*priv
)
811 struct gpio_chip
*gc
;
814 gc
= devm_kzalloc(&pdev
->dev
, sizeof(*gc
), GFP_KERNEL
);
820 gc
->ngpio
= EXYNOS5440_MAX_PINS
;
821 gc
->parent
= &pdev
->dev
;
822 gc
->set
= exynos5440_gpio_set
;
823 gc
->get
= exynos5440_gpio_get
;
824 gc
->direction_input
= exynos5440_gpio_direction_input
;
825 gc
->direction_output
= exynos5440_gpio_direction_output
;
826 gc
->to_irq
= exynos5440_gpio_to_irq
;
827 gc
->label
= "gpiolib-exynos5440";
828 gc
->owner
= THIS_MODULE
;
829 ret
= gpiochip_add_data(gc
, priv
);
831 dev_err(&pdev
->dev
, "failed to register gpio_chip %s, error "
832 "code: %d\n", gc
->label
, ret
);
839 /* unregister the gpiolib interface with the gpiolib subsystem */
840 static int exynos5440_gpiolib_unregister(struct platform_device
*pdev
,
841 struct exynos5440_pinctrl_priv_data
*priv
)
843 gpiochip_remove(priv
->gc
);
847 static void exynos5440_gpio_irq_unmask(struct irq_data
*irqd
)
849 struct exynos5440_pinctrl_priv_data
*d
;
850 unsigned long gpio_int
;
852 d
= irq_data_get_irq_chip_data(irqd
);
853 gpio_int
= readl(d
->reg_base
+ GPIO_INT
);
854 gpio_int
|= 1 << irqd
->hwirq
;
855 writel(gpio_int
, d
->reg_base
+ GPIO_INT
);
858 static void exynos5440_gpio_irq_mask(struct irq_data
*irqd
)
860 struct exynos5440_pinctrl_priv_data
*d
;
861 unsigned long gpio_int
;
863 d
= irq_data_get_irq_chip_data(irqd
);
864 gpio_int
= readl(d
->reg_base
+ GPIO_INT
);
865 gpio_int
&= ~(1 << irqd
->hwirq
);
866 writel(gpio_int
, d
->reg_base
+ GPIO_INT
);
869 /* irq_chip for gpio interrupts */
870 static struct irq_chip exynos5440_gpio_irq_chip
= {
871 .name
= "exynos5440_gpio_irq_chip",
872 .irq_unmask
= exynos5440_gpio_irq_unmask
,
873 .irq_mask
= exynos5440_gpio_irq_mask
,
876 /* interrupt handler for GPIO interrupts 0..7 */
877 static irqreturn_t
exynos5440_gpio_irq(int irq
, void *data
)
879 struct exynos5440_gpio_intr_data
*intd
= data
;
880 struct exynos5440_pinctrl_priv_data
*d
= intd
->priv
;
883 virq
= irq_linear_revmap(d
->irq_domain
, intd
->gpio_int
);
886 generic_handle_irq(virq
);
890 static int exynos5440_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
893 struct exynos5440_pinctrl_priv_data
*d
= h
->host_data
;
895 irq_set_chip_data(virq
, d
);
896 irq_set_chip_and_handler(virq
, &exynos5440_gpio_irq_chip
,
901 /* irq domain callbacks for gpio interrupt controller */
902 static const struct irq_domain_ops exynos5440_gpio_irqd_ops
= {
903 .map
= exynos5440_gpio_irq_map
,
904 .xlate
= irq_domain_xlate_twocell
,
907 /* setup handling of gpio interrupts */
908 static int exynos5440_gpio_irq_init(struct platform_device
*pdev
,
909 struct exynos5440_pinctrl_priv_data
*priv
)
911 struct device
*dev
= &pdev
->dev
;
912 struct exynos5440_gpio_intr_data
*intd
;
915 intd
= devm_kzalloc(dev
, sizeof(*intd
) * EXYNOS5440_MAX_GPIO_INT
,
920 for (i
= 0; i
< EXYNOS5440_MAX_GPIO_INT
; i
++) {
921 irq
= irq_of_parse_and_map(dev
->of_node
, i
);
923 dev_err(dev
, "irq parsing failed\n");
929 ret
= devm_request_irq(dev
, irq
, exynos5440_gpio_irq
,
930 0, dev_name(dev
), intd
++);
932 dev_err(dev
, "irq request failed\n");
937 priv
->irq_domain
= irq_domain_add_linear(dev
->of_node
,
938 EXYNOS5440_MAX_GPIO_INT
,
939 &exynos5440_gpio_irqd_ops
, priv
);
940 if (!priv
->irq_domain
) {
941 dev_err(dev
, "failed to create irq domain\n");
948 static int exynos5440_pinctrl_probe(struct platform_device
*pdev
)
950 struct device
*dev
= &pdev
->dev
;
951 struct exynos5440_pinctrl_priv_data
*priv
;
952 struct resource
*res
;
956 dev_err(dev
, "device tree node not found\n");
960 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
964 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
965 priv
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
966 if (IS_ERR(priv
->reg_base
))
967 return PTR_ERR(priv
->reg_base
);
969 ret
= exynos5440_gpiolib_register(pdev
, priv
);
973 ret
= exynos5440_pinctrl_register(pdev
, priv
);
975 exynos5440_gpiolib_unregister(pdev
, priv
);
979 ret
= exynos5440_gpio_irq_init(pdev
, priv
);
981 dev_err(dev
, "failed to setup gpio interrupts\n");
985 platform_set_drvdata(pdev
, priv
);
986 dev_info(dev
, "EXYNOS5440 pinctrl driver registered\n");
990 static const struct of_device_id exynos5440_pinctrl_dt_match
[] = {
991 { .compatible
= "samsung,exynos5440-pinctrl" },
994 MODULE_DEVICE_TABLE(of
, exynos5440_pinctrl_dt_match
);
996 static struct platform_driver exynos5440_pinctrl_driver
= {
997 .probe
= exynos5440_pinctrl_probe
,
999 .name
= "exynos5440-pinctrl",
1000 .of_match_table
= exynos5440_pinctrl_dt_match
,
1004 static int __init
exynos5440_pinctrl_drv_register(void)
1006 return platform_driver_register(&exynos5440_pinctrl_driver
);
1008 postcore_initcall(exynos5440_pinctrl_drv_register
);
1010 static void __exit
exynos5440_pinctrl_drv_unregister(void)
1012 platform_driver_unregister(&exynos5440_pinctrl_driver
);
1014 module_exit(exynos5440_pinctrl_drv_unregister
);
1016 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1017 MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1018 MODULE_LICENSE("GPL v2");