?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: DCB: Validate DCB_ATTR_DCB_BUFFER argument
[linux/fpc-iii.git] / drivers / perf / arm-ccn.c
blob336948b41bd163a024e26c37ee9bd3966c74ac8e
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2014 ARM Limited
5 */
6
7 #include <linux/ctype.h>
8 #include <linux/hrtimer.h>
9 #include <linux/idr.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/perf_event.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17
18 #define CCN_NUM_XP_PORTS 2
19 #define CCN_NUM_VCS 4
20 #define CCN_NUM_REGIONS 256
21 #define CCN_REGION_SIZE 0x10000
22
23 #define CCN_ALL_OLY_ID 0xff00
24 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
25 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
26 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
27 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
28
29 #define CCN_MN_ERRINT_STATUS 0x0008
30 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
31 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
32 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
33 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
34 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
35 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
36 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
37 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
38 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
39 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
40 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
41 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
42 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
43
44 #define CCN_DT_ACTIVE_DSM 0x0000
45 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
46 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
47 #define CCN_DT_CTL 0x0028
48 #define CCN_DT_CTL__DT_EN (1 << 0)
49 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
50 #define CCN_DT_PMCCNTR 0x0140
51 #define CCN_DT_PMCCNTRSR 0x0190
52 #define CCN_DT_PMOVSR 0x0198
53 #define CCN_DT_PMOVSR_CLR 0x01a0
54 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
55 #define CCN_DT_PMCR 0x01a8
56 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
57 #define CCN_DT_PMCR__PMU_EN (1 << 0)
58 #define CCN_DT_PMSR 0x01b0
59 #define CCN_DT_PMSR_REQ 0x01b8
60 #define CCN_DT_PMSR_CLR 0x01c0
61
62 #define CCN_HNF_PMU_EVENT_SEL 0x0600
63 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
64 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
65
66 #define CCN_XP_DT_CONFIG 0x0300
67 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
68 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
69 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
70 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
71 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
72 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
73 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
74 #define CCN_XP_DT_INTERFACE_SEL 0x0308
75 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
76 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
77 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
78 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
79 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
80 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
81 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
82 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
83 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
84 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
85 #define CCN_XP_DT_CONTROL 0x0370
86 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
87 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
88 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
89 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
90 #define CCN_XP_PMU_EVENT_SEL 0x0600
91 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
92 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
93
94 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
95 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
96 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
97
98 #define CCN_RNI_PMU_EVENT_SEL 0x0600
99 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
100 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
101
102 #define CCN_TYPE_MN 0x01
103 #define CCN_TYPE_DT 0x02
104 #define CCN_TYPE_HNF 0x04
105 #define CCN_TYPE_HNI 0x05
106 #define CCN_TYPE_XP 0x08
107 #define CCN_TYPE_SBSX 0x0c
108 #define CCN_TYPE_SBAS 0x10
109 #define CCN_TYPE_RNI_1P 0x14
110 #define CCN_TYPE_RNI_2P 0x15
111 #define CCN_TYPE_RNI_3P 0x16
112 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
113 #define CCN_TYPE_RND_2P 0x19
114 #define CCN_TYPE_RND_3P 0x1a
115 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
116
117 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
118
119 #define CCN_NUM_PMU_EVENTS 4
120 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
121 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
122 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
123
124 #define CCN_NUM_PREDEFINED_MASKS 4
125 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
126 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
127 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
128 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
129
130 struct arm_ccn_component {
131 void __iomem *base;
132 u32 type;
133
134 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
135 union {
136 struct {
137 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
138 } xp;
139 };
140 };
141
142 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
143 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
144
145 struct arm_ccn_dt {
146 int id;
147 void __iomem *base;
148
149 spinlock_t config_lock;
150
151 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
152 struct {
153 struct arm_ccn_component *source;
154 struct perf_event *event;
155 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
156
157 struct {
158 u64 l, h;
159 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
160
161 struct hrtimer hrtimer;
162
163 unsigned int cpu;
164 struct hlist_node node;
165
166 struct pmu pmu;
167 };
168
169 struct arm_ccn {
170 struct device *dev;
171 void __iomem *base;
172 unsigned int irq;
173
174 unsigned sbas_present:1;
175 unsigned sbsx_present:1;
176
177 int num_nodes;
178 struct arm_ccn_component *node;
179
180 int num_xps;
181 struct arm_ccn_component *xp;
182
183 struct arm_ccn_dt dt;
184 int mn_id;
185 };
186
187 static int arm_ccn_node_to_xp(int node)
188 {
189 return node / CCN_NUM_XP_PORTS;
190 }
191
192 static int arm_ccn_node_to_xp_port(int node)
193 {
194 return node % CCN_NUM_XP_PORTS;
195 }
196
197
198 /*
199 * Bit shifts and masks in these defines must be kept in sync with
200 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
201 */
202 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
203 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
204 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
205 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
206 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
207 #define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
208 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
209 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
210 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
211
212 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
213 {
214 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
215 *config |= (node_xp << 0) | (type << 8) | (port << 24);
216 }
217
218 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
219 struct device_attribute *attr, char *buf)
220 {
221 struct dev_ext_attribute *ea = container_of(attr,
222 struct dev_ext_attribute, attr);
223
224 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
225 }
226
227 #define CCN_FORMAT_ATTR(_name, _config) \
228 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
229 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
230 NULL), _config }
231
232 static CCN_FORMAT_ATTR(node, "config:0-7");
233 static CCN_FORMAT_ATTR(xp, "config:0-7");
234 static CCN_FORMAT_ATTR(type, "config:8-15");
235 static CCN_FORMAT_ATTR(event, "config:16-23");
236 static CCN_FORMAT_ATTR(port, "config:24-25");
237 static CCN_FORMAT_ATTR(bus, "config:24-25");
238 static CCN_FORMAT_ATTR(vc, "config:26-28");
239 static CCN_FORMAT_ATTR(dir, "config:29-29");
240 static CCN_FORMAT_ATTR(mask, "config:30-33");
241 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
242 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
243
244 static struct attribute *arm_ccn_pmu_format_attrs[] = {
245 &arm_ccn_pmu_format_attr_node.attr.attr,
246 &arm_ccn_pmu_format_attr_xp.attr.attr,
247 &arm_ccn_pmu_format_attr_type.attr.attr,
248 &arm_ccn_pmu_format_attr_event.attr.attr,
249 &arm_ccn_pmu_format_attr_port.attr.attr,
250 &arm_ccn_pmu_format_attr_bus.attr.attr,
251 &arm_ccn_pmu_format_attr_vc.attr.attr,
252 &arm_ccn_pmu_format_attr_dir.attr.attr,
253 &arm_ccn_pmu_format_attr_mask.attr.attr,
254 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
255 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
256 NULL
257 };
258
259 static const struct attribute_group arm_ccn_pmu_format_attr_group = {
260 .name = "format",
261 .attrs = arm_ccn_pmu_format_attrs,
262 };
263
264
265 struct arm_ccn_pmu_event {
266 struct device_attribute attr;
267 u32 type;
268 u32 event;
269 int num_ports;
270 int num_vcs;
271 const char *def;
272 int mask;
273 };
274
275 #define CCN_EVENT_ATTR(_name) \
276 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
277
278 /*
279 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
280 * their ports in XP they are connected to. For the sake of usability they are
281 * explicitly defined here (and translated into a relevant watchpoint in
282 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
283 * knowledge of the flit format.
284 */
285
286 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
287 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
288 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
289 .def = _def, .mask = _mask, }
290
291 #define CCN_EVENT_HNI(_name, _def, _mask) { \
292 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
293 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
294 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
295
296 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
297 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
298 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
299 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
300
301 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
302 .type = CCN_TYPE_HNF, .event = _event, }
303
304 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
305 .type = CCN_TYPE_XP, .event = _event, \
306 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
307
308 /*
309 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
310 * on configuration. One of them is picked to represent the whole group,
311 * as they all share the same event types.
312 */
313 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
314 .type = CCN_TYPE_RNI_3P, .event = _event, }
315
316 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
317 .type = CCN_TYPE_SBAS, .event = _event, }
318
319 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
320 .type = CCN_TYPE_CYCLES }
321
322
323 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
324 struct device_attribute *attr, char *buf)
325 {
326 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
327 struct arm_ccn_pmu_event *event = container_of(attr,
328 struct arm_ccn_pmu_event, attr);
329 ssize_t res;
330
331 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
332 if (event->event)
333 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
334 event->event);
335 if (event->def)
336 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
337 event->def);
338 if (event->mask)
339 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
340 event->mask);
341
342 /* Arguments required by an event */
343 switch (event->type) {
344 case CCN_TYPE_CYCLES:
345 break;
346 case CCN_TYPE_XP:
347 res += snprintf(buf + res, PAGE_SIZE - res,
348 ",xp=?,vc=?");
349 if (event->event == CCN_EVENT_WATCHPOINT)
350 res += snprintf(buf + res, PAGE_SIZE - res,
351 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
352 else
353 res += snprintf(buf + res, PAGE_SIZE - res,
354 ",bus=?");
355
356 break;
357 case CCN_TYPE_MN:
358 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
359 break;
360 default:
361 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
362 break;
363 }
364
365 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
366
367 return res;
368 }
369
370 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
371 struct attribute *attr, int index)
372 {
373 struct device *dev = kobj_to_dev(kobj);
374 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
375 struct device_attribute *dev_attr = container_of(attr,
376 struct device_attribute, attr);
377 struct arm_ccn_pmu_event *event = container_of(dev_attr,
378 struct arm_ccn_pmu_event, attr);
379
380 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
381 return 0;
382 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
383 return 0;
384
385 return attr->mode;
386 }
387
388 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
389 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
390 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
391 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
392 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
393 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
394 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
395 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
396 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
397 CCN_IDX_MASK_ORDER),
398 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
399 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
400 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
401 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
402 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
403 CCN_IDX_MASK_ORDER),
404 CCN_EVENT_HNF(cache_miss, 0x1),
405 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
406 CCN_EVENT_HNF(cache_fill, 0x3),
407 CCN_EVENT_HNF(pocq_retry, 0x4),
408 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
409 CCN_EVENT_HNF(sf_hit, 0x6),
410 CCN_EVENT_HNF(sf_evictions, 0x7),
411 CCN_EVENT_HNF(snoops_sent, 0x8),
412 CCN_EVENT_HNF(snoops_broadcast, 0x9),
413 CCN_EVENT_HNF(l3_eviction, 0xa),
414 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
415 CCN_EVENT_HNF(mc_retries, 0xc),
416 CCN_EVENT_HNF(mc_reqs, 0xd),
417 CCN_EVENT_HNF(qos_hh_retry, 0xe),
418 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
419 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
420 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
421 CCN_EVENT_RNI(rxdat_flits, 0x4),
422 CCN_EVENT_RNI(txdat_flits, 0x5),
423 CCN_EVENT_RNI(txreq_flits, 0x6),
424 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
425 CCN_EVENT_RNI(rrt_full, 0x8),
426 CCN_EVENT_RNI(wrt_full, 0x9),
427 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
428 CCN_EVENT_XP(upload_starvation, 0x1),
429 CCN_EVENT_XP(download_starvation, 0x2),
430 CCN_EVENT_XP(respin, 0x3),
431 CCN_EVENT_XP(valid_flit, 0x4),
432 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
433 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
434 CCN_EVENT_SBAS(rxdat_flits, 0x4),
435 CCN_EVENT_SBAS(txdat_flits, 0x5),
436 CCN_EVENT_SBAS(txreq_flits, 0x6),
437 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
438 CCN_EVENT_SBAS(rrt_full, 0x8),
439 CCN_EVENT_SBAS(wrt_full, 0x9),
440 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
441 CCN_EVENT_CYCLES(cycles),
442 };
443
444 /* Populated in arm_ccn_init() */
445 static struct attribute
446 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
447
448 static const struct attribute_group arm_ccn_pmu_events_attr_group = {
449 .name = "events",
450 .is_visible = arm_ccn_pmu_events_is_visible,
451 .attrs = arm_ccn_pmu_events_attrs,
452 };
453
454
455 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
456 {
457 unsigned long i;
458
459 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
460 return NULL;
461 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
462
463 switch (name[1]) {
464 case 'l':
465 return &ccn->dt.cmp_mask[i].l;
466 case 'h':
467 return &ccn->dt.cmp_mask[i].h;
468 default:
469 return NULL;
470 }
471 }
472
473 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
474 struct device_attribute *attr, char *buf)
475 {
476 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
477 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
478
479 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
480 }
481
482 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
483 struct device_attribute *attr, const char *buf, size_t count)
484 {
485 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
486 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
487 int err = -EINVAL;
488
489 if (mask)
490 err = kstrtoull(buf, 0, mask);
491
492 return err ? err : count;
493 }
494
495 #define CCN_CMP_MASK_ATTR(_name) \
496 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
497 __ATTR(_name, S_IRUGO | S_IWUSR, \
498 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
499
500 #define CCN_CMP_MASK_ATTR_RO(_name) \
501 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
502 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
503
504 static CCN_CMP_MASK_ATTR(0l);
505 static CCN_CMP_MASK_ATTR(0h);
506 static CCN_CMP_MASK_ATTR(1l);
507 static CCN_CMP_MASK_ATTR(1h);
508 static CCN_CMP_MASK_ATTR(2l);
509 static CCN_CMP_MASK_ATTR(2h);
510 static CCN_CMP_MASK_ATTR(3l);
511 static CCN_CMP_MASK_ATTR(3h);
512 static CCN_CMP_MASK_ATTR(4l);
513 static CCN_CMP_MASK_ATTR(4h);
514 static CCN_CMP_MASK_ATTR(5l);
515 static CCN_CMP_MASK_ATTR(5h);
516 static CCN_CMP_MASK_ATTR(6l);
517 static CCN_CMP_MASK_ATTR(6h);
518 static CCN_CMP_MASK_ATTR(7l);
519 static CCN_CMP_MASK_ATTR(7h);
520 static CCN_CMP_MASK_ATTR_RO(8l);
521 static CCN_CMP_MASK_ATTR_RO(8h);
522 static CCN_CMP_MASK_ATTR_RO(9l);
523 static CCN_CMP_MASK_ATTR_RO(9h);
524 static CCN_CMP_MASK_ATTR_RO(al);
525 static CCN_CMP_MASK_ATTR_RO(ah);
526 static CCN_CMP_MASK_ATTR_RO(bl);
527 static CCN_CMP_MASK_ATTR_RO(bh);
528
529 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
530 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
531 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
532 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
533 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
534 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
535 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
536 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
537 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
538 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
539 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
540 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
541 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
542 NULL
543 };
544
545 static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
546 .name = "cmp_mask",
547 .attrs = arm_ccn_pmu_cmp_mask_attrs,
548 };
549
550 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
551 struct device_attribute *attr, char *buf)
552 {
553 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
554
555 return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));
556 }
557
558 static struct device_attribute arm_ccn_pmu_cpumask_attr =
559 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
560
561 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
562 &arm_ccn_pmu_cpumask_attr.attr,
563 NULL,
564 };
565
566 static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
567 .attrs = arm_ccn_pmu_cpumask_attrs,
568 };
569
570 /*
571 * Default poll period is 10ms, which is way over the top anyway,
572 * as in the worst case scenario (an event every cycle), with 1GHz
573 * clocked bus, the smallest, 32 bit counter will overflow in
574 * more than 4s.
575 */
576 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
577 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
578 S_IRUGO | S_IWUSR);
579
580 static ktime_t arm_ccn_pmu_timer_period(void)
581 {
582 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
583 }
584
585
586 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
587 &arm_ccn_pmu_events_attr_group,
588 &arm_ccn_pmu_format_attr_group,
589 &arm_ccn_pmu_cmp_mask_attr_group,
590 &arm_ccn_pmu_cpumask_attr_group,
591 NULL
592 };
593
594
595 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
596 {
597 int bit;
598
599 do {
600 bit = find_first_zero_bit(bitmap, size);
601 if (bit >= size)
602 return -EAGAIN;
603 } while (test_and_set_bit(bit, bitmap));
604
605 return bit;
606 }
607
608 /* All RN-I and RN-D nodes have identical PMUs */
609 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
610 {
611 if (a == b)
612 return 1;
613
614 switch (a) {
615 case CCN_TYPE_RNI_1P:
616 case CCN_TYPE_RNI_2P:
617 case CCN_TYPE_RNI_3P:
618 case CCN_TYPE_RND_1P:
619 case CCN_TYPE_RND_2P:
620 case CCN_TYPE_RND_3P:
621 switch (b) {
622 case CCN_TYPE_RNI_1P:
623 case CCN_TYPE_RNI_2P:
624 case CCN_TYPE_RNI_3P:
625 case CCN_TYPE_RND_1P:
626 case CCN_TYPE_RND_2P:
627 case CCN_TYPE_RND_3P:
628 return 1;
629 }
630 break;
631 }
632
633 return 0;
634 }
635
636 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
637 {
638 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
639 struct hw_perf_event *hw = &event->hw;
640 u32 node_xp, type, event_id;
641 struct arm_ccn_component *source;
642 int bit;
643
644 node_xp = CCN_CONFIG_NODE(event->attr.config);
645 type = CCN_CONFIG_TYPE(event->attr.config);
646 event_id = CCN_CONFIG_EVENT(event->attr.config);
647
648 /* Allocate the cycle counter */
649 if (type == CCN_TYPE_CYCLES) {
650 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
651 ccn->dt.pmu_counters_mask))
652 return -EAGAIN;
653
654 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
655 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
656
657 return 0;
658 }
659
660 /* Allocate an event counter */
661 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
662 CCN_NUM_PMU_EVENT_COUNTERS);
663 if (hw->idx < 0) {
664 dev_dbg(ccn->dev, "No more counters available!\n");
665 return -EAGAIN;
666 }
667
668 if (type == CCN_TYPE_XP)
669 source = &ccn->xp[node_xp];
670 else
671 source = &ccn->node[node_xp];
672 ccn->dt.pmu_counters[hw->idx].source = source;
673
674 /* Allocate an event source or a watchpoint */
675 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
676 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
677 CCN_NUM_XP_WATCHPOINTS);
678 else
679 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
680 CCN_NUM_PMU_EVENTS);
681 if (bit < 0) {
682 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
683 node_xp);
684 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
685 return -EAGAIN;
686 }
687 hw->config_base = bit;
688
689 ccn->dt.pmu_counters[hw->idx].event = event;
690
691 return 0;
692 }
693
694 static void arm_ccn_pmu_event_release(struct perf_event *event)
695 {
696 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
697 struct hw_perf_event *hw = &event->hw;
698
699 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
700 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
701 } else {
702 struct arm_ccn_component *source =
703 ccn->dt.pmu_counters[hw->idx].source;
704
705 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
706 CCN_CONFIG_EVENT(event->attr.config) ==
707 CCN_EVENT_WATCHPOINT)
708 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
709 else
710 clear_bit(hw->config_base, source->pmu_events_mask);
711 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
712 }
713
714 ccn->dt.pmu_counters[hw->idx].source = NULL;
715 ccn->dt.pmu_counters[hw->idx].event = NULL;
716 }
717
718 static int arm_ccn_pmu_event_init(struct perf_event *event)
719 {
720 struct arm_ccn *ccn;
721 struct hw_perf_event *hw = &event->hw;
722 u32 node_xp, type, event_id;
723 int valid;
724 int i;
725 struct perf_event *sibling;
726
727 if (event->attr.type != event->pmu->type)
728 return -ENOENT;
729
730 ccn = pmu_to_arm_ccn(event->pmu);
731
732 if (hw->sample_period) {
733 dev_dbg(ccn->dev, "Sampling not supported!\n");
734 return -EOPNOTSUPP;
735 }
736
737 if (has_branch_stack(event)) {
738 dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
739 return -EINVAL;
740 }
741
742 if (event->cpu < 0) {
743 dev_dbg(ccn->dev, "Can't provide per-task data!\n");
744 return -EOPNOTSUPP;
745 }
746 /*
747 * Many perf core operations (eg. events rotation) operate on a
748 * single CPU context. This is obvious for CPU PMUs, where one
749 * expects the same sets of events being observed on all CPUs,
750 * but can lead to issues for off-core PMUs, like CCN, where each
751 * event could be theoretically assigned to a different CPU. To
752 * mitigate this, we enforce CPU assignment to one, selected
753 * processor (the one described in the "cpumask" attribute).
754 */
755 event->cpu = ccn->dt.cpu;
756
757 node_xp = CCN_CONFIG_NODE(event->attr.config);
758 type = CCN_CONFIG_TYPE(event->attr.config);
759 event_id = CCN_CONFIG_EVENT(event->attr.config);
760
761 /* Validate node/xp vs topology */
762 switch (type) {
763 case CCN_TYPE_MN:
764 if (node_xp != ccn->mn_id) {
765 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
766 return -EINVAL;
767 }
768 break;
769 case CCN_TYPE_XP:
770 if (node_xp >= ccn->num_xps) {
771 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
772 return -EINVAL;
773 }
774 break;
775 case CCN_TYPE_CYCLES:
776 break;
777 default:
778 if (node_xp >= ccn->num_nodes) {
779 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
780 return -EINVAL;
781 }
782 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
783 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
784 type, node_xp);
785 return -EINVAL;
786 }
787 break;
788 }
789
790 /* Validate event ID vs available for the type */
791 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
792 i++) {
793 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
794 u32 port = CCN_CONFIG_PORT(event->attr.config);
795 u32 vc = CCN_CONFIG_VC(event->attr.config);
796
797 if (!arm_ccn_pmu_type_eq(type, e->type))
798 continue;
799 if (event_id != e->event)
800 continue;
801 if (e->num_ports && port >= e->num_ports) {
802 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
803 port, node_xp);
804 return -EINVAL;
805 }
806 if (e->num_vcs && vc >= e->num_vcs) {
807 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
808 vc, node_xp);
809 return -EINVAL;
810 }
811 valid = 1;
812 }
813 if (!valid) {
814 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
815 event_id, node_xp);
816 return -EINVAL;
817 }
818
819 /* Watchpoint-based event for a node is actually set on XP */
820 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
821 u32 port;
822
823 type = CCN_TYPE_XP;
824 port = arm_ccn_node_to_xp_port(node_xp);
825 node_xp = arm_ccn_node_to_xp(node_xp);
826
827 arm_ccn_pmu_config_set(&event->attr.config,
828 node_xp, type, port);
829 }
830
831 /*
832 * We must NOT create groups containing mixed PMUs, although software
833 * events are acceptable (for example to create a CCN group
834 * periodically read when a hrtimer aka cpu-clock leader triggers).
835 */
836 if (event->group_leader->pmu != event->pmu &&
837 !is_software_event(event->group_leader))
838 return -EINVAL;
839
840 for_each_sibling_event(sibling, event->group_leader) {
841 if (sibling->pmu != event->pmu &&
842 !is_software_event(sibling))
843 return -EINVAL;
844 }
845
846 return 0;
847 }
848
849 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
850 {
851 u64 res;
852
853 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
854 #ifdef readq
855 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
856 #else
857 /* 40 bit counter, can do snapshot and read in two parts */
858 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
859 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
860 ;
861 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
862 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
863 res <<= 32;
864 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
865 #endif
866 } else {
867 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
868 }
869
870 return res;
871 }
872
873 static void arm_ccn_pmu_event_update(struct perf_event *event)
874 {
875 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
876 struct hw_perf_event *hw = &event->hw;
877 u64 prev_count, new_count, mask;
878
879 do {
880 prev_count = local64_read(&hw->prev_count);
881 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
882 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
883
884 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
885
886 local64_add((new_count - prev_count) & mask, &event->count);
887 }
888
889 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
890 {
891 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
892 struct hw_perf_event *hw = &event->hw;
893 struct arm_ccn_component *xp;
894 u32 val, dt_cfg;
895
896 /* Nothing to do for cycle counter */
897 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
898 return;
899
900 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
901 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
902 else
903 xp = &ccn->xp[arm_ccn_node_to_xp(
904 CCN_CONFIG_NODE(event->attr.config))];
905
906 if (enable)
907 dt_cfg = hw->event_base;
908 else
909 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
910
911 spin_lock(&ccn->dt.config_lock);
912
913 val = readl(xp->base + CCN_XP_DT_CONFIG);
914 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
915 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
916 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
917 writel(val, xp->base + CCN_XP_DT_CONFIG);
918
919 spin_unlock(&ccn->dt.config_lock);
920 }
921
922 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
923 {
924 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
925 struct hw_perf_event *hw = &event->hw;
926
927 local64_set(&event->hw.prev_count,
928 arm_ccn_pmu_read_counter(ccn, hw->idx));
929 hw->state = 0;
930
931 /* Set the DT bus input, engaging the counter */
932 arm_ccn_pmu_xp_dt_config(event, 1);
933 }
934
935 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
936 {
937 struct hw_perf_event *hw = &event->hw;
938
939 /* Disable counting, setting the DT bus to pass-through mode */
940 arm_ccn_pmu_xp_dt_config(event, 0);
941
942 if (flags & PERF_EF_UPDATE)
943 arm_ccn_pmu_event_update(event);
944
945 hw->state |= PERF_HES_STOPPED;
946 }
947
948 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
949 {
950 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
951 struct hw_perf_event *hw = &event->hw;
952 struct arm_ccn_component *source =
953 ccn->dt.pmu_counters[hw->idx].source;
954 unsigned long wp = hw->config_base;
955 u32 val;
956 u64 cmp_l = event->attr.config1;
957 u64 cmp_h = event->attr.config2;
958 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
959 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
960
961 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
962
963 /* Direction (RX/TX), device (port) & virtual channel */
964 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
965 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
966 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
967 val |= CCN_CONFIG_DIR(event->attr.config) <<
968 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
969 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
970 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
971 val |= CCN_CONFIG_PORT(event->attr.config) <<
972 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
973 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
974 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
975 val |= CCN_CONFIG_VC(event->attr.config) <<
976 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
977 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
978
979 /* Comparison values */
980 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
981 writel((cmp_l >> 32) & 0x7fffffff,
982 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
983 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
984 writel((cmp_h >> 32) & 0x0fffffff,
985 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
986
987 /* Mask */
988 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
989 writel((mask_l >> 32) & 0x7fffffff,
990 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
991 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
992 writel((mask_h >> 32) & 0x0fffffff,
993 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
994 }
995
996 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
997 {
998 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
999 struct hw_perf_event *hw = &event->hw;
1000 struct arm_ccn_component *source =
1001 ccn->dt.pmu_counters[hw->idx].source;
1002 u32 val, id;
1003
1004 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1005
1006 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1007 (CCN_CONFIG_BUS(event->attr.config) << 3) |
1008 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1009
1010 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1011 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1012 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1013 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1014 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1015 }
1016
1017 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1018 {
1019 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1020 struct hw_perf_event *hw = &event->hw;
1021 struct arm_ccn_component *source =
1022 ccn->dt.pmu_counters[hw->idx].source;
1023 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1024 u32 val, port;
1025
1026 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1027 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1028 hw->config_base);
1029
1030 /* These *_event_sel regs should be identical, but let's make sure... */
1031 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1032 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1033 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1034 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1035 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1036 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1037 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1038 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1039 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1040 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1041 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1042 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1043 return;
1044
1045 /* Set the event id for the pre-allocated counter */
1046 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1047 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1048 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1049 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1050 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1051 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1052 }
1053
1054 static void arm_ccn_pmu_event_config(struct perf_event *event)
1055 {
1056 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1057 struct hw_perf_event *hw = &event->hw;
1058 u32 xp, offset, val;
1059
1060 /* Cycle counter requires no setup */
1061 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1062 return;
1063
1064 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1065 xp = CCN_CONFIG_XP(event->attr.config);
1066 else
1067 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1068
1069 spin_lock(&ccn->dt.config_lock);
1070
1071 /* Set the DT bus "distance" register */
1072 offset = (hw->idx / 4) * 4;
1073 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1074 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1075 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1076 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1077 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1078
1079 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1080 if (CCN_CONFIG_EVENT(event->attr.config) ==
1081 CCN_EVENT_WATCHPOINT)
1082 arm_ccn_pmu_xp_watchpoint_config(event);
1083 else
1084 arm_ccn_pmu_xp_event_config(event);
1085 } else {
1086 arm_ccn_pmu_node_event_config(event);
1087 }
1088
1089 spin_unlock(&ccn->dt.config_lock);
1090 }
1091
1092 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1093 {
1094 return bitmap_weight(ccn->dt.pmu_counters_mask,
1095 CCN_NUM_PMU_EVENT_COUNTERS + 1);
1096 }
1097
1098 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1099 {
1100 int err;
1101 struct hw_perf_event *hw = &event->hw;
1102 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1103
1104 err = arm_ccn_pmu_event_alloc(event);
1105 if (err)
1106 return err;
1107
1108 /*
1109 * Pin the timer, so that the overflows are handled by the chosen
1110 * event->cpu (this is the same one as presented in "cpumask"
1111 * attribute).
1112 */
1113 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1114 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1115 HRTIMER_MODE_REL_PINNED);
1116
1117 arm_ccn_pmu_event_config(event);
1118
1119 hw->state = PERF_HES_STOPPED;
1120
1121 if (flags & PERF_EF_START)
1122 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1123
1124 return 0;
1125 }
1126
1127 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1128 {
1129 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1130
1131 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1132
1133 arm_ccn_pmu_event_release(event);
1134
1135 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1136 hrtimer_cancel(&ccn->dt.hrtimer);
1137 }
1138
1139 static void arm_ccn_pmu_event_read(struct perf_event *event)
1140 {
1141 arm_ccn_pmu_event_update(event);
1142 }
1143
1144 static void arm_ccn_pmu_enable(struct pmu *pmu)
1145 {
1146 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1147
1148 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1149 val |= CCN_DT_PMCR__PMU_EN;
1150 writel(val, ccn->dt.base + CCN_DT_PMCR);
1151 }
1152
1153 static void arm_ccn_pmu_disable(struct pmu *pmu)
1154 {
1155 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1156
1157 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1158 val &= ~CCN_DT_PMCR__PMU_EN;
1159 writel(val, ccn->dt.base + CCN_DT_PMCR);
1160 }
1161
1162 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1163 {
1164 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1165 int idx;
1166
1167 if (!pmovsr)
1168 return IRQ_NONE;
1169
1170 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1171
1172 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1173
1174 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1175 struct perf_event *event = dt->pmu_counters[idx].event;
1176 int overflowed = pmovsr & BIT(idx);
1177
1178 WARN_ON_ONCE(overflowed && !event &&
1179 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1180
1181 if (!event || !overflowed)
1182 continue;
1183
1184 arm_ccn_pmu_event_update(event);
1185 }
1186
1187 return IRQ_HANDLED;
1188 }
1189
1190 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1191 {
1192 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1193 hrtimer);
1194 unsigned long flags;
1195
1196 local_irq_save(flags);
1197 arm_ccn_pmu_overflow_handler(dt);
1198 local_irq_restore(flags);
1199
1200 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1201 return HRTIMER_RESTART;
1202 }
1203
1204
1205 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1206 {
1207 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1208 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1209 unsigned int target;
1210
1211 if (cpu != dt->cpu)
1212 return 0;
1213 target = cpumask_any_but(cpu_online_mask, cpu);
1214 if (target >= nr_cpu_ids)
1215 return 0;
1216 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1217 dt->cpu = target;
1218 if (ccn->irq)
1219 WARN_ON(irq_set_affinity_hint(ccn->irq, cpumask_of(dt->cpu)));
1220 return 0;
1221 }
1222
1223 static DEFINE_IDA(arm_ccn_pmu_ida);
1224
1225 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1226 {
1227 int i;
1228 char *name;
1229 int err;
1230
1231 /* Initialize DT subsystem */
1232 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1233 spin_lock_init(&ccn->dt.config_lock);
1234 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1235 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1236 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1237 ccn->dt.base + CCN_DT_PMCR);
1238 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1239 for (i = 0; i < ccn->num_xps; i++) {
1240 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1241 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1242 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1243 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1244 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1245 CCN_XP_DT_CONTROL__DT_ENABLE,
1246 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1247 }
1248 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1249 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1250 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1251 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1252 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1253 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1254 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1255 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1256
1257 /* Get a convenient /sys/event_source/devices/ name */
1258 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1259 if (ccn->dt.id == 0) {
1260 name = "ccn";
1261 } else {
1262 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
1263 ccn->dt.id);
1264 if (!name) {
1265 err = -ENOMEM;
1266 goto error_choose_name;
1267 }
1268 }
1269
1270 /* Perf driver registration */
1271 ccn->dt.pmu = (struct pmu) {
1272 .module = THIS_MODULE,
1273 .attr_groups = arm_ccn_pmu_attr_groups,
1274 .task_ctx_nr = perf_invalid_context,
1275 .event_init = arm_ccn_pmu_event_init,
1276 .add = arm_ccn_pmu_event_add,
1277 .del = arm_ccn_pmu_event_del,
1278 .start = arm_ccn_pmu_event_start,
1279 .stop = arm_ccn_pmu_event_stop,
1280 .read = arm_ccn_pmu_event_read,
1281 .pmu_enable = arm_ccn_pmu_enable,
1282 .pmu_disable = arm_ccn_pmu_disable,
1283 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
1284 };
1285
1286 /* No overflow interrupt? Have to use a timer instead. */
1287 if (!ccn->irq) {
1288 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1289 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1290 HRTIMER_MODE_REL);
1291 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1292 }
1293
1294 /* Pick one CPU which we will use to collect data from CCN... */
1295 ccn->dt.cpu = raw_smp_processor_id();
1296
1297 /* Also make sure that the overflow interrupt is handled by this CPU */
1298 if (ccn->irq) {
1299 err = irq_set_affinity_hint(ccn->irq, cpumask_of(ccn->dt.cpu));
1300 if (err) {
1301 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1302 goto error_set_affinity;
1303 }
1304 }
1305
1306 cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1307 &ccn->dt.node);
1308
1309 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1310 if (err)
1311 goto error_pmu_register;
1312
1313 return 0;
1314
1315 error_pmu_register:
1316 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1317 &ccn->dt.node);
1318 error_set_affinity:
1319 error_choose_name:
1320 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1321 for (i = 0; i < ccn->num_xps; i++)
1322 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1323 writel(0, ccn->dt.base + CCN_DT_PMCR);
1324 return err;
1325 }
1326
1327 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1328 {
1329 int i;
1330
1331 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1332 &ccn->dt.node);
1333 if (ccn->irq)
1334 irq_set_affinity_hint(ccn->irq, NULL);
1335 for (i = 0; i < ccn->num_xps; i++)
1336 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1337 writel(0, ccn->dt.base + CCN_DT_PMCR);
1338 perf_pmu_unregister(&ccn->dt.pmu);
1339 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1340 }
1341
1342 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1343 int (*callback)(struct arm_ccn *ccn, int region,
1344 void __iomem *base, u32 type, u32 id))
1345 {
1346 int region;
1347
1348 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1349 u32 val, type, id;
1350 void __iomem *base;
1351 int err;
1352
1353 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1354 4 * (region / 32));
1355 if (!(val & (1 << (region % 32))))
1356 continue;
1357
1358 base = ccn->base + region * CCN_REGION_SIZE;
1359 val = readl(base + CCN_ALL_OLY_ID);
1360 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1361 CCN_ALL_OLY_ID__OLY_ID__MASK;
1362 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1363 CCN_ALL_OLY_ID__NODE_ID__MASK;
1364
1365 err = callback(ccn, region, base, type, id);
1366 if (err)
1367 return err;
1368 }
1369
1370 return 0;
1371 }
1372
1373 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1374 void __iomem *base, u32 type, u32 id)
1375 {
1376
1377 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1378 ccn->num_xps = id + 1;
1379 else if (id >= ccn->num_nodes)
1380 ccn->num_nodes = id + 1;
1381
1382 return 0;
1383 }
1384
1385 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1386 void __iomem *base, u32 type, u32 id)
1387 {
1388 struct arm_ccn_component *component;
1389
1390 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1391
1392 switch (type) {
1393 case CCN_TYPE_MN:
1394 ccn->mn_id = id;
1395 return 0;
1396 case CCN_TYPE_DT:
1397 return 0;
1398 case CCN_TYPE_XP:
1399 component = &ccn->xp[id];
1400 break;
1401 case CCN_TYPE_SBSX:
1402 ccn->sbsx_present = 1;
1403 component = &ccn->node[id];
1404 break;
1405 case CCN_TYPE_SBAS:
1406 ccn->sbas_present = 1;
1407 /* Fall-through */
1408 default:
1409 component = &ccn->node[id];
1410 break;
1411 }
1412
1413 component->base = base;
1414 component->type = type;
1415
1416 return 0;
1417 }
1418
1419
1420 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1421 const u32 *err_sig_val)
1422 {
1423 /* This should be really handled by firmware... */
1424 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1425 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1426 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1427 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1428 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1429 ccn->base + CCN_MN_ERRINT_STATUS);
1430
1431 return IRQ_HANDLED;
1432 }
1433
1434
1435 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1436 {
1437 irqreturn_t res = IRQ_NONE;
1438 struct arm_ccn *ccn = dev_id;
1439 u32 err_sig_val[6];
1440 u32 err_or;
1441 int i;
1442
1443 /* PMU overflow is a special case */
1444 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1445 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1446 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1447 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1448 }
1449
1450 /* Have to read all err_sig_vals to clear them */
1451 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1452 err_sig_val[i] = readl(ccn->base +
1453 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1454 err_or |= err_sig_val[i];
1455 }
1456 if (err_or)
1457 res |= arm_ccn_error_handler(ccn, err_sig_val);
1458
1459 if (res != IRQ_NONE)
1460 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1461 ccn->base + CCN_MN_ERRINT_STATUS);
1462
1463 return res;
1464 }
1465
1466
1467 static int arm_ccn_probe(struct platform_device *pdev)
1468 {
1469 struct arm_ccn *ccn;
1470 struct resource *res;
1471 unsigned int irq;
1472 int err;
1473
1474 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1475 if (!ccn)
1476 return -ENOMEM;
1477 ccn->dev = &pdev->dev;
1478 platform_set_drvdata(pdev, ccn);
1479
1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481 ccn->base = devm_ioremap_resource(ccn->dev, res);
1482 if (IS_ERR(ccn->base))
1483 return PTR_ERR(ccn->base);
1484
1485 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1486 if (!res)
1487 return -EINVAL;
1488 irq = res->start;
1489
1490 /* Check if we can use the interrupt */
1491 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1492 ccn->base + CCN_MN_ERRINT_STATUS);
1493 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1494 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1495 /* Can set 'disable' bits, so can acknowledge interrupts */
1496 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1497 ccn->base + CCN_MN_ERRINT_STATUS);
1498 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1499 IRQF_NOBALANCING | IRQF_NO_THREAD,
1500 dev_name(ccn->dev), ccn);
1501 if (err)
1502 return err;
1503
1504 ccn->irq = irq;
1505 }
1506
1507
1508 /* Build topology */
1509
1510 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1511 if (err)
1512 return err;
1513
1514 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
1515 GFP_KERNEL);
1516 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
1517 GFP_KERNEL);
1518 if (!ccn->node || !ccn->xp)
1519 return -ENOMEM;
1520
1521 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1522 if (err)
1523 return err;
1524
1525 return arm_ccn_pmu_init(ccn);
1526 }
1527
1528 static int arm_ccn_remove(struct platform_device *pdev)
1529 {
1530 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1531
1532 arm_ccn_pmu_cleanup(ccn);
1533
1534 return 0;
1535 }
1536
1537 static const struct of_device_id arm_ccn_match[] = {
1538 { .compatible = "arm,ccn-502", },
1539 { .compatible = "arm,ccn-504", },
1540 {},
1541 };
1542 MODULE_DEVICE_TABLE(of, arm_ccn_match);
1543
1544 static struct platform_driver arm_ccn_driver = {
1545 .driver = {
1546 .name = "arm-ccn",
1547 .of_match_table = arm_ccn_match,
1548 .suppress_bind_attrs = true,
1549 },
1550 .probe = arm_ccn_probe,
1551 .remove = arm_ccn_remove,
1552 };
1553
1554 static int __init arm_ccn_init(void)
1555 {
1556 int i, ret;
1557
1558 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1559 "perf/arm/ccn:online", NULL,
1560 arm_ccn_pmu_offline_cpu);
1561 if (ret)
1562 return ret;
1563
1564 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1565 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1566
1567 ret = platform_driver_register(&arm_ccn_driver);
1568 if (ret)
1569 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1570 return ret;
1571 }
1572
1573 static void __exit arm_ccn_exit(void)
1574 {
1575 platform_driver_unregister(&arm_ccn_driver);
1576 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1577 }
1578
1579 module_init(arm_ccn_init);
1580 module_exit(arm_ccn_exit);
1581
1582 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1583 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support