drivers/usb/dwc3/dwc3-meson-g12a.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * USB Glue for Amlogic G12A SoCs
   4  *
   5  * Copyright (c) 2019 BayLibre, SAS
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 /*
  10  * The USB is organized with a glue around the DWC3 Controller IP as :
  11  * - Control registers for each USB2 Ports
  12  * - Control registers for the USB PHY layer
  13  * - SuperSpeed PHY can be enabled only if port is used
  14  * - Dynamic OTG switching with ID change interrupt
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/clk.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <linux/bitfield.h>
  26 #include <linux/bitops.h>
  27 #include <linux/reset.h>
  28 #include <linux/phy/phy.h>
  29 #include <linux/usb/otg.h>
  30 #include <linux/usb/role.h>
  31 #include <linux/regulator/consumer.h>
  32
  33 /* USB2 Ports Control Registers */
  34
  35 #define U2P_REG_SIZE                                            0x20
  36
  37 #define U2P_R0                                                  0x0
  38         #define U2P_R0_HOST_DEVICE                              BIT(0)
  39         #define U2P_R0_POWER_OK                                 BIT(1)
  40         #define U2P_R0_HAST_MODE                                BIT(2)
  41         #define U2P_R0_POWER_ON_RESET                           BIT(3)
  42         #define U2P_R0_ID_PULLUP                                BIT(4)
  43         #define U2P_R0_DRV_VBUS                                 BIT(5)
  44
  45 #define U2P_R1                                                  0x4
  46         #define U2P_R1_PHY_READY                                BIT(0)
  47         #define U2P_R1_ID_DIG                                   BIT(1)
  48         #define U2P_R1_OTG_SESSION_VALID                        BIT(2)
  49         #define U2P_R1_VBUS_VALID                               BIT(3)
  50
  51 /* USB Glue Control Registers */
  52
  53 #define USB_R0                                                  0x80
  54         #define USB_R0_P30_LANE0_TX2RX_LOOPBACK                 BIT(17)
  55         #define USB_R0_P30_LANE0_EXT_PCLK_REQ                   BIT(18)
  56         #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK             GENMASK(28, 19)
  57         #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK               GENMASK(30, 29)
  58         #define USB_R0_U2D_ACT                                  BIT(31)
  59
  60 #define USB_R1                                                  0x84
  61         #define USB_R1_U3H_BIGENDIAN_GS                         BIT(0)
  62         #define USB_R1_U3H_PME_ENABLE                           BIT(1)
  63         #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK            GENMASK(4, 2)
  64         #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK            GENMASK(9, 7)
  65         #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK            GENMASK(13, 12)
  66         #define USB_R1_U3H_HOST_U3_PORT_DISABLE                 BIT(16)
  67         #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT      BIT(17)
  68         #define USB_R1_U3H_HOST_MSI_ENABLE                      BIT(18)
  69         #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK                 GENMASK(24, 19)
  70         #define USB_R1_P30_PCS_TX_SWING_FULL_MASK               GENMASK(31, 25)
  71
  72 #define USB_R2                                                  0x88
  73         #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK             GENMASK(25, 20)
  74         #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK               GENMASK(31, 26)
  75
  76 #define USB_R3                                                  0x8c
  77         #define USB_R3_P30_SSC_ENABLE                           BIT(0)
  78         #define USB_R3_P30_SSC_RANGE_MASK                       GENMASK(3, 1)
  79         #define USB_R3_P30_SSC_REF_CLK_SEL_MASK                 GENMASK(12, 4)
  80         #define USB_R3_P30_REF_SSP_EN                           BIT(13)
  81
  82 #define USB_R4                                                  0x90
  83         #define USB_R4_P21_PORT_RESET_0                         BIT(0)
  84         #define USB_R4_P21_SLEEP_M0                             BIT(1)
  85         #define USB_R4_MEM_PD_MASK                              GENMASK(3, 2)
  86         #define USB_R4_P21_ONLY                                 BIT(4)
  87
  88 #define USB_R5                                                  0x94
  89         #define USB_R5_ID_DIG_SYNC                              BIT(0)
  90         #define USB_R5_ID_DIG_REG                               BIT(1)
  91         #define USB_R5_ID_DIG_CFG_MASK                          GENMASK(3, 2)
  92         #define USB_R5_ID_DIG_EN_0                              BIT(4)
  93         #define USB_R5_ID_DIG_EN_1                              BIT(5)
  94         #define USB_R5_ID_DIG_CURR                              BIT(6)
  95         #define USB_R5_ID_DIG_IRQ                               BIT(7)
  96         #define USB_R5_ID_DIG_TH_MASK                           GENMASK(15, 8)
  97         #define USB_R5_ID_DIG_CNT_MASK                          GENMASK(23, 16)
  98
  99 enum {
 100         USB2_HOST_PHY = 0,
 101         USB2_OTG_PHY,
 102         USB3_HOST_PHY,
 103         PHY_COUNT,
 104 };
 105
 106 static const char *phy_names[PHY_COUNT] = {
 107         "usb2-phy0", "usb2-phy1", "usb3-phy0",
 108 };
 109
 110 struct dwc3_meson_g12a {
 111         struct device           *dev;
 112         struct regmap           *regmap;
 113         struct clk              *clk;
 114         struct reset_control    *reset;
 115         struct phy              *phys[PHY_COUNT];
 116         enum usb_dr_mode        otg_mode;
 117         enum phy_mode           otg_phy_mode;
 118         unsigned int            usb2_ports;
 119         unsigned int            usb3_ports;
 120         struct regulator        *vbus;
 121         struct usb_role_switch_desc switch_desc;
 122         struct usb_role_switch  *role_switch;
 123 };
 124
 125 static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
 126                                           int i, enum phy_mode mode)
 127 {
 128         if (mode == PHY_MODE_USB_HOST)
 129                 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
 130                                 U2P_R0_HOST_DEVICE,
 131                                 U2P_R0_HOST_DEVICE);
 132         else
 133                 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
 134                                 U2P_R0_HOST_DEVICE, 0);
 135 }
 136
 137 static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
 138 {
 139         int i;
 140
 141         if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
 142                 priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
 143         else
 144                 priv->otg_phy_mode = PHY_MODE_USB_HOST;
 145
 146         for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
 147                 if (!priv->phys[i])
 148                         continue;
 149
 150                 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
 151                                    U2P_R0_POWER_ON_RESET,
 152                                    U2P_R0_POWER_ON_RESET);
 153
 154                 if (i == USB2_OTG_PHY) {
 155                         regmap_update_bits(priv->regmap,
 156                                 U2P_R0 + (U2P_REG_SIZE * i),
 157                                 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
 158                                 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
 159
 160                         dwc3_meson_g12a_usb2_set_mode(priv, i,
 161                                                       priv->otg_phy_mode);
 162                 } else
 163                         dwc3_meson_g12a_usb2_set_mode(priv, i,
 164                                                       PHY_MODE_USB_HOST);
 165
 166                 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
 167                                    U2P_R0_POWER_ON_RESET, 0);
 168         }
 169
 170         return 0;
 171 }
 172
 173 static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
 174 {
 175         regmap_update_bits(priv->regmap, USB_R3,
 176                         USB_R3_P30_SSC_RANGE_MASK |
 177                         USB_R3_P30_REF_SSP_EN,
 178                         USB_R3_P30_SSC_ENABLE |
 179                         FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
 180                         USB_R3_P30_REF_SSP_EN);
 181         udelay(2);
 182
 183         regmap_update_bits(priv->regmap, USB_R2,
 184                         USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
 185                         FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
 186
 187         regmap_update_bits(priv->regmap, USB_R2,
 188                         USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
 189                         FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
 190
 191         udelay(2);
 192
 193         regmap_update_bits(priv->regmap, USB_R1,
 194                         USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
 195                         USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
 196
 197         regmap_update_bits(priv->regmap, USB_R1,
 198                         USB_R1_P30_PCS_TX_SWING_FULL_MASK,
 199                         FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
 200 }
 201
 202 static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
 203 {
 204         if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) {
 205                 regmap_update_bits(priv->regmap, USB_R0,
 206                                 USB_R0_U2D_ACT, USB_R0_U2D_ACT);
 207                 regmap_update_bits(priv->regmap, USB_R0,
 208                                 USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
 209                 regmap_update_bits(priv->regmap, USB_R4,
 210                                 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
 211         } else {
 212                 regmap_update_bits(priv->regmap, USB_R0,
 213                                 USB_R0_U2D_ACT, 0);
 214                 regmap_update_bits(priv->regmap, USB_R4,
 215                                 USB_R4_P21_SLEEP_M0, 0);
 216         }
 217 }
 218
 219 static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
 220 {
 221         int ret;
 222
 223         ret = dwc3_meson_g12a_usb2_init(priv);
 224         if (ret)
 225                 return ret;
 226
 227         regmap_update_bits(priv->regmap, USB_R1,
 228                         USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
 229                         FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
 230
 231         regmap_update_bits(priv->regmap, USB_R5,
 232                         USB_R5_ID_DIG_EN_0,
 233                         USB_R5_ID_DIG_EN_0);
 234         regmap_update_bits(priv->regmap, USB_R5,
 235                         USB_R5_ID_DIG_EN_1,
 236                         USB_R5_ID_DIG_EN_1);
 237         regmap_update_bits(priv->regmap, USB_R5,
 238                         USB_R5_ID_DIG_TH_MASK,
 239                         FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
 240
 241         /* If we have an actual SuperSpeed port, initialize it */
 242         if (priv->usb3_ports)
 243                 dwc3_meson_g12a_usb3_init(priv);
 244
 245         dwc3_meson_g12a_usb_otg_apply_mode(priv);
 246
 247         return 0;
 248 }
 249
 250 static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = {
 251         .reg_bits = 8,
 252         .val_bits = 32,
 253         .reg_stride = 4,
 254         .max_register = USB_R5,
 255 };
 256
 257 static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
 258 {
 259         int i;
 260
 261         for (i = 0 ; i < PHY_COUNT ; ++i) {
 262                 priv->phys[i] = devm_phy_optional_get(priv->dev, phy_names[i]);
 263                 if (!priv->phys[i])
 264                         continue;
 265
 266                 if (IS_ERR(priv->phys[i]))
 267                         return PTR_ERR(priv->phys[i]);
 268
 269                 if (i == USB3_HOST_PHY)
 270                         priv->usb3_ports++;
 271                 else
 272                         priv->usb2_ports++;
 273         }
 274
 275         dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports);
 276         dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports);
 277
 278         return 0;
 279 }
 280
 281 static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv)
 282 {
 283         u32 reg;
 284
 285         regmap_read(priv->regmap, USB_R5, &reg);
 286
 287         if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG))
 288                 return PHY_MODE_USB_DEVICE;
 289
 290         return PHY_MODE_USB_HOST;
 291 }
 292
 293 static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
 294                                         enum phy_mode mode)
 295 {
 296         int ret;
 297
 298         if (!priv->phys[USB2_OTG_PHY])
 299                 return -EINVAL;
 300
 301         if (mode == PHY_MODE_USB_HOST)
 302                 dev_info(priv->dev, "switching to Host Mode\n");
 303         else
 304                 dev_info(priv->dev, "switching to Device Mode\n");
 305
 306         if (priv->vbus) {
 307                 if (mode == PHY_MODE_USB_DEVICE)
 308                         ret = regulator_disable(priv->vbus);
 309                 else
 310                         ret = regulator_enable(priv->vbus);
 311                 if (ret)
 312                         return ret;
 313         }
 314
 315         priv->otg_phy_mode = mode;
 316
 317         dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
 318
 319         dwc3_meson_g12a_usb_otg_apply_mode(priv);
 320
 321         return 0;
 322 }
 323
 324 static int dwc3_meson_g12a_role_set(struct device *dev, enum usb_role role)
 325 {
 326         struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
 327         enum phy_mode mode;
 328
 329         if (role == USB_ROLE_NONE)
 330                 return 0;
 331
 332         mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST
 333                                        : PHY_MODE_USB_DEVICE;
 334
 335         if (mode == priv->otg_phy_mode)
 336                 return 0;
 337
 338         return dwc3_meson_g12a_otg_mode_set(priv, mode);
 339 }
 340
 341 static enum usb_role dwc3_meson_g12a_role_get(struct device *dev)
 342 {
 343         struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
 344
 345         return priv->otg_phy_mode == PHY_MODE_USB_HOST ?
 346                 USB_ROLE_HOST : USB_ROLE_DEVICE;
 347 }
 348
 349 static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data)
 350 {
 351         struct dwc3_meson_g12a *priv = data;
 352         enum phy_mode otg_id;
 353
 354         otg_id = dwc3_meson_g12a_get_id(priv);
 355         if (otg_id != priv->otg_phy_mode) {
 356                 if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
 357                         dev_warn(priv->dev, "Failed to switch OTG mode\n");
 358         }
 359
 360         regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0);
 361
 362         return IRQ_HANDLED;
 363 }
 364
 365 static struct device *dwc3_meson_g12_find_child(struct device *dev,
 366                                                 const char *compatible)
 367 {
 368         struct platform_device *pdev;
 369         struct device_node *np;
 370
 371         np = of_get_compatible_child(dev->of_node, compatible);
 372         if (!np)
 373                 return NULL;
 374
 375         pdev = of_find_device_by_node(np);
 376         of_node_put(np);
 377         if (!pdev)
 378                 return NULL;
 379
 380         return &pdev->dev;
 381 }
 382
 383 static int dwc3_meson_g12a_probe(struct platform_device *pdev)
 384 {
 385         struct dwc3_meson_g12a  *priv;
 386         struct device           *dev = &pdev->dev;
 387         struct device_node      *np = dev->of_node;
 388         void __iomem *base;
 389         enum phy_mode otg_id;
 390         int ret, i, irq;
 391
 392         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 393         if (!priv)
 394                 return -ENOMEM;
 395
 396         base = devm_platform_ioremap_resource(pdev, 0);
 397         if (IS_ERR(base))
 398                 return PTR_ERR(base);
 399
 400         priv->regmap = devm_regmap_init_mmio(dev, base,
 401                                              &phy_meson_g12a_usb3_regmap_conf);
 402         if (IS_ERR(priv->regmap))
 403                 return PTR_ERR(priv->regmap);
 404
 405         priv->vbus = devm_regulator_get_optional(dev, "vbus");
 406         if (IS_ERR(priv->vbus)) {
 407                 if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
 408                         return PTR_ERR(priv->vbus);
 409                 priv->vbus = NULL;
 410         }
 411
 412         priv->clk = devm_clk_get(dev, NULL);
 413         if (IS_ERR(priv->clk))
 414                 return PTR_ERR(priv->clk);
 415
 416         ret = clk_prepare_enable(priv->clk);
 417         if (ret)
 418                 return ret;
 419
 420         devm_add_action_or_reset(dev,
 421                                  (void(*)(void *))clk_disable_unprepare,
 422                                  priv->clk);
 423
 424         platform_set_drvdata(pdev, priv);
 425         priv->dev = dev;
 426
 427         priv->reset = devm_reset_control_get(dev, NULL);
 428         if (IS_ERR(priv->reset)) {
 429                 ret = PTR_ERR(priv->reset);
 430                 dev_err(dev, "failed to get device reset, err=%d\n", ret);
 431                 return ret;
 432         }
 433
 434         ret = reset_control_reset(priv->reset);
 435         if (ret)
 436                 return ret;
 437
 438         ret = dwc3_meson_g12a_get_phys(priv);
 439         if (ret)
 440                 return ret;
 441
 442         if (priv->vbus) {
 443                 ret = regulator_enable(priv->vbus);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         /* Get dr_mode */
 449         priv->otg_mode = usb_get_dr_mode(dev);
 450
 451         if (priv->otg_mode == USB_DR_MODE_OTG) {
 452                 /* Ack irq before registering */
 453                 regmap_update_bits(priv->regmap, USB_R5,
 454                                    USB_R5_ID_DIG_IRQ, 0);
 455
 456                 irq = platform_get_irq(pdev, 0);
 457                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 458                                                 dwc3_meson_g12a_irq_thread,
 459                                                 IRQF_ONESHOT, pdev->name, priv);
 460                 if (ret)
 461                         return ret;
 462         }
 463
 464         dwc3_meson_g12a_usb_init(priv);
 465
 466         /* Init PHYs */
 467         for (i = 0 ; i < PHY_COUNT ; ++i) {
 468                 ret = phy_init(priv->phys[i]);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         /* Set PHY Power */
 474         for (i = 0 ; i < PHY_COUNT ; ++i) {
 475                 ret = phy_power_on(priv->phys[i]);
 476                 if (ret)
 477                         goto err_phys_exit;
 478         }
 479
 480         ret = of_platform_populate(np, NULL, NULL, dev);
 481         if (ret) {
 482                 clk_disable_unprepare(priv->clk);
 483                 goto err_phys_power;
 484         }
 485
 486         /* Setup OTG mode corresponding to the ID pin */
 487         if (priv->otg_mode == USB_DR_MODE_OTG) {
 488                 otg_id = dwc3_meson_g12a_get_id(priv);
 489                 if (otg_id != priv->otg_phy_mode) {
 490                         if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
 491                                 dev_warn(dev, "Failed to switch OTG mode\n");
 492                 }
 493         }
 494
 495         /* Setup role switcher */
 496         priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
 497                                                                 "snps,dwc3");
 498         priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
 499         priv->switch_desc.allow_userspace_control = true;
 500         priv->switch_desc.set = dwc3_meson_g12a_role_set;
 501         priv->switch_desc.get = dwc3_meson_g12a_role_get;
 502
 503         priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
 504         if (IS_ERR(priv->role_switch))
 505                 dev_warn(dev, "Unable to register Role Switch\n");
 506
 507         pm_runtime_set_active(dev);
 508         pm_runtime_enable(dev);
 509         pm_runtime_get_sync(dev);
 510
 511         return 0;
 512
 513 err_phys_power:
 514         for (i = 0 ; i < PHY_COUNT ; ++i)
 515                 phy_power_off(priv->phys[i]);
 516
 517 err_phys_exit:
 518         for (i = 0 ; i < PHY_COUNT ; ++i)
 519                 phy_exit(priv->phys[i]);
 520
 521         return ret;
 522 }
 523
 524 static int dwc3_meson_g12a_remove(struct platform_device *pdev)
 525 {
 526         struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev);
 527         struct device *dev = &pdev->dev;
 528         int i;
 529
 530         usb_role_switch_unregister(priv->role_switch);
 531
 532         of_platform_depopulate(dev);
 533
 534         for (i = 0 ; i < PHY_COUNT ; ++i) {
 535                 phy_power_off(priv->phys[i]);
 536                 phy_exit(priv->phys[i]);
 537         }
 538
 539         pm_runtime_disable(dev);
 540         pm_runtime_put_noidle(dev);
 541         pm_runtime_set_suspended(dev);
 542
 543         return 0;
 544 }
 545
 546 static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
 547 {
 548         struct dwc3_meson_g12a  *priv = dev_get_drvdata(dev);
 549
 550         clk_disable(priv->clk);
 551
 552         return 0;
 553 }
 554
 555 static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
 556 {
 557         struct dwc3_meson_g12a  *priv = dev_get_drvdata(dev);
 558
 559         return clk_enable(priv->clk);
 560 }
 561
 562 static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
 563 {
 564         struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
 565         int i, ret;
 566
 567         if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
 568                 ret = regulator_disable(priv->vbus);
 569                 if (ret)
 570                         return ret;
 571         }
 572
 573         for (i = 0 ; i < PHY_COUNT ; ++i) {
 574                 phy_power_off(priv->phys[i]);
 575                 phy_exit(priv->phys[i]);
 576         }
 577
 578         reset_control_assert(priv->reset);
 579
 580         return 0;
 581 }
 582
 583 static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
 584 {
 585         struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
 586         int i, ret;
 587
 588         reset_control_deassert(priv->reset);
 589
 590         dwc3_meson_g12a_usb_init(priv);
 591
 592         /* Init PHYs */
 593         for (i = 0 ; i < PHY_COUNT ; ++i) {
 594                 ret = phy_init(priv->phys[i]);
 595                 if (ret)
 596                         return ret;
 597         }
 598
 599         /* Set PHY Power */
 600         for (i = 0 ; i < PHY_COUNT ; ++i) {
 601                 ret = phy_power_on(priv->phys[i]);
 602                 if (ret)
 603                         return ret;
 604         }
 605
 606        if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
 607                ret = regulator_enable(priv->vbus);
 608                 if (ret)
 609                         return ret;
 610         }
 611
 612         return 0;
 613 }
 614
 615 static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
 616         SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume)
 617         SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend,
 618                            dwc3_meson_g12a_runtime_resume, NULL)
 619 };
 620
 621 static const struct of_device_id dwc3_meson_g12a_match[] = {
 622         { .compatible = "amlogic,meson-g12a-usb-ctrl" },
 623         { /* Sentinel */ }
 624 };
 625 MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
 626
 627 static struct platform_driver dwc3_meson_g12a_driver = {
 628         .probe          = dwc3_meson_g12a_probe,
 629         .remove         = dwc3_meson_g12a_remove,
 630         .driver         = {
 631                 .name   = "dwc3-meson-g12a",
 632                 .of_match_table = dwc3_meson_g12a_match,
 633                 .pm     = &dwc3_meson_g12a_dev_pm_ops,
 634         },
 635 };
 636
 637 module_platform_driver(dwc3_meson_g12a_driver);
 638 MODULE_LICENSE("GPL v2");
 639 MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer");
 640 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");