1 // SPDX-License-Identifier: GPL-1.0+
3 * Open Host Controller Interface (OHCI) driver for USB.
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the http://www.usb.org website.
21 * This file is licenced under the GPL.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/usb.h>
37 #include <linux/usb/otg.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmapool.h>
41 #include <linux/workqueue.h>
42 #include <linux/debugfs.h>
43 #include <linux/genalloc.h>
47 #include <asm/unaligned.h>
48 #include <asm/byteorder.h>
51 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
54 /*-------------------------------------------------------------------------*/
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78 #define IO_WATCHDOG_OFF 0xffffff00
81 #include "pci-quirks.h"
83 static void ohci_dump(struct ohci_hcd
*ohci
);
84 static void ohci_stop(struct usb_hcd
*hcd
);
85 static void io_watchdog_func(struct timer_list
*t
);
94 * On architectures with edge-triggered interrupts we must never return
97 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
98 #define IRQ_NOTMINE IRQ_HANDLED
100 #define IRQ_NOTMINE IRQ_NONE
104 /* Some boards misreport power switching/overcurrent */
105 static bool distrust_firmware
= true;
106 module_param (distrust_firmware
, bool, 0);
107 MODULE_PARM_DESC (distrust_firmware
,
108 "true to distrust firmware power/overcurrent setup");
110 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
111 static bool no_handshake
;
112 module_param (no_handshake
, bool, 0);
113 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
115 /*-------------------------------------------------------------------------*/
117 static int number_of_tds(struct urb
*urb
)
119 int len
, i
, num
, this_sg_len
;
120 struct scatterlist
*sg
;
122 len
= urb
->transfer_buffer_length
;
123 i
= urb
->num_mapped_sgs
;
125 if (len
> 0 && i
> 0) { /* Scatter-gather transfer */
129 this_sg_len
= min_t(int, sg_dma_len(sg
), len
);
130 num
+= DIV_ROUND_UP(this_sg_len
, 4096);
132 if (--i
<= 0 || len
<= 0)
137 } else { /* Non-SG transfer */
138 /* one TD for every 4096 Bytes (could be up to 8K) */
139 num
= DIV_ROUND_UP(len
, 4096);
145 * queue up an urb for anything except the root hub
147 static int ohci_urb_enqueue (
152 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
154 urb_priv_t
*urb_priv
;
155 unsigned int pipe
= urb
->pipe
;
160 /* every endpoint has a ed, locate and maybe (re)initialize it */
161 ed
= ed_get(ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
);
165 /* for the private part of the URB we need the number of TDs (size) */
168 /* td_submit_urb() doesn't yet handle these */
169 if (urb
->transfer_buffer_length
> 4096)
172 /* 1 TD for setup, 1 for ACK, plus ... */
175 // case PIPE_INTERRUPT:
178 size
+= number_of_tds(urb
);
179 /* maybe a zero-length packet to wrap it up */
182 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
183 && (urb
->transfer_buffer_length
184 % usb_maxpacket (urb
->dev
, pipe
,
185 usb_pipeout (pipe
))) == 0)
188 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
189 size
= urb
->number_of_packets
;
193 /* allocate the private part of the URB */
194 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
198 INIT_LIST_HEAD (&urb_priv
->pending
);
199 urb_priv
->length
= size
;
202 /* allocate the TDs (deferring hash chain updates) */
203 for (i
= 0; i
< size
; i
++) {
204 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
205 if (!urb_priv
->td
[i
]) {
206 urb_priv
->length
= i
;
207 urb_free_priv (ohci
, urb_priv
);
212 spin_lock_irqsave (&ohci
->lock
, flags
);
214 /* don't submit to a dead HC */
215 if (!HCD_HW_ACCESSIBLE(hcd
)) {
219 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
223 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
227 /* schedule the ed if needed */
228 if (ed
->state
== ED_IDLE
) {
229 retval
= ed_schedule (ohci
, ed
);
231 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
235 /* Start up the I/O watchdog timer, if it's not running */
236 if (ohci
->prev_frame_no
== IO_WATCHDOG_OFF
&&
237 list_empty(&ohci
->eds_in_use
) &&
238 !(ohci
->flags
& OHCI_QUIRK_QEMU
)) {
239 ohci
->prev_frame_no
= ohci_frame_no(ohci
);
240 mod_timer(&ohci
->io_watchdog
,
241 jiffies
+ IO_WATCHDOG_DELAY
);
243 list_add(&ed
->in_use_list
, &ohci
->eds_in_use
);
245 if (ed
->type
== PIPE_ISOCHRONOUS
) {
246 u16 frame
= ohci_frame_no(ohci
);
248 /* delay a few frames before the first TD */
249 frame
+= max_t (u16
, 8, ed
->interval
);
250 frame
&= ~(ed
->interval
- 1);
252 urb
->start_frame
= frame
;
253 ed
->last_iso
= frame
+ ed
->interval
* (size
- 1);
255 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
256 u16 next
= ohci_frame_no(ohci
) + 1;
257 u16 frame
= ed
->last_iso
+ ed
->interval
;
258 u16 length
= ed
->interval
* (size
- 1);
260 /* Behind the scheduling threshold? */
261 if (unlikely(tick_before(frame
, next
))) {
263 /* URB_ISO_ASAP: Round up to the first available slot */
264 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
265 frame
+= (next
- frame
+ ed
->interval
- 1) &
269 * Not ASAP: Use the next slot in the stream,
274 * Some OHCI hardware doesn't handle late TDs
275 * correctly. After retiring them it proceeds
276 * to the next ED instead of the next TD.
277 * Therefore we have to omit the late TDs
280 urb_priv
->td_cnt
= DIV_ROUND_UP(
281 (u16
) (next
- frame
),
283 if (urb_priv
->td_cnt
>= urb_priv
->length
) {
284 ++urb_priv
->td_cnt
; /* Mark it */
285 ohci_dbg(ohci
, "iso underrun %p (%u+%u < %u)\n",
291 urb
->start_frame
= frame
;
292 ed
->last_iso
= frame
+ length
;
295 /* fill the TDs and link them to the ed; and
296 * enable that part of the schedule, if needed
297 * and update count of queued periodic urbs
299 urb
->hcpriv
= urb_priv
;
300 td_submit_urb (ohci
, urb
);
304 urb_free_priv (ohci
, urb_priv
);
305 spin_unlock_irqrestore (&ohci
->lock
, flags
);
310 * decouple the URB from the HC queues (TDs, urb_priv).
311 * reporting is always done
312 * asynchronously, and we might be dealing with an urb that's
313 * partially transferred, or an ED with other urbs being unlinked.
315 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
317 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
320 urb_priv_t
*urb_priv
;
322 spin_lock_irqsave (&ohci
->lock
, flags
);
323 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
326 /* Unless an IRQ completed the unlink while it was being
327 * handed to us, flag it for unlink and giveback, and force
328 * some upcoming INTR_SF to call finish_unlinks()
330 urb_priv
= urb
->hcpriv
;
331 if (urb_priv
->ed
->state
== ED_OPER
)
332 start_ed_unlink(ohci
, urb_priv
->ed
);
334 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
335 /* With HC dead, we can clean up right away */
339 spin_unlock_irqrestore (&ohci
->lock
, flags
);
343 /*-------------------------------------------------------------------------*/
345 /* frees config/altsetting state for endpoints,
346 * including ED memory, dummy TD, and bulk/intr data toggle
350 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
352 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
354 struct ed
*ed
= ep
->hcpriv
;
355 unsigned limit
= 1000;
357 /* ASSERT: any requests/urbs are being unlinked */
358 /* ASSERT: nobody can be submitting urbs for this any more */
364 spin_lock_irqsave (&ohci
->lock
, flags
);
366 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
373 case ED_UNLINK
: /* wait for hw to finish? */
374 /* major IRQ delivery trouble loses INTR_SF too... */
376 ohci_warn(ohci
, "ED unlink timeout\n");
379 spin_unlock_irqrestore (&ohci
->lock
, flags
);
380 schedule_timeout_uninterruptible(1);
382 case ED_IDLE
: /* fully unlinked */
383 if (list_empty (&ed
->td_list
)) {
384 td_free (ohci
, ed
->dummy
);
390 /* caller was supposed to have unlinked any requests;
391 * that's not our job. can't recover; must leak ed.
393 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
394 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
395 list_empty (&ed
->td_list
) ? "" : " (has tds)");
396 td_free (ohci
, ed
->dummy
);
400 spin_unlock_irqrestore (&ohci
->lock
, flags
);
403 static int ohci_get_frame (struct usb_hcd
*hcd
)
405 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
407 return ohci_frame_no(ohci
);
410 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
412 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
413 ohci
->hc_control
&= OHCI_CTRL_RWC
;
414 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
415 ohci
->rh_state
= OHCI_RH_HALTED
;
418 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
419 * other cases where the next software may expect clean state from the
420 * "firmware". this is bus-neutral, unlike shutdown() methods.
422 static void _ohci_shutdown(struct usb_hcd
*hcd
)
424 struct ohci_hcd
*ohci
;
426 ohci
= hcd_to_ohci (hcd
);
427 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
429 /* Software reset, after which the controller goes into SUSPEND */
430 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
431 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
434 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
435 ohci
->rh_state
= OHCI_RH_HALTED
;
438 static void ohci_shutdown(struct usb_hcd
*hcd
)
440 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
443 spin_lock_irqsave(&ohci
->lock
, flags
);
445 spin_unlock_irqrestore(&ohci
->lock
, flags
);
448 /*-------------------------------------------------------------------------*
450 *-------------------------------------------------------------------------*/
452 /* init memory, and kick BIOS/SMM off */
454 static int ohci_init (struct ohci_hcd
*ohci
)
457 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
459 /* Accept arbitrarily long scatter-gather lists */
460 if (!hcd
->localmem_pool
)
461 hcd
->self
.sg_tablesize
= ~0;
463 if (distrust_firmware
)
464 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
466 ohci
->rh_state
= OHCI_RH_HALTED
;
467 ohci
->regs
= hcd
->regs
;
469 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
470 * was never needed for most non-PCI systems ... remove the code?
474 /* SMM owns the HC? not for long! */
475 if (!no_handshake
&& ohci_readl (ohci
,
476 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
479 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
481 /* this timeout is arbitrary. we make it long, so systems
482 * depending on usb keyboards may be usable even if the
483 * BIOS/SMM code seems pretty broken.
485 temp
= 500; /* arbitrary: five seconds */
487 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
488 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
489 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
492 ohci_err (ohci
, "USB HC takeover failed!"
493 " (BIOS/SMM bug)\n");
497 ohci_usb_reset (ohci
);
501 /* Disable HC interrupts */
502 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
504 /* flush the writes, and save key bits like RWC */
505 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
506 ohci
->hc_control
|= OHCI_CTRL_RWC
;
508 /* Read the number of ports unless overridden */
509 if (ohci
->num_ports
== 0)
510 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
515 timer_setup(&ohci
->io_watchdog
, io_watchdog_func
, 0);
516 ohci
->prev_frame_no
= IO_WATCHDOG_OFF
;
518 if (hcd
->localmem_pool
)
519 ohci
->hcca
= gen_pool_dma_alloc_align(hcd
->localmem_pool
,
521 &ohci
->hcca_dma
, 256);
523 ohci
->hcca
= dma_alloc_coherent(hcd
->self
.controller
,
530 if ((ret
= ohci_mem_init (ohci
)) < 0)
533 create_debug_files (ohci
);
539 /*-------------------------------------------------------------------------*/
541 /* Start an OHCI controller, set the BUS operational
542 * resets USB and controller
545 static int ohci_run (struct ohci_hcd
*ohci
)
548 int first
= ohci
->fminterval
== 0;
549 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
551 ohci
->rh_state
= OHCI_RH_HALTED
;
553 /* boot firmware should have set this up (5.1.1.3.1) */
556 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
557 ohci
->fminterval
= val
& 0x3fff;
558 if (ohci
->fminterval
!= FI
)
559 ohci_dbg (ohci
, "fminterval delta %d\n",
560 ohci
->fminterval
- FI
);
561 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
562 /* also: power/overcurrent flags in roothub.a */
565 /* Reset USB nearly "by the book". RemoteWakeupConnected has
566 * to be checked in case boot firmware (BIOS/SMM/...) has set up
567 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
568 * If the bus glue detected wakeup capability then it should
569 * already be enabled; if so we'll just enable it again.
571 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
572 device_set_wakeup_capable(hcd
->self
.controller
, 1);
574 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
578 case OHCI_USB_SUSPEND
:
579 case OHCI_USB_RESUME
:
580 ohci
->hc_control
&= OHCI_CTRL_RWC
;
581 ohci
->hc_control
|= OHCI_USB_RESUME
;
582 val
= 10 /* msec wait */;
584 // case OHCI_USB_RESET:
586 ohci
->hc_control
&= OHCI_CTRL_RWC
;
587 ohci
->hc_control
|= OHCI_USB_RESET
;
588 val
= 50 /* msec wait */;
591 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
593 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
596 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
598 /* 2msec timelimit here means no irqs/preempt */
599 spin_lock_irq (&ohci
->lock
);
602 /* HC Reset requires max 10 us delay */
603 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
604 val
= 30; /* ... allow extra time */
605 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
607 spin_unlock_irq (&ohci
->lock
);
608 ohci_err (ohci
, "USB HC reset timed out!\n");
614 /* now we're in the SUSPEND state ... must go OPERATIONAL
615 * within 2msec else HC enters RESUME
617 * ... but some hardware won't init fmInterval "by the book"
618 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
619 * this if we write fmInterval after we're OPERATIONAL.
620 * Unclear about ALi, ServerWorks, and others ... this could
621 * easily be a longstanding bug in chip init on Linux.
623 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
624 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
625 // flush those writes
626 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
629 /* Tell the controller where the control and bulk lists are
630 * The lists are empty now. */
631 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
632 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
634 /* a reset clears this */
635 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
637 periodic_reinit (ohci
);
639 /* some OHCI implementations are finicky about how they init.
640 * bogus values here mean not even enumeration could work.
642 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
643 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
644 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
645 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
646 ohci_dbg (ohci
, "enabling initreset quirk\n");
649 spin_unlock_irq (&ohci
->lock
);
650 ohci_err (ohci
, "init err (%08x %04x)\n",
651 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
652 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
656 /* use rhsc irqs after hub_wq is allocated */
657 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
658 hcd
->uses_new_polling
= 1;
660 /* start controller operations */
661 ohci
->hc_control
&= OHCI_CTRL_RWC
;
662 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
663 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
664 ohci
->rh_state
= OHCI_RH_RUNNING
;
666 /* wake on ConnectStatusChange, matching external hubs */
667 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
669 /* Choose the interrupts we care about now, others later on demand */
670 mask
= OHCI_INTR_INIT
;
671 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
672 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
674 /* handle root hub init quirks ... */
675 val
= roothub_a (ohci
);
676 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
677 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
678 /* NSC 87560 and maybe others */
680 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
681 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
682 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
683 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
684 /* hub power always on; required for AMD-756 and some
685 * Mac platforms. ganged overcurrent reporting, if any.
688 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
690 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
691 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
692 &ohci
->regs
->roothub
.b
);
693 // flush those writes
694 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
696 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
697 spin_unlock_irq (&ohci
->lock
);
699 // POTPGT delay is bits 24-31, in 2 ms units.
700 mdelay ((val
>> 23) & 0x1fe);
707 /* ohci_setup routine for generic controller initialization */
709 int ohci_setup(struct usb_hcd
*hcd
)
711 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
715 return ohci_init(ohci
);
717 EXPORT_SYMBOL_GPL(ohci_setup
);
719 /* ohci_start routine for generic controller start of all OHCI bus glue */
720 static int ohci_start(struct usb_hcd
*hcd
)
722 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
725 ret
= ohci_run(ohci
);
727 ohci_err(ohci
, "can't start\n");
733 /*-------------------------------------------------------------------------*/
736 * Some OHCI controllers are known to lose track of completed TDs. They
737 * don't add the TDs to the hardware done queue, which means we never see
738 * them as being completed.
740 * This watchdog routine checks for such problems. Without some way to
741 * tell when those TDs have completed, we would never take their EDs off
742 * the unlink list. As a result, URBs could never be dequeued and
743 * endpoints could never be released.
745 static void io_watchdog_func(struct timer_list
*t
)
747 struct ohci_hcd
*ohci
= from_timer(ohci
, t
, io_watchdog
);
748 bool takeback_all_pending
= false;
752 struct td
*td
, *td_start
, *td_next
;
753 unsigned frame_no
, prev_frame_no
= IO_WATCHDOG_OFF
;
756 spin_lock_irqsave(&ohci
->lock
, flags
);
759 * One way to lose track of completed TDs is if the controller
760 * never writes back the done queue head. If it hasn't been
761 * written back since the last time this function ran and if it
762 * was non-empty at that time, something is badly wrong with the
765 status
= ohci_readl(ohci
, &ohci
->regs
->intrstatus
);
766 if (!(status
& OHCI_INTR_WDH
) && ohci
->wdh_cnt
== ohci
->prev_wdh_cnt
) {
767 if (ohci
->prev_donehead
) {
768 ohci_err(ohci
, "HcDoneHead not written back; disabled\n");
770 usb_hc_died(ohci_to_hcd(ohci
));
772 _ohci_shutdown(ohci_to_hcd(ohci
));
775 /* No write back because the done queue was empty */
776 takeback_all_pending
= true;
780 /* Check every ED which might have pending TDs */
781 list_for_each_entry(ed
, &ohci
->eds_in_use
, in_use_list
) {
782 if (ed
->pending_td
) {
783 if (takeback_all_pending
||
784 OKAY_TO_TAKEBACK(ohci
, ed
)) {
785 unsigned tmp
= hc32_to_cpu(ohci
, ed
->hwINFO
);
787 ohci_dbg(ohci
, "takeback pending TD for dev %d ep 0x%x\n",
789 (0x000f & (tmp
>> 7)) +
790 ((tmp
& ED_IN
) >> 5));
791 add_to_done_list(ohci
, ed
->pending_td
);
795 /* Starting from the latest pending TD, */
798 /* or the last TD on the done list, */
800 list_for_each_entry(td_next
, &ed
->td_list
, td_list
) {
801 if (!td_next
->next_dl_td
)
807 /* find the last TD processed by the controller. */
808 head
= hc32_to_cpu(ohci
, READ_ONCE(ed
->hwHeadP
)) & TD_MASK
;
810 td_next
= list_prepare_entry(td
, &ed
->td_list
, td_list
);
811 list_for_each_entry_continue(td_next
, &ed
->td_list
, td_list
) {
812 if (head
== (u32
) td_next
->td_dma
)
814 td
= td_next
; /* head pointer has passed this TD */
816 if (td
!= td_start
) {
818 * In case a WDH cycle is in progress, we will wait
819 * for the next two cycles to complete before assuming
820 * this TD will never get on the done queue.
822 ed
->takeback_wdh_cnt
= ohci
->wdh_cnt
+ 2;
829 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
832 * Sometimes a controller just stops working. We can tell
833 * by checking that the frame counter has advanced since
834 * the last time we ran.
836 * But be careful: Some controllers violate the spec by
837 * stopping their frame counter when no ports are active.
839 frame_no
= ohci_frame_no(ohci
);
840 if (frame_no
== ohci
->prev_frame_no
) {
845 for (i
= 0; i
< ohci
->num_ports
; ++i
) {
846 tmp
= roothub_portstatus(ohci
, i
);
847 /* Enabled and not suspended? */
848 if ((tmp
& RH_PS_PES
) && !(tmp
& RH_PS_PSS
))
852 if (active_cnt
> 0) {
853 ohci_err(ohci
, "frame counter not updating; disabled\n");
857 if (!list_empty(&ohci
->eds_in_use
)) {
858 prev_frame_no
= frame_no
;
859 ohci
->prev_wdh_cnt
= ohci
->wdh_cnt
;
860 ohci
->prev_donehead
= ohci_readl(ohci
,
861 &ohci
->regs
->donehead
);
862 mod_timer(&ohci
->io_watchdog
,
863 jiffies
+ IO_WATCHDOG_DELAY
);
868 ohci
->prev_frame_no
= prev_frame_no
;
869 spin_unlock_irqrestore(&ohci
->lock
, flags
);
872 /* an interrupt happens */
874 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
876 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
877 struct ohci_regs __iomem
*regs
= ohci
->regs
;
880 /* Read interrupt status (and flush pending writes). We ignore the
881 * optimization of checking the LSB of hcca->done_head; it doesn't
882 * work on all systems (edge triggering for OHCI can be a factor).
884 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
886 /* Check for an all 1's result which is a typical consequence
887 * of dead, unclocked, or unplugged (CardBus...) devices
889 if (ints
== ~(u32
)0) {
890 ohci
->rh_state
= OHCI_RH_HALTED
;
891 ohci_dbg (ohci
, "device removed!\n");
896 /* We only care about interrupts that are enabled */
897 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
899 /* interrupt for some other device? */
900 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
903 if (ints
& OHCI_INTR_UE
) {
904 // e.g. due to PCI Master/Target Abort
905 if (quirk_nec(ohci
)) {
906 /* Workaround for a silicon bug in some NEC chips used
907 * in Apple's PowerBooks. Adapted from Darwin code.
909 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
911 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
913 schedule_work (&ohci
->nec_work
);
915 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
916 ohci
->rh_state
= OHCI_RH_HALTED
;
921 ohci_usb_reset (ohci
);
924 if (ints
& OHCI_INTR_RHSC
) {
925 ohci_dbg(ohci
, "rhsc\n");
926 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
927 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
930 /* NOTE: Vendors didn't always make the same implementation
931 * choices for RHSC. Many followed the spec; RHSC triggers
932 * on an edge, like setting and maybe clearing a port status
933 * change bit. With others it's level-triggered, active
934 * until hub_wq clears all the port status change bits. We'll
935 * always disable it here and rely on polling until hub_wq
938 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
939 usb_hcd_poll_rh_status(hcd
);
942 /* For connect and disconnect events, we expect the controller
943 * to turn on RHSC along with RD. But for remote wakeup events
944 * this might not happen.
946 else if (ints
& OHCI_INTR_RD
) {
947 ohci_dbg(ohci
, "resume detect\n");
948 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
949 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
950 if (ohci
->autostop
) {
951 spin_lock (&ohci
->lock
);
952 ohci_rh_resume (ohci
);
953 spin_unlock (&ohci
->lock
);
955 usb_hcd_resume_root_hub(hcd
);
958 spin_lock(&ohci
->lock
);
959 if (ints
& OHCI_INTR_WDH
)
960 update_done_list(ohci
);
962 /* could track INTR_SO to reduce available PCI/... bandwidth */
964 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
965 * when there's still unlinking to be done (next frame).
968 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
969 && ohci
->rh_state
== OHCI_RH_RUNNING
)
970 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
972 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
973 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
974 if (ints
& OHCI_INTR_WDH
)
977 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
978 // flush those writes
979 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
981 spin_unlock(&ohci
->lock
);
986 /*-------------------------------------------------------------------------*/
988 static void ohci_stop (struct usb_hcd
*hcd
)
990 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
995 flush_work(&ohci
->nec_work
);
996 del_timer_sync(&ohci
->io_watchdog
);
997 ohci
->prev_frame_no
= IO_WATCHDOG_OFF
;
999 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1000 ohci_usb_reset(ohci
);
1001 free_irq(hcd
->irq
, hcd
);
1004 if (quirk_amdiso(ohci
))
1007 remove_debug_files (ohci
);
1008 ohci_mem_cleanup (ohci
);
1010 if (hcd
->localmem_pool
)
1011 gen_pool_free(hcd
->localmem_pool
,
1012 (unsigned long)ohci
->hcca
,
1013 sizeof(*ohci
->hcca
));
1015 dma_free_coherent(hcd
->self
.controller
,
1016 sizeof(*ohci
->hcca
),
1017 ohci
->hcca
, ohci
->hcca_dma
);
1023 /*-------------------------------------------------------------------------*/
1025 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1027 /* must not be called from interrupt context */
1028 int ohci_restart(struct ohci_hcd
*ohci
)
1032 struct urb_priv
*priv
;
1035 spin_lock_irq(&ohci
->lock
);
1036 ohci
->rh_state
= OHCI_RH_HALTED
;
1038 /* Recycle any "live" eds/tds (and urbs). */
1039 if (!list_empty (&ohci
->pending
))
1040 ohci_dbg(ohci
, "abort schedule...\n");
1041 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
1042 struct urb
*urb
= priv
->td
[0]->urb
;
1043 struct ed
*ed
= priv
->ed
;
1045 switch (ed
->state
) {
1047 ed
->state
= ED_UNLINK
;
1048 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
1049 ed_deschedule (ohci
, ed
);
1051 ed
->ed_next
= ohci
->ed_rm_list
;
1053 ohci
->ed_rm_list
= ed
;
1058 ohci_dbg(ohci
, "bogus ed %p state %d\n",
1063 urb
->unlinked
= -ESHUTDOWN
;
1066 spin_unlock_irq(&ohci
->lock
);
1068 /* paranoia, in case that didn't work: */
1070 /* empty the interrupt branches */
1071 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
1072 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
1074 /* no EDs to remove */
1075 ohci
->ed_rm_list
= NULL
;
1077 /* empty control and bulk lists */
1078 ohci
->ed_controltail
= NULL
;
1079 ohci
->ed_bulktail
= NULL
;
1081 if ((temp
= ohci_run (ohci
)) < 0) {
1082 ohci_err (ohci
, "can't restart, %d\n", temp
);
1085 ohci_dbg(ohci
, "restart complete\n");
1088 EXPORT_SYMBOL_GPL(ohci_restart
);
1094 int ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1096 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1097 unsigned long flags
;
1100 /* Disable irq emission and mark HW unaccessible. Use
1101 * the spinlock to properly synchronize with possible pending
1102 * RH suspend or resume activity.
1104 spin_lock_irqsave (&ohci
->lock
, flags
);
1105 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1106 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1108 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1109 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1111 synchronize_irq(hcd
->irq
);
1113 if (do_wakeup
&& HCD_WAKEUP_PENDING(hcd
)) {
1114 ohci_resume(hcd
, false);
1119 EXPORT_SYMBOL_GPL(ohci_suspend
);
1122 int ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1124 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
1126 bool need_reinit
= false;
1128 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1130 /* Make sure resume from hibernation re-enumerates everything */
1132 ohci_usb_reset(ohci
);
1134 /* See if the controller is already running or has been reset */
1135 ohci
->hc_control
= ohci_readl(ohci
, &ohci
->regs
->control
);
1136 if (ohci
->hc_control
& (OHCI_CTRL_IR
| OHCI_SCHED_ENABLES
)) {
1139 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
1141 case OHCI_USB_RESET
:
1146 /* If needed, reinitialize and suspend the root hub */
1148 spin_lock_irq(&ohci
->lock
);
1149 ohci_rh_resume(ohci
);
1150 ohci_rh_suspend(ohci
, 0);
1151 spin_unlock_irq(&ohci
->lock
);
1154 /* Normally just turn on port power and enable interrupts */
1156 ohci_dbg(ohci
, "powerup ports\n");
1157 for (port
= 0; port
< ohci
->num_ports
; port
++)
1158 ohci_writel(ohci
, RH_PS_PPS
,
1159 &ohci
->regs
->roothub
.portstatus
[port
]);
1161 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrenable
);
1162 ohci_readl(ohci
, &ohci
->regs
->intrenable
);
1166 usb_hcd_resume_root_hub(hcd
);
1170 EXPORT_SYMBOL_GPL(ohci_resume
);
1174 /*-------------------------------------------------------------------------*/
1177 * Generic structure: This gets copied for platform drivers so that
1178 * individual entries can be overridden as needed.
1181 static const struct hc_driver ohci_hc_driver
= {
1182 .description
= hcd_name
,
1183 .product_desc
= "OHCI Host Controller",
1184 .hcd_priv_size
= sizeof(struct ohci_hcd
),
1187 * generic hardware linkage
1190 .flags
= HCD_MEMORY
| HCD_DMA
| HCD_USB11
,
1193 * basic lifecycle operations
1195 .reset
= ohci_setup
,
1196 .start
= ohci_start
,
1198 .shutdown
= ohci_shutdown
,
1201 * managing i/o requests and associated device resources
1203 .urb_enqueue
= ohci_urb_enqueue
,
1204 .urb_dequeue
= ohci_urb_dequeue
,
1205 .endpoint_disable
= ohci_endpoint_disable
,
1208 * scheduling support
1210 .get_frame_number
= ohci_get_frame
,
1215 .hub_status_data
= ohci_hub_status_data
,
1216 .hub_control
= ohci_hub_control
,
1218 .bus_suspend
= ohci_bus_suspend
,
1219 .bus_resume
= ohci_bus_resume
,
1221 .start_port_reset
= ohci_start_port_reset
,
1224 void ohci_init_driver(struct hc_driver
*drv
,
1225 const struct ohci_driver_overrides
*over
)
1227 /* Copy the generic table to drv and then apply the overrides */
1228 *drv
= ohci_hc_driver
;
1231 drv
->product_desc
= over
->product_desc
;
1232 drv
->hcd_priv_size
+= over
->extra_priv_size
;
1234 drv
->reset
= over
->reset
;
1237 EXPORT_SYMBOL_GPL(ohci_init_driver
);
1239 /*-------------------------------------------------------------------------*/
1241 MODULE_AUTHOR (DRIVER_AUTHOR
);
1242 MODULE_DESCRIPTION(DRIVER_DESC
);
1243 MODULE_LICENSE ("GPL");
1245 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1246 #include "ohci-sa1111.c"
1247 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1250 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1251 #include "ohci-ppc-of.c"
1252 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1255 #ifdef CONFIG_PPC_PS3
1256 #include "ohci-ps3.c"
1257 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1260 #ifdef CONFIG_MFD_SM501
1261 #include "ohci-sm501.c"
1262 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1265 #ifdef CONFIG_MFD_TC6393XB
1266 #include "ohci-tmio.c"
1267 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1270 static int __init
ohci_hcd_mod_init(void)
1277 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1278 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name
,
1279 sizeof (struct ed
), sizeof (struct td
));
1280 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1282 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1284 #ifdef PS3_SYSTEM_BUS_DRIVER
1285 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1290 #ifdef OF_PLATFORM_DRIVER
1291 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1293 goto error_of_platform
;
1296 #ifdef SA1111_DRIVER
1297 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1302 #ifdef SM501_OHCI_DRIVER
1303 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1308 #ifdef TMIO_OHCI_DRIVER
1309 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1317 #ifdef TMIO_OHCI_DRIVER
1318 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1321 #ifdef SM501_OHCI_DRIVER
1322 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1325 #ifdef SA1111_DRIVER
1326 sa1111_driver_unregister(&SA1111_DRIVER
);
1329 #ifdef OF_PLATFORM_DRIVER
1330 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1333 #ifdef PS3_SYSTEM_BUS_DRIVER
1334 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1337 debugfs_remove(ohci_debug_root
);
1338 ohci_debug_root
= NULL
;
1340 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1343 module_init(ohci_hcd_mod_init
);
1345 static void __exit
ohci_hcd_mod_exit(void)
1347 #ifdef TMIO_OHCI_DRIVER
1348 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1350 #ifdef SM501_OHCI_DRIVER
1351 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1353 #ifdef SA1111_DRIVER
1354 sa1111_driver_unregister(&SA1111_DRIVER
);
1356 #ifdef OF_PLATFORM_DRIVER
1357 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1359 #ifdef PS3_SYSTEM_BUS_DRIVER
1360 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1362 debugfs_remove(ohci_debug_root
);
1363 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1365 module_exit(ohci_hcd_mod_exit
);