drivers/usb/host/xhci-mtk.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author:
   5  *  Zhigang.Wei <zhigang.wei@mediatek.com>
   6  *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
   7  */
   8
   9 #ifndef _XHCI_MTK_H_
  10 #define _XHCI_MTK_H_
  11
  12 #include "xhci.h"
  13
  14 /**
  15  * To simplify scheduler algorithm, set a upper limit for ESIT,
  16  * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
  17  * round down to the limit value, that means allocating more
  18  * bandwidth to it.
  19  */
  20 #define XHCI_MTK_MAX_ESIT       64
  21
  22 /**
  23  * @split_bit_map: used to avoid split microframes overlay
  24  * @ep_list: Endpoints using this TT
  25  * @usb_tt: usb TT related
  26  * @tt_port: TT port number
  27  */
  28 struct mu3h_sch_tt {
  29         DECLARE_BITMAP(split_bit_map, XHCI_MTK_MAX_ESIT);
  30         struct list_head ep_list;
  31         struct usb_tt *usb_tt;
  32         int tt_port;
  33 };
  34
  35 /**
  36  * struct mu3h_sch_bw_info: schedule information for bandwidth domain
  37  *
  38  * @bus_bw: array to keep track of bandwidth already used at each uframes
  39  * @bw_ep_list: eps in the bandwidth domain
  40  *
  41  * treat a HS root port as a bandwidth domain, but treat a SS root port as
  42  * two bandwidth domains, one for IN eps and another for OUT eps.
  43  */
  44 struct mu3h_sch_bw_info {
  45         u32 bus_bw[XHCI_MTK_MAX_ESIT];
  46         struct list_head bw_ep_list;
  47 };
  48
  49 /**
  50  * struct mu3h_sch_ep_info: schedule information for endpoint
  51  *
  52  * @esit: unit is 125us, equal to 2 << Interval field in ep-context
  53  * @num_budget_microframes: number of continuous uframes
  54  *              (@repeat==1) scheduled within the interval
  55  * @bw_cost_per_microframe: bandwidth cost per microframe
  56  * @endpoint: linked into bandwidth domain which it belongs to
  57  * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
  58  * @sch_tt: mu3h_sch_tt linked into
  59  * @ep_type: endpoint type
  60  * @maxpkt: max packet size of endpoint
  61  * @ep: address of usb_host_endpoint struct
  62  * @offset: which uframe of the interval that transfer should be
  63  *              scheduled first time within the interval
  64  * @repeat: the time gap between two uframes that transfers are
  65  *              scheduled within a interval. in the simple algorithm, only
  66  *              assign 0 or 1 to it; 0 means using only one uframe in a
  67  *              interval, and 1 means using @num_budget_microframes
  68  *              continuous uframes
  69  * @pkts: number of packets to be transferred in the scheduled uframes
  70  * @cs_count: number of CS that host will trigger
  71  * @burst_mode: burst mode for scheduling. 0: normal burst mode,
  72  *              distribute the bMaxBurst+1 packets for a single burst
  73  *              according to @pkts and @repeat, repeate the burst multiple
  74  *              times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
  75  *              according to @pkts and @repeat. normal mode is used by
  76  *              default
  77  * @bw_budget_table: table to record bandwidth budget per microframe
  78  */
  79 struct mu3h_sch_ep_info {
  80         u32 esit;
  81         u32 num_budget_microframes;
  82         u32 bw_cost_per_microframe;
  83         struct list_head endpoint;
  84         struct list_head tt_endpoint;
  85         struct mu3h_sch_tt *sch_tt;
  86         u32 ep_type;
  87         u32 maxpkt;
  88         void *ep;
  89         /*
  90          * mtk xHCI scheduling information put into reserved DWs
  91          * in ep context
  92          */
  93         u32 offset;
  94         u32 repeat;
  95         u32 pkts;
  96         u32 cs_count;
  97         u32 burst_mode;
  98         u32 bw_budget_table[0];
  99 };
 100
 101 #define MU3C_U3_PORT_MAX 4
 102 #define MU3C_U2_PORT_MAX 5
 103
 104 /**
 105  * struct mu3c_ippc_regs: MTK ssusb ip port control registers
 106  * @ip_pw_ctr0~3: ip power and clock control registers
 107  * @ip_pw_sts1~2: ip power and clock status registers
 108  * @ip_xhci_cap: ip xHCI capability register
 109  * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
 110  * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
 111  * @u2_phy_pll: usb2 phy pll control register
 112  */
 113 struct mu3c_ippc_regs {
 114         __le32 ip_pw_ctr0;
 115         __le32 ip_pw_ctr1;
 116         __le32 ip_pw_ctr2;
 117         __le32 ip_pw_ctr3;
 118         __le32 ip_pw_sts1;
 119         __le32 ip_pw_sts2;
 120         __le32 reserved0[3];
 121         __le32 ip_xhci_cap;
 122         __le32 reserved1[2];
 123         __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
 124         __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
 125         __le32 reserved2;
 126         __le32 u2_phy_pll;
 127         __le32 reserved3[33]; /* 0x80 ~ 0xff */
 128 };
 129
 130 struct xhci_hcd_mtk {
 131         struct device *dev;
 132         struct usb_hcd *hcd;
 133         struct mu3h_sch_bw_info *sch_array;
 134         struct mu3c_ippc_regs __iomem *ippc_regs;
 135         bool has_ippc;
 136         int num_u2_ports;
 137         int num_u3_ports;
 138         int u3p_dis_msk;
 139         struct regulator *vusb33;
 140         struct regulator *vbus;
 141         struct clk *sys_clk;    /* sys and mac clock */
 142         struct clk *xhci_clk;
 143         struct clk *ref_clk;
 144         struct clk *mcu_clk;
 145         struct clk *dma_clk;
 146         struct regmap *pericfg;
 147         struct phy **phys;
 148         int num_phys;
 149         bool lpm_support;
 150         /* usb remote wakeup */
 151         bool uwk_en;
 152         struct regmap *uwk;
 153         u32 uwk_reg_base;
 154         u32 uwk_vers;
 155 };
 156
 157 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
 158 {
 159         return dev_get_drvdata(hcd->self.controller);
 160 }
 161
 162 #if IS_ENABLED(CONFIG_USB_XHCI_MTK)
 163 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
 164 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
 165 int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 166                 struct usb_host_endpoint *ep);
 167 void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 168                 struct usb_host_endpoint *ep);
 169
 170 #else
 171 static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
 172         struct usb_device *udev, struct usb_host_endpoint *ep)
 173 {
 174         return 0;
 175 }
 176
 177 static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
 178         struct usb_device *udev, struct usb_host_endpoint *ep)
 179 {
 180 }
 181
 182 #endif
 183
 184 #endif          /* _XHCI_MTK_H_ */