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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / sound / soc / fsl / fsl_sai.c
blob0754df771e3b4c8a945c29e8c3c99f5c23403719
1 /*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
4 * Copyright 2012-2015 Freescale Semiconductor, Inc.
5 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/time.h>
21 #include <sound/core.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/pcm_params.h>
24
25 #include "fsl_sai.h"
26 #include "imx-pcm.h"
27
28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
29 FSL_SAI_CSR_FEIE)
30
31 static const unsigned int fsl_sai_rates[] = {
32 8000, 11025, 12000, 16000, 22050,
33 24000, 32000, 44100, 48000, 64000,
34 88200, 96000, 176400, 192000
35 };
36
37 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
38 .count = ARRAY_SIZE(fsl_sai_rates),
39 .list = fsl_sai_rates,
40 };
41
42 static irqreturn_t fsl_sai_isr(int irq, void *devid)
43 {
44 struct fsl_sai *sai = (struct fsl_sai *)devid;
45 struct device *dev = &sai->pdev->dev;
46 u32 flags, xcsr, mask;
47 bool irq_none = true;
48
49 /*
50 * Both IRQ status bits and IRQ mask bits are in the xCSR but
51 * different shifts. And we here create a mask only for those
52 * IRQs that we activated.
53 */
54 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
55
56 /* Tx IRQ */
57 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
58 flags = xcsr & mask;
59
60 if (flags)
61 irq_none = false;
62 else
63 goto irq_rx;
64
65 if (flags & FSL_SAI_CSR_WSF)
66 dev_dbg(dev, "isr: Start of Tx word detected\n");
67
68 if (flags & FSL_SAI_CSR_SEF)
69 dev_warn(dev, "isr: Tx Frame sync error detected\n");
70
71 if (flags & FSL_SAI_CSR_FEF) {
72 dev_warn(dev, "isr: Transmit underrun detected\n");
73 /* FIFO reset for safety */
74 xcsr |= FSL_SAI_CSR_FR;
75 }
76
77 if (flags & FSL_SAI_CSR_FWF)
78 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
79
80 if (flags & FSL_SAI_CSR_FRF)
81 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
82
83 flags &= FSL_SAI_CSR_xF_W_MASK;
84 xcsr &= ~FSL_SAI_CSR_xF_MASK;
85
86 if (flags)
87 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
88
89 irq_rx:
90 /* Rx IRQ */
91 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
92 flags = xcsr & mask;
93
94 if (flags)
95 irq_none = false;
96 else
97 goto out;
98
99 if (flags & FSL_SAI_CSR_WSF)
100 dev_dbg(dev, "isr: Start of Rx word detected\n");
101
102 if (flags & FSL_SAI_CSR_SEF)
103 dev_warn(dev, "isr: Rx Frame sync error detected\n");
104
105 if (flags & FSL_SAI_CSR_FEF) {
106 dev_warn(dev, "isr: Receive overflow detected\n");
107 /* FIFO reset for safety */
108 xcsr |= FSL_SAI_CSR_FR;
109 }
110
111 if (flags & FSL_SAI_CSR_FWF)
112 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
113
114 if (flags & FSL_SAI_CSR_FRF)
115 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
116
117 flags &= FSL_SAI_CSR_xF_W_MASK;
118 xcsr &= ~FSL_SAI_CSR_xF_MASK;
119
120 if (flags)
121 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
122
123 out:
124 if (irq_none)
125 return IRQ_NONE;
126 else
127 return IRQ_HANDLED;
128 }
129
130 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
131 u32 rx_mask, int slots, int slot_width)
132 {
133 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
134
135 sai->slots = slots;
136 sai->slot_width = slot_width;
137
138 return 0;
139 }
140
141 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
142 int clk_id, unsigned int freq, int fsl_dir)
143 {
144 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
145 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
146 u32 val_cr2 = 0;
147
148 switch (clk_id) {
149 case FSL_SAI_CLK_BUS:
150 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
151 break;
152 case FSL_SAI_CLK_MAST1:
153 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
154 break;
155 case FSL_SAI_CLK_MAST2:
156 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
157 break;
158 case FSL_SAI_CLK_MAST3:
159 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
166 FSL_SAI_CR2_MSEL_MASK, val_cr2);
167
168 return 0;
169 }
170
171 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
172 int clk_id, unsigned int freq, int dir)
173 {
174 int ret;
175
176 if (dir == SND_SOC_CLOCK_IN)
177 return 0;
178
179 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
180 FSL_FMT_TRANSMITTER);
181 if (ret) {
182 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
183 return ret;
184 }
185
186 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
187 FSL_FMT_RECEIVER);
188 if (ret)
189 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
190
191 return ret;
192 }
193
194 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
195 unsigned int fmt, int fsl_dir)
196 {
197 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
198 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
199 u32 val_cr2 = 0, val_cr4 = 0;
200
201 if (!sai->is_lsb_first)
202 val_cr4 |= FSL_SAI_CR4_MF;
203
204 /* DAI mode */
205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
206 case SND_SOC_DAIFMT_I2S:
207 /*
208 * Frame low, 1clk before data, one word length for frame sync,
209 * frame sync starts one serial clock cycle earlier,
210 * that is, together with the last bit of the previous
211 * data word.
212 */
213 val_cr2 |= FSL_SAI_CR2_BCP;
214 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
215 break;
216 case SND_SOC_DAIFMT_LEFT_J:
217 /*
218 * Frame high, one word length for frame sync,
219 * frame sync asserts with the first bit of the frame.
220 */
221 val_cr2 |= FSL_SAI_CR2_BCP;
222 break;
223 case SND_SOC_DAIFMT_DSP_A:
224 /*
225 * Frame high, 1clk before data, one bit for frame sync,
226 * frame sync starts one serial clock cycle earlier,
227 * that is, together with the last bit of the previous
228 * data word.
229 */
230 val_cr2 |= FSL_SAI_CR2_BCP;
231 val_cr4 |= FSL_SAI_CR4_FSE;
232 sai->is_dsp_mode = true;
233 break;
234 case SND_SOC_DAIFMT_DSP_B:
235 /*
236 * Frame high, one bit for frame sync,
237 * frame sync asserts with the first bit of the frame.
238 */
239 val_cr2 |= FSL_SAI_CR2_BCP;
240 sai->is_dsp_mode = true;
241 break;
242 case SND_SOC_DAIFMT_RIGHT_J:
243 /* To be done */
244 default:
245 return -EINVAL;
246 }
247
248 /* DAI clock inversion */
249 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
250 case SND_SOC_DAIFMT_IB_IF:
251 /* Invert both clocks */
252 val_cr2 ^= FSL_SAI_CR2_BCP;
253 val_cr4 ^= FSL_SAI_CR4_FSP;
254 break;
255 case SND_SOC_DAIFMT_IB_NF:
256 /* Invert bit clock */
257 val_cr2 ^= FSL_SAI_CR2_BCP;
258 break;
259 case SND_SOC_DAIFMT_NB_IF:
260 /* Invert frame clock */
261 val_cr4 ^= FSL_SAI_CR4_FSP;
262 break;
263 case SND_SOC_DAIFMT_NB_NF:
264 /* Nothing to do for both normal cases */
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 /* DAI clock master masks */
271 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
272 case SND_SOC_DAIFMT_CBS_CFS:
273 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
274 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
275 break;
276 case SND_SOC_DAIFMT_CBM_CFM:
277 sai->is_slave_mode = true;
278 break;
279 case SND_SOC_DAIFMT_CBS_CFM:
280 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
281 break;
282 case SND_SOC_DAIFMT_CBM_CFS:
283 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
284 sai->is_slave_mode = true;
285 break;
286 default:
287 return -EINVAL;
288 }
289
290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
291 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
292 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
293 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
294 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
295
296 return 0;
297 }
298
299 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
300 {
301 int ret;
302
303 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
304 if (ret) {
305 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
306 return ret;
307 }
308
309 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
310 if (ret)
311 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
312
313 return ret;
314 }
315
316 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
317 {
318 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
319 unsigned long clk_rate;
320 u32 savediv = 0, ratio, savesub = freq;
321 u32 id;
322 int ret = 0;
323
324 /* Don't apply to slave mode */
325 if (sai->is_slave_mode)
326 return 0;
327
328 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
329 clk_rate = clk_get_rate(sai->mclk_clk[id]);
330 if (!clk_rate)
331 continue;
332
333 ratio = clk_rate / freq;
334
335 ret = clk_rate - ratio * freq;
336
337 /*
338 * Drop the source that can not be
339 * divided into the required rate.
340 */
341 if (ret != 0 && clk_rate / ret < 1000)
342 continue;
343
344 dev_dbg(dai->dev,
345 "ratio %d for freq %dHz based on clock %ldHz\n",
346 ratio, freq, clk_rate);
347
348 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
349 ratio /= 2;
350 else
351 continue;
352
353 if (ret < savesub) {
354 savediv = ratio;
355 sai->mclk_id[tx] = id;
356 savesub = ret;
357 }
358
359 if (ret == 0)
360 break;
361 }
362
363 if (savediv == 0) {
364 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
365 tx ? 'T' : 'R', freq);
366 return -EINVAL;
367 }
368
369 /*
370 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
371 * set TCR2 register for playback.
372 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
373 * and capture.
374 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
375 * and capture.
376 * 4) For Tx and Rx are both Synchronous with another SAI, we just
377 * ignore it.
378 */
379 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
380 (!tx && !sai->synchronous[RX])) {
381 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
382 FSL_SAI_CR2_MSEL_MASK,
383 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
384 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
385 FSL_SAI_CR2_DIV_MASK, savediv - 1);
386 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
387 (tx && !sai->synchronous[TX])) {
388 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
389 FSL_SAI_CR2_MSEL_MASK,
390 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
391 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
392 FSL_SAI_CR2_DIV_MASK, savediv - 1);
393 }
394
395 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
396 sai->mclk_id[tx], savediv, savesub);
397
398 return 0;
399 }
400
401 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
402 struct snd_pcm_hw_params *params,
403 struct snd_soc_dai *cpu_dai)
404 {
405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
406 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
407 unsigned int channels = params_channels(params);
408 u32 word_width = params_width(params);
409 u32 val_cr4 = 0, val_cr5 = 0;
410 u32 slots = (channels == 1) ? 2 : channels;
411 u32 slot_width = word_width;
412 int ret;
413
414 if (sai->slots)
415 slots = sai->slots;
416
417 if (sai->slot_width)
418 slot_width = sai->slot_width;
419
420 if (!sai->is_slave_mode) {
421 ret = fsl_sai_set_bclk(cpu_dai, tx,
422 slots * slot_width * params_rate(params));
423 if (ret)
424 return ret;
425
426 /* Do not enable the clock if it is already enabled */
427 if (!(sai->mclk_streams & BIT(substream->stream))) {
428 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
429 if (ret)
430 return ret;
431
432 sai->mclk_streams |= BIT(substream->stream);
433 }
434 }
435
436 if (!sai->is_dsp_mode)
437 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
438
439 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
440 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
441
442 if (sai->is_lsb_first)
443 val_cr5 |= FSL_SAI_CR5_FBT(0);
444 else
445 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
446
447 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
448
449 /*
450 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
451 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
452 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
453 * error.
454 */
455
456 if (!sai->is_slave_mode) {
457 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
458 regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
459 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
460 val_cr4);
461 regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
462 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
463 FSL_SAI_CR5_FBT_MASK, val_cr5);
464 regmap_write(sai->regmap, FSL_SAI_TMR,
465 ~0UL - ((1 << channels) - 1));
466 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
467 regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
468 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
469 val_cr4);
470 regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
471 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
472 FSL_SAI_CR5_FBT_MASK, val_cr5);
473 regmap_write(sai->regmap, FSL_SAI_RMR,
474 ~0UL - ((1 << channels) - 1));
475 }
476 }
477
478 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
479 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
480 val_cr4);
481 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
482 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
483 FSL_SAI_CR5_FBT_MASK, val_cr5);
484 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
485
486 return 0;
487 }
488
489 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
490 struct snd_soc_dai *cpu_dai)
491 {
492 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
493 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
494
495 if (!sai->is_slave_mode &&
496 sai->mclk_streams & BIT(substream->stream)) {
497 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
498 sai->mclk_streams &= ~BIT(substream->stream);
499 }
500
501 return 0;
502 }
503
504
505 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
506 struct snd_soc_dai *cpu_dai)
507 {
508 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
509 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
510 u32 xcsr, count = 100;
511
512 /*
513 * Asynchronous mode: Clear SYNC for both Tx and Rx.
514 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
515 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
516 */
517 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
518 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
519 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
520 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
521
522 /*
523 * It is recommended that the transmitter is the last enabled
524 * and the first disabled.
525 */
526 switch (cmd) {
527 case SNDRV_PCM_TRIGGER_START:
528 case SNDRV_PCM_TRIGGER_RESUME:
529 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
530 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
531 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
532
533 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
534 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
535 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
536 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
537
538 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
539 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
540 break;
541 case SNDRV_PCM_TRIGGER_STOP:
542 case SNDRV_PCM_TRIGGER_SUSPEND:
543 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
544 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
545 FSL_SAI_CSR_FRDE, 0);
546 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
547 FSL_SAI_CSR_xIE_MASK, 0);
548
549 /* Check if the opposite FRDE is also disabled */
550 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
551 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
552 /* Disable both directions and reset their FIFOs */
553 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
554 FSL_SAI_CSR_TERE, 0);
555 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
556 FSL_SAI_CSR_TERE, 0);
557
558 /* TERE will remain set till the end of current frame */
559 do {
560 udelay(10);
561 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
562 } while (--count && xcsr & FSL_SAI_CSR_TERE);
563
564 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
565 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
566 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
567 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
568
569 /*
570 * For sai master mode, after several open/close sai,
571 * there will be no frame clock, and can't recover
572 * anymore. Add software reset to fix this issue.
573 * This is a hardware bug, and will be fix in the
574 * next sai version.
575 */
576 if (!sai->is_slave_mode) {
577 /* Software Reset for both Tx and Rx */
578 regmap_write(sai->regmap,
579 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
580 regmap_write(sai->regmap,
581 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
582 /* Clear SR bit to finish the reset */
583 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
584 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
585 }
586 }
587 break;
588 default:
589 return -EINVAL;
590 }
591
592 return 0;
593 }
594
595 static int fsl_sai_startup(struct snd_pcm_substream *substream,
596 struct snd_soc_dai *cpu_dai)
597 {
598 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
599 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
600 struct device *dev = &sai->pdev->dev;
601 int ret;
602
603 ret = clk_prepare_enable(sai->bus_clk);
604 if (ret) {
605 dev_err(dev, "failed to enable bus clock: %d\n", ret);
606 return ret;
607 }
608
609 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
610 FSL_SAI_CR3_TRCE);
611
612 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
613 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
614
615 return ret;
616 }
617
618 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
619 struct snd_soc_dai *cpu_dai)
620 {
621 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
622 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
623
624 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
625
626 clk_disable_unprepare(sai->bus_clk);
627 }
628
629 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
630 .set_sysclk = fsl_sai_set_dai_sysclk,
631 .set_fmt = fsl_sai_set_dai_fmt,
632 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
633 .hw_params = fsl_sai_hw_params,
634 .hw_free = fsl_sai_hw_free,
635 .trigger = fsl_sai_trigger,
636 .startup = fsl_sai_startup,
637 .shutdown = fsl_sai_shutdown,
638 };
639
640 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
641 {
642 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
643
644 /* Software Reset for both Tx and Rx */
645 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
646 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
647 /* Clear SR bit to finish the reset */
648 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
649 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
650
651 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
652 FSL_SAI_MAXBURST_TX * 2);
653 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
654 FSL_SAI_MAXBURST_RX - 1);
655
656 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
657 &sai->dma_params_rx);
658
659 snd_soc_dai_set_drvdata(cpu_dai, sai);
660
661 return 0;
662 }
663
664 static struct snd_soc_dai_driver fsl_sai_dai = {
665 .probe = fsl_sai_dai_probe,
666 .playback = {
667 .stream_name = "CPU-Playback",
668 .channels_min = 1,
669 .channels_max = 2,
670 .rate_min = 8000,
671 .rate_max = 192000,
672 .rates = SNDRV_PCM_RATE_KNOT,
673 .formats = FSL_SAI_FORMATS,
674 },
675 .capture = {
676 .stream_name = "CPU-Capture",
677 .channels_min = 1,
678 .channels_max = 2,
679 .rate_min = 8000,
680 .rate_max = 192000,
681 .rates = SNDRV_PCM_RATE_KNOT,
682 .formats = FSL_SAI_FORMATS,
683 },
684 .ops = &fsl_sai_pcm_dai_ops,
685 };
686
687 static const struct snd_soc_component_driver fsl_component = {
688 .name = "fsl-sai",
689 };
690
691 static struct reg_default fsl_sai_reg_defaults[] = {
692 {FSL_SAI_TCR1, 0},
693 {FSL_SAI_TCR2, 0},
694 {FSL_SAI_TCR3, 0},
695 {FSL_SAI_TCR4, 0},
696 {FSL_SAI_TCR5, 0},
697 {FSL_SAI_TDR, 0},
698 {FSL_SAI_TMR, 0},
699 {FSL_SAI_RCR1, 0},
700 {FSL_SAI_RCR2, 0},
701 {FSL_SAI_RCR3, 0},
702 {FSL_SAI_RCR4, 0},
703 {FSL_SAI_RCR5, 0},
704 {FSL_SAI_RMR, 0},
705 };
706
707 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
708 {
709 switch (reg) {
710 case FSL_SAI_TCSR:
711 case FSL_SAI_TCR1:
712 case FSL_SAI_TCR2:
713 case FSL_SAI_TCR3:
714 case FSL_SAI_TCR4:
715 case FSL_SAI_TCR5:
716 case FSL_SAI_TFR:
717 case FSL_SAI_TMR:
718 case FSL_SAI_RCSR:
719 case FSL_SAI_RCR1:
720 case FSL_SAI_RCR2:
721 case FSL_SAI_RCR3:
722 case FSL_SAI_RCR4:
723 case FSL_SAI_RCR5:
724 case FSL_SAI_RDR:
725 case FSL_SAI_RFR:
726 case FSL_SAI_RMR:
727 return true;
728 default:
729 return false;
730 }
731 }
732
733 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
734 {
735 switch (reg) {
736 case FSL_SAI_TCSR:
737 case FSL_SAI_RCSR:
738 case FSL_SAI_TFR:
739 case FSL_SAI_RFR:
740 case FSL_SAI_RDR:
741 return true;
742 default:
743 return false;
744 }
745 }
746
747 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
748 {
749 switch (reg) {
750 case FSL_SAI_TCSR:
751 case FSL_SAI_TCR1:
752 case FSL_SAI_TCR2:
753 case FSL_SAI_TCR3:
754 case FSL_SAI_TCR4:
755 case FSL_SAI_TCR5:
756 case FSL_SAI_TDR:
757 case FSL_SAI_TMR:
758 case FSL_SAI_RCSR:
759 case FSL_SAI_RCR1:
760 case FSL_SAI_RCR2:
761 case FSL_SAI_RCR3:
762 case FSL_SAI_RCR4:
763 case FSL_SAI_RCR5:
764 case FSL_SAI_RMR:
765 return true;
766 default:
767 return false;
768 }
769 }
770
771 static const struct regmap_config fsl_sai_regmap_config = {
772 .reg_bits = 32,
773 .reg_stride = 4,
774 .val_bits = 32,
775
776 .max_register = FSL_SAI_RMR,
777 .reg_defaults = fsl_sai_reg_defaults,
778 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
779 .readable_reg = fsl_sai_readable_reg,
780 .volatile_reg = fsl_sai_volatile_reg,
781 .writeable_reg = fsl_sai_writeable_reg,
782 .cache_type = REGCACHE_FLAT,
783 };
784
785 static int fsl_sai_probe(struct platform_device *pdev)
786 {
787 struct device_node *np = pdev->dev.of_node;
788 struct fsl_sai *sai;
789 struct resource *res;
790 void __iomem *base;
791 char tmp[8];
792 int irq, ret, i;
793
794 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
795 if (!sai)
796 return -ENOMEM;
797
798 sai->pdev = pdev;
799
800 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
801 sai->sai_on_imx = true;
802
803 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
804
805 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
806 base = devm_ioremap_resource(&pdev->dev, res);
807 if (IS_ERR(base))
808 return PTR_ERR(base);
809
810 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
811 "bus", base, &fsl_sai_regmap_config);
812
813 /* Compatible with old DTB cases */
814 if (IS_ERR(sai->regmap))
815 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
816 "sai", base, &fsl_sai_regmap_config);
817 if (IS_ERR(sai->regmap)) {
818 dev_err(&pdev->dev, "regmap init failed\n");
819 return PTR_ERR(sai->regmap);
820 }
821
822 /* No error out for old DTB cases but only mark the clock NULL */
823 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
824 if (IS_ERR(sai->bus_clk)) {
825 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
826 PTR_ERR(sai->bus_clk));
827 sai->bus_clk = NULL;
828 }
829
830 sai->mclk_clk[0] = sai->bus_clk;
831 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
832 sprintf(tmp, "mclk%d", i);
833 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
834 if (IS_ERR(sai->mclk_clk[i])) {
835 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
836 i + 1, PTR_ERR(sai->mclk_clk[i]));
837 sai->mclk_clk[i] = NULL;
838 }
839 }
840
841 irq = platform_get_irq(pdev, 0);
842 if (irq < 0) {
843 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
844 return irq;
845 }
846
847 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
848 if (ret) {
849 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
850 return ret;
851 }
852
853 /* Sync Tx with Rx as default by following old DT binding */
854 sai->synchronous[RX] = true;
855 sai->synchronous[TX] = false;
856 fsl_sai_dai.symmetric_rates = 1;
857 fsl_sai_dai.symmetric_channels = 1;
858 fsl_sai_dai.symmetric_samplebits = 1;
859
860 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
861 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
862 /* error out if both synchronous and asynchronous are present */
863 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
864 return -EINVAL;
865 }
866
867 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
868 /* Sync Rx with Tx */
869 sai->synchronous[RX] = false;
870 sai->synchronous[TX] = true;
871 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
872 /* Discard all settings for asynchronous mode */
873 sai->synchronous[RX] = false;
874 sai->synchronous[TX] = false;
875 fsl_sai_dai.symmetric_rates = 0;
876 fsl_sai_dai.symmetric_channels = 0;
877 fsl_sai_dai.symmetric_samplebits = 0;
878 }
879
880 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
881 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
882 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
883 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
884
885 platform_set_drvdata(pdev, sai);
886
887 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
888 &fsl_sai_dai, 1);
889 if (ret)
890 return ret;
891
892 if (sai->sai_on_imx)
893 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
894 else
895 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
896 }
897
898 static const struct of_device_id fsl_sai_ids[] = {
899 { .compatible = "fsl,vf610-sai", },
900 { .compatible = "fsl,imx6sx-sai", },
901 { /* sentinel */ }
902 };
903 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
904
905 #ifdef CONFIG_PM_SLEEP
906 static int fsl_sai_suspend(struct device *dev)
907 {
908 struct fsl_sai *sai = dev_get_drvdata(dev);
909
910 regcache_cache_only(sai->regmap, true);
911 regcache_mark_dirty(sai->regmap);
912
913 return 0;
914 }
915
916 static int fsl_sai_resume(struct device *dev)
917 {
918 struct fsl_sai *sai = dev_get_drvdata(dev);
919
920 regcache_cache_only(sai->regmap, false);
921 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
922 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
923 usleep_range(1000, 2000);
924 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
925 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
926 return regcache_sync(sai->regmap);
927 }
928 #endif /* CONFIG_PM_SLEEP */
929
930 static const struct dev_pm_ops fsl_sai_pm_ops = {
931 SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
932 };
933
934 static struct platform_driver fsl_sai_driver = {
935 .probe = fsl_sai_probe,
936 .driver = {
937 .name = "fsl-sai",
938 .pm = &fsl_sai_pm_ops,
939 .of_match_table = fsl_sai_ids,
940 },
941 };
942 module_platform_driver(fsl_sai_driver);
943
944 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
945 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
946 MODULE_ALIAS("platform:fsl-sai");
947 MODULE_LICENSE("GPL");
Linux with added FPC-III support