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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / arch / mips / math-emu / cp1emu.c
blobbf0fc6b16ad9487648c0e38f945db0fd7f5461d6
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
50 #include <asm/fpu.h>
51
52 #include "ieee754.h"
53
54 /* Function which emulates a floating point instruction. */
55
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
57 mips_instruction);
58
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
61
62 /* Control registers */
63
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
66
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
69
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
72 FPU_CSR_COND0,
73 FPU_CSR_COND1,
74 FPU_CSR_COND2,
75 FPU_CSR_COND3,
76 FPU_CSR_COND4,
77 FPU_CSR_COND5,
78 FPU_CSR_COND6,
79 FPU_CSR_COND7
80 };
81
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
87
88 /*
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
92 */
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
94 {
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
97 int func, fmt, op;
98
99 switch (insn.mm_i_format.opcode) {
100 case mm_ldc132_op:
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
104 break;
105 case mm_lwc132_op:
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
109 break;
110 case mm_sdc132_op:
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
114 break;
115 case mm_swc132_op:
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
119 break;
120 case mm_pool32i_op:
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
128 } else
129 return SIGILL;
130 break;
131 case mm_pool32f_op:
132 switch (insn.mm_fp0_format.func) {
133 case mm_32f_01_op:
134 case mm_32f_11_op:
135 case mm_32f_02_op:
136 case mm_32f_12_op:
137 case mm_32f_41_op:
138 case mm_32f_51_op:
139 case mm_32f_42_op:
140 case mm_32f_52_op:
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
143 func = madd_s_op;
144 else if (op == mm_32f_11_op)
145 func = madd_d_op;
146 else if (op == mm_32f_02_op)
147 func = nmadd_s_op;
148 else if (op == mm_32f_12_op)
149 func = nmadd_d_op;
150 else if (op == mm_32f_41_op)
151 func = msub_s_op;
152 else if (op == mm_32f_51_op)
153 func = msub_d_op;
154 else if (op == mm_32f_42_op)
155 func = nmsub_s_op;
156 else
157 func = nmsub_d_op;
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
164 break;
165 case mm_32f_10_op:
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
169 func = ldxc1_op;
170 else if (op == mm_sdxc1_op)
171 func = sdxc1_op;
172 else if (op == mm_lwxc1_op)
173 func = lwxc1_op;
174 else if (op == mm_swxc1_op)
175 func = swxc1_op;
176
177 if (func != -1) {
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
186 } else
187 return SIGILL;
188 break;
189 case mm_32f_40_op:
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
192 op = 1;
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
194 op = 0;
195 if (op != -1) {
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
206 } else
207 return SIGILL;
208 break;
209 case mm_32f_60_op:
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
212 func = fadd_op;
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
214 func = fsub_op;
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
216 func = fmul_op;
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
218 func = fdiv_op;
219 if (func != -1) {
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
230 } else
231 return SIGILL;
232 break;
233 case mm_32f_70_op:
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
236 func = fmovn_op;
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
238 func = fmovz_op;
239 if (func != -1) {
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
250 } else
251 return SIGILL;
252 break;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
255 case mm_movf0_op:
256 case mm_movf1_op:
257 case mm_movt0_op:
258 case mm_movt1_op:
259 if ((insn.mm_fp1_format.op & 0x7f) ==
260 mm_movf0_op)
261 op = 0;
262 else
263 op = 1;
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
271 break;
272 case mm_fcvtd0_op:
273 case mm_fcvtd1_op:
274 case mm_fcvts0_op:
275 case mm_fcvts1_op:
276 if ((insn.mm_fp1_format.op & 0x7f) ==
277 mm_fcvtd0_op) {
278 func = fcvtd_op;
279 fmt = swl_format[insn.mm_fp3_format.fmt];
280 } else {
281 func = fcvts_op;
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
283 }
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
292 break;
293 case mm_fmov0_op:
294 case mm_fmov1_op:
295 case mm_fabs0_op:
296 case mm_fabs1_op:
297 case mm_fneg0_op:
298 case mm_fneg1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_fmov0_op)
301 func = fmov_op;
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
303 mm_fabs0_op)
304 func = fabs_op;
305 else
306 func = fneg_op;
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
316 break;
317 case mm_ffloorl_op:
318 case mm_ffloorw_op:
319 case mm_fceill_op:
320 case mm_fceilw_op:
321 case mm_ftruncl_op:
322 case mm_ftruncw_op:
323 case mm_froundl_op:
324 case mm_froundw_op:
325 case mm_fcvtl_op:
326 case mm_fcvtw_op:
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
328 func = ffloorl_op;
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
330 func = ffloor_op;
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
332 func = fceill_op;
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
334 func = fceil_op;
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
336 func = ftruncl_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
338 func = ftrunc_op;
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
340 func = froundl_op;
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
342 func = fround_op;
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
344 func = fcvtl_op;
345 else
346 func = fcvtw_op;
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
356 break;
357 case mm_frsqrt_op:
358 case mm_fsqrt_op:
359 case mm_frecip_op:
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
361 func = frsqrt_op;
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
363 func = fsqrt_op;
364 else
365 func = frecip_op;
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
375 break;
376 case mm_mfc1_op:
377 case mm_mtc1_op:
378 case mm_cfc1_op:
379 case mm_ctc1_op:
380 case mm_mfhc1_op:
381 case mm_mthc1_op:
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
383 op = mfc_op;
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
385 op = mtc_op;
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
387 op = cfc_op;
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
389 op = ctc_op;
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
391 op = mfhc_op;
392 else
393 op = mthc_op;
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
402 break;
403 default:
404 return SIGILL;
405 }
406 break;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
416 break;
417 default:
418 return SIGILL;
419 }
420 break;
421 default:
422 return SIGILL;
423 }
424
425 *insn_ptr = mips32_insn;
426 return 0;
427 }
428
429 /*
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
433 * modules.
434 */
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
437 {
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
439 unsigned int fcr31;
440 unsigned int bit = 0;
441
442 switch (insn.i_format.opcode) {
443 case spec_op:
444 switch (insn.r_format.func) {
445 case jalr_op:
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
449 /* Fall through */
450 case jr_op:
451 *contpc = regs->regs[insn.r_format.rs];
452 return 1;
453 }
454 break;
455 case bcond_op:
456 switch (insn.i_format.rt) {
457 case bltzal_op:
458 case bltzall_op:
459 regs->regs[31] = regs->cp0_epc +
460 dec_insn.pc_inc +
461 dec_insn.next_pc_inc;
462 /* Fall through */
463 case bltz_op:
464 case bltzl_op:
465 if ((long)regs->regs[insn.i_format.rs] < 0)
466 *contpc = regs->cp0_epc +
467 dec_insn.pc_inc +
468 (insn.i_format.simmediate << 2);
469 else
470 *contpc = regs->cp0_epc +
471 dec_insn.pc_inc +
472 dec_insn.next_pc_inc;
473 return 1;
474 case bgezal_op:
475 case bgezall_op:
476 regs->regs[31] = regs->cp0_epc +
477 dec_insn.pc_inc +
478 dec_insn.next_pc_inc;
479 /* Fall through */
480 case bgez_op:
481 case bgezl_op:
482 if ((long)regs->regs[insn.i_format.rs] >= 0)
483 *contpc = regs->cp0_epc +
484 dec_insn.pc_inc +
485 (insn.i_format.simmediate << 2);
486 else
487 *contpc = regs->cp0_epc +
488 dec_insn.pc_inc +
489 dec_insn.next_pc_inc;
490 return 1;
491 }
492 break;
493 case jalx_op:
494 set_isa16_mode(bit);
495 case jal_op:
496 regs->regs[31] = regs->cp0_epc +
497 dec_insn.pc_inc +
498 dec_insn.next_pc_inc;
499 /* Fall through */
500 case j_op:
501 *contpc = regs->cp0_epc + dec_insn.pc_inc;
502 *contpc >>= 28;
503 *contpc <<= 28;
504 *contpc |= (insn.j_format.target << 2);
505 /* Set microMIPS mode bit: XOR for jalx. */
506 *contpc ^= bit;
507 return 1;
508 case beq_op:
509 case beql_op:
510 if (regs->regs[insn.i_format.rs] ==
511 regs->regs[insn.i_format.rt])
512 *contpc = regs->cp0_epc +
513 dec_insn.pc_inc +
514 (insn.i_format.simmediate << 2);
515 else
516 *contpc = regs->cp0_epc +
517 dec_insn.pc_inc +
518 dec_insn.next_pc_inc;
519 return 1;
520 case bne_op:
521 case bnel_op:
522 if (regs->regs[insn.i_format.rs] !=
523 regs->regs[insn.i_format.rt])
524 *contpc = regs->cp0_epc +
525 dec_insn.pc_inc +
526 (insn.i_format.simmediate << 2);
527 else
528 *contpc = regs->cp0_epc +
529 dec_insn.pc_inc +
530 dec_insn.next_pc_inc;
531 return 1;
532 case blez_op:
533 case blezl_op:
534 if ((long)regs->regs[insn.i_format.rs] <= 0)
535 *contpc = regs->cp0_epc +
536 dec_insn.pc_inc +
537 (insn.i_format.simmediate << 2);
538 else
539 *contpc = regs->cp0_epc +
540 dec_insn.pc_inc +
541 dec_insn.next_pc_inc;
542 return 1;
543 case bgtz_op:
544 case bgtzl_op:
545 if ((long)regs->regs[insn.i_format.rs] > 0)
546 *contpc = regs->cp0_epc +
547 dec_insn.pc_inc +
548 (insn.i_format.simmediate << 2);
549 else
550 *contpc = regs->cp0_epc +
551 dec_insn.pc_inc +
552 dec_insn.next_pc_inc;
553 return 1;
554 #ifdef CONFIG_CPU_CAVIUM_OCTEON
555 case lwc2_op: /* This is bbit0 on Octeon */
556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
558 else
559 *contpc = regs->cp0_epc + 8;
560 return 1;
561 case ldc2_op: /* This is bbit032 on Octeon */
562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
564 else
565 *contpc = regs->cp0_epc + 8;
566 return 1;
567 case swc2_op: /* This is bbit1 on Octeon */
568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
570 else
571 *contpc = regs->cp0_epc + 8;
572 return 1;
573 case sdc2_op: /* This is bbit132 on Octeon */
574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
576 else
577 *contpc = regs->cp0_epc + 8;
578 return 1;
579 #endif
580 case cop0_op:
581 case cop1_op:
582 case cop2_op:
583 case cop1x_op:
584 if (insn.i_format.rs == bc_op) {
585 preempt_disable();
586 if (is_fpu_owner())
587 asm volatile(
588 ".set push\n"
589 "\t.set mips1\n"
590 "\tcfc1\t%0,$31\n"
591 "\t.set pop" : "=r" (fcr31));
592 else
593 fcr31 = current->thread.fpu.fcr31;
594 preempt_enable();
595
596 bit = (insn.i_format.rt >> 2);
597 bit += (bit != 0);
598 bit += 23;
599 switch (insn.i_format.rt & 3) {
600 case 0: /* bc1f */
601 case 2: /* bc1fl */
602 if (~fcr31 & (1 << bit))
603 *contpc = regs->cp0_epc +
604 dec_insn.pc_inc +
605 (insn.i_format.simmediate << 2);
606 else
607 *contpc = regs->cp0_epc +
608 dec_insn.pc_inc +
609 dec_insn.next_pc_inc;
610 return 1;
611 case 1: /* bc1t */
612 case 3: /* bc1tl */
613 if (fcr31 & (1 << bit))
614 *contpc = regs->cp0_epc +
615 dec_insn.pc_inc +
616 (insn.i_format.simmediate << 2);
617 else
618 *contpc = regs->cp0_epc +
619 dec_insn.pc_inc +
620 dec_insn.next_pc_inc;
621 return 1;
622 }
623 }
624 break;
625 }
626 return 0;
627 }
628
629 /*
630 * In the Linux kernel, we support selection of FPR format on the
631 * basis of the Status.FR bit. If an FPU is not present, the FR bit
632 * is hardwired to zero, which would imply a 32-bit FPU even for
633 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
634 * FPU emu is slow and bulky and optimizing this function offers fairly
635 * sizeable benefits so we try to be clever and make this function return
636 * a constant whenever possible, that is on 64-bit kernels without O32
637 * compatibility enabled and on 32-bit without 64-bit FPU support.
638 */
639 static inline int cop1_64bit(struct pt_regs *xcp)
640 {
641 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
642 return 1;
643 else if (config_enabled(CONFIG_32BIT) &&
644 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
645 return 0;
646
647 return !test_thread_flag(TIF_32BIT_FPREGS);
648 }
649
650 #define SIFROMREG(si, x) \
651 do { \
652 if (cop1_64bit(xcp)) \
653 (si) = get_fpr32(&ctx->fpr[x], 0); \
654 else \
655 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
656 } while (0)
657
658 #define SITOREG(si, x) \
659 do { \
660 if (cop1_64bit(xcp)) { \
661 unsigned i; \
662 set_fpr32(&ctx->fpr[x], 0, si); \
663 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
664 set_fpr32(&ctx->fpr[x], i, 0); \
665 } else { \
666 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
667 } \
668 } while (0)
669
670 #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
671
672 #define SITOHREG(si, x) \
673 do { \
674 unsigned i; \
675 set_fpr32(&ctx->fpr[x], 1, si); \
676 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
677 set_fpr32(&ctx->fpr[x], i, 0); \
678 } while (0)
679
680 #define DIFROMREG(di, x) \
681 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
682
683 #define DITOREG(di, x) \
684 do { \
685 unsigned fpr, i; \
686 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
687 set_fpr64(&ctx->fpr[fpr], 0, di); \
688 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
689 set_fpr64(&ctx->fpr[fpr], i, 0); \
690 } while (0)
691
692 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
693 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
694 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
695 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
696
697 /*
698 * Emulate the single floating point instruction pointed at by EPC.
699 * Two instructions if the instruction is in a branch delay slot.
700 */
701
702 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
703 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
704 {
705 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
706 unsigned int cond, cbit;
707 mips_instruction ir;
708 int likely, pc_inc;
709 u32 __user *wva;
710 u64 __user *dva;
711 u32 value;
712 u32 wval;
713 u64 dval;
714 int sig;
715
716 /*
717 * These are giving gcc a gentle hint about what to expect in
718 * dec_inst in order to do better optimization.
719 */
720 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
721 unreachable();
722
723 /* XXX NEC Vr54xx bug workaround */
724 if (delay_slot(xcp)) {
725 if (dec_insn.micro_mips_mode) {
726 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
727 clear_delay_slot(xcp);
728 } else {
729 if (!isBranchInstr(xcp, dec_insn, &contpc))
730 clear_delay_slot(xcp);
731 }
732 }
733
734 if (delay_slot(xcp)) {
735 /*
736 * The instruction to be emulated is in a branch delay slot
737 * which means that we have to emulate the branch instruction
738 * BEFORE we do the cop1 instruction.
739 *
740 * This branch could be a COP1 branch, but in that case we
741 * would have had a trap for that instruction, and would not
742 * come through this route.
743 *
744 * Linux MIPS branch emulator operates on context, updating the
745 * cp0_epc.
746 */
747 ir = dec_insn.next_insn; /* process delay slot instr */
748 pc_inc = dec_insn.next_pc_inc;
749 } else {
750 ir = dec_insn.insn; /* process current instr */
751 pc_inc = dec_insn.pc_inc;
752 }
753
754 /*
755 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
756 * instructions, we want to convert microMIPS FPU instructions
757 * into MIPS32 instructions so that we could reuse all of the
758 * FPU emulation code.
759 *
760 * NOTE: We cannot do this for branch instructions since they
761 * are not a subset. Example: Cannot emulate a 16-bit
762 * aligned target address with a MIPS32 instruction.
763 */
764 if (dec_insn.micro_mips_mode) {
765 /*
766 * If next instruction is a 16-bit instruction, then it
767 * it cannot be a FPU instruction. This could happen
768 * since we can be called for non-FPU instructions.
769 */
770 if ((pc_inc == 2) ||
771 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
772 == SIGILL))
773 return SIGILL;
774 }
775
776 emul:
777 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
778 MIPS_FPU_EMU_INC_STATS(emulated);
779 switch (MIPSInst_OPCODE(ir)) {
780 case ldc1_op:
781 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
782 MIPSInst_SIMM(ir));
783 MIPS_FPU_EMU_INC_STATS(loads);
784
785 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
786 MIPS_FPU_EMU_INC_STATS(errors);
787 *fault_addr = dva;
788 return SIGBUS;
789 }
790 if (__get_user(dval, dva)) {
791 MIPS_FPU_EMU_INC_STATS(errors);
792 *fault_addr = dva;
793 return SIGSEGV;
794 }
795 DITOREG(dval, MIPSInst_RT(ir));
796 break;
797
798 case sdc1_op:
799 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
800 MIPSInst_SIMM(ir));
801 MIPS_FPU_EMU_INC_STATS(stores);
802 DIFROMREG(dval, MIPSInst_RT(ir));
803 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
804 MIPS_FPU_EMU_INC_STATS(errors);
805 *fault_addr = dva;
806 return SIGBUS;
807 }
808 if (__put_user(dval, dva)) {
809 MIPS_FPU_EMU_INC_STATS(errors);
810 *fault_addr = dva;
811 return SIGSEGV;
812 }
813 break;
814
815 case lwc1_op:
816 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
817 MIPSInst_SIMM(ir));
818 MIPS_FPU_EMU_INC_STATS(loads);
819 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
820 MIPS_FPU_EMU_INC_STATS(errors);
821 *fault_addr = wva;
822 return SIGBUS;
823 }
824 if (__get_user(wval, wva)) {
825 MIPS_FPU_EMU_INC_STATS(errors);
826 *fault_addr = wva;
827 return SIGSEGV;
828 }
829 SITOREG(wval, MIPSInst_RT(ir));
830 break;
831
832 case swc1_op:
833 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
834 MIPSInst_SIMM(ir));
835 MIPS_FPU_EMU_INC_STATS(stores);
836 SIFROMREG(wval, MIPSInst_RT(ir));
837 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
838 MIPS_FPU_EMU_INC_STATS(errors);
839 *fault_addr = wva;
840 return SIGBUS;
841 }
842 if (__put_user(wval, wva)) {
843 MIPS_FPU_EMU_INC_STATS(errors);
844 *fault_addr = wva;
845 return SIGSEGV;
846 }
847 break;
848
849 case cop1_op:
850 switch (MIPSInst_RS(ir)) {
851 case dmfc_op:
852 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
853 return SIGILL;
854
855 /* copregister fs -> gpr[rt] */
856 if (MIPSInst_RT(ir) != 0) {
857 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
858 MIPSInst_RD(ir));
859 }
860 break;
861
862 case dmtc_op:
863 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
864 return SIGILL;
865
866 /* copregister fs <- rt */
867 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
868 break;
869
870 case mfhc_op:
871 if (!cpu_has_mips_r2)
872 goto sigill;
873
874 /* copregister rd -> gpr[rt] */
875 if (MIPSInst_RT(ir) != 0) {
876 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
877 MIPSInst_RD(ir));
878 }
879 break;
880
881 case mthc_op:
882 if (!cpu_has_mips_r2)
883 goto sigill;
884
885 /* copregister rd <- gpr[rt] */
886 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
887 break;
888
889 case mfc_op:
890 /* copregister rd -> gpr[rt] */
891 if (MIPSInst_RT(ir) != 0) {
892 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
893 MIPSInst_RD(ir));
894 }
895 break;
896
897 case mtc_op:
898 /* copregister rd <- rt */
899 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
900 break;
901
902 case cfc_op:
903 /* cop control register rd -> gpr[rt] */
904 if (MIPSInst_RD(ir) == FPCREG_CSR) {
905 value = ctx->fcr31;
906 value = (value & ~FPU_CSR_RM) | modeindex(value);
907 pr_debug("%p gpr[%d]<-csr=%08x\n",
908 (void *) (xcp->cp0_epc),
909 MIPSInst_RT(ir), value);
910 }
911 else if (MIPSInst_RD(ir) == FPCREG_RID)
912 value = 0;
913 else
914 value = 0;
915 if (MIPSInst_RT(ir))
916 xcp->regs[MIPSInst_RT(ir)] = value;
917 break;
918
919 case ctc_op:
920 /* copregister rd <- rt */
921 if (MIPSInst_RT(ir) == 0)
922 value = 0;
923 else
924 value = xcp->regs[MIPSInst_RT(ir)];
925
926 /* we only have one writable control reg
927 */
928 if (MIPSInst_RD(ir) == FPCREG_CSR) {
929 pr_debug("%p gpr[%d]->csr=%08x\n",
930 (void *) (xcp->cp0_epc),
931 MIPSInst_RT(ir), value);
932
933 /*
934 * Don't write reserved bits,
935 * and convert to ieee library modes
936 */
937 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
938 modeindex(value);
939 }
940 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
941 return SIGFPE;
942 }
943 break;
944
945 case bc_op:
946 if (delay_slot(xcp))
947 return SIGILL;
948
949 if (cpu_has_mips_4_5_r)
950 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
951 else
952 cbit = FPU_CSR_COND;
953 cond = ctx->fcr31 & cbit;
954
955 likely = 0;
956 switch (MIPSInst_RT(ir) & 3) {
957 case bcfl_op:
958 likely = 1;
959 case bcf_op:
960 cond = !cond;
961 break;
962 case bctl_op:
963 likely = 1;
964 case bct_op:
965 break;
966 default:
967 /* thats an illegal instruction */
968 return SIGILL;
969 }
970
971 set_delay_slot(xcp);
972 if (cond) {
973 /*
974 * Branch taken: emulate dslot instruction
975 */
976 xcp->cp0_epc += dec_insn.pc_inc;
977
978 contpc = MIPSInst_SIMM(ir);
979 ir = dec_insn.next_insn;
980 if (dec_insn.micro_mips_mode) {
981 contpc = (xcp->cp0_epc + (contpc << 1));
982
983 /* If 16-bit instruction, not FPU. */
984 if ((dec_insn.next_pc_inc == 2) ||
985 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
986
987 /*
988 * Since this instruction will
989 * be put on the stack with
990 * 32-bit words, get around
991 * this problem by putting a
992 * NOP16 as the second one.
993 */
994 if (dec_insn.next_pc_inc == 2)
995 ir = (ir & (~0xffff)) | MM_NOP16;
996
997 /*
998 * Single step the non-CP1
999 * instruction in the dslot.
1000 */
1001 return mips_dsemul(xcp, ir, contpc);
1002 }
1003 } else
1004 contpc = (xcp->cp0_epc + (contpc << 2));
1005
1006 switch (MIPSInst_OPCODE(ir)) {
1007 case lwc1_op:
1008 goto emul;
1009
1010 case swc1_op:
1011 goto emul;
1012
1013 case ldc1_op:
1014 case sdc1_op:
1015 if (cpu_has_mips_2_3_4_5 ||
1016 cpu_has_mips64)
1017 goto emul;
1018
1019 return SIGILL;
1020 goto emul;
1021
1022 case cop1_op:
1023 goto emul;
1024
1025 case cop1x_op:
1026 if (cpu_has_mips_4_5 || cpu_has_mips64)
1027 /* its one of ours */
1028 goto emul;
1029
1030 return SIGILL;
1031
1032 case spec_op:
1033 if (!cpu_has_mips_4_5_r)
1034 return SIGILL;
1035
1036 if (MIPSInst_FUNC(ir) == movc_op)
1037 goto emul;
1038 break;
1039 }
1040
1041 /*
1042 * Single step the non-cp1
1043 * instruction in the dslot
1044 */
1045 return mips_dsemul(xcp, ir, contpc);
1046 } else if (likely) { /* branch not taken */
1047 /*
1048 * branch likely nullifies
1049 * dslot if not taken
1050 */
1051 xcp->cp0_epc += dec_insn.pc_inc;
1052 contpc += dec_insn.pc_inc;
1053 /*
1054 * else continue & execute
1055 * dslot as normal insn
1056 */
1057 }
1058 break;
1059
1060 default:
1061 if (!(MIPSInst_RS(ir) & 0x10))
1062 return SIGILL;
1063
1064 /* a real fpu computation instruction */
1065 if ((sig = fpu_emu(xcp, ctx, ir)))
1066 return sig;
1067 }
1068 break;
1069
1070 case cop1x_op:
1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64)
1072 return SIGILL;
1073
1074 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1075 if (sig)
1076 return sig;
1077 break;
1078
1079 case spec_op:
1080 if (!cpu_has_mips_4_5_r)
1081 return SIGILL;
1082
1083 if (MIPSInst_FUNC(ir) != movc_op)
1084 return SIGILL;
1085 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1086 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1087 xcp->regs[MIPSInst_RD(ir)] =
1088 xcp->regs[MIPSInst_RS(ir)];
1089 break;
1090 default:
1091 sigill:
1092 return SIGILL;
1093 }
1094
1095 /* we did it !! */
1096 xcp->cp0_epc = contpc;
1097 clear_delay_slot(xcp);
1098
1099 return 0;
1100 }
1101
1102 /*
1103 * Conversion table from MIPS compare ops 48-63
1104 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1105 */
1106 static const unsigned char cmptab[8] = {
1107 0, /* cmp_0 (sig) cmp_sf */
1108 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1109 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1110 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1111 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1112 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1113 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1114 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1115 };
1116
1117
1118 /*
1119 * Additional MIPS4 instructions
1120 */
1121
1122 #define DEF3OP(name, p, f1, f2, f3) \
1123 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1124 union ieee754##p s, union ieee754##p t) \
1125 { \
1126 struct _ieee754_csr ieee754_csr_save; \
1127 s = f1(s, t); \
1128 ieee754_csr_save = ieee754_csr; \
1129 s = f2(s, r); \
1130 ieee754_csr_save.cx |= ieee754_csr.cx; \
1131 ieee754_csr_save.sx |= ieee754_csr.sx; \
1132 s = f3(s); \
1133 ieee754_csr.cx |= ieee754_csr_save.cx; \
1134 ieee754_csr.sx |= ieee754_csr_save.sx; \
1135 return s; \
1136 }
1137
1138 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1139 {
1140 return ieee754dp_div(ieee754dp_one(0), d);
1141 }
1142
1143 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1144 {
1145 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1146 }
1147
1148 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1149 {
1150 return ieee754sp_div(ieee754sp_one(0), s);
1151 }
1152
1153 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1154 {
1155 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1156 }
1157
1158 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1159 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1160 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1161 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1162 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1163 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1164 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1165 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1166
1167 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1168 mips_instruction ir, void *__user *fault_addr)
1169 {
1170 unsigned rcsr = 0; /* resulting csr */
1171
1172 MIPS_FPU_EMU_INC_STATS(cp1xops);
1173
1174 switch (MIPSInst_FMA_FFMT(ir)) {
1175 case s_fmt:{ /* 0 */
1176
1177 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1178 union ieee754sp fd, fr, fs, ft;
1179 u32 __user *va;
1180 u32 val;
1181
1182 switch (MIPSInst_FUNC(ir)) {
1183 case lwxc1_op:
1184 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1185 xcp->regs[MIPSInst_FT(ir)]);
1186
1187 MIPS_FPU_EMU_INC_STATS(loads);
1188 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1189 MIPS_FPU_EMU_INC_STATS(errors);
1190 *fault_addr = va;
1191 return SIGBUS;
1192 }
1193 if (__get_user(val, va)) {
1194 MIPS_FPU_EMU_INC_STATS(errors);
1195 *fault_addr = va;
1196 return SIGSEGV;
1197 }
1198 SITOREG(val, MIPSInst_FD(ir));
1199 break;
1200
1201 case swxc1_op:
1202 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1203 xcp->regs[MIPSInst_FT(ir)]);
1204
1205 MIPS_FPU_EMU_INC_STATS(stores);
1206
1207 SIFROMREG(val, MIPSInst_FS(ir));
1208 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1209 MIPS_FPU_EMU_INC_STATS(errors);
1210 *fault_addr = va;
1211 return SIGBUS;
1212 }
1213 if (put_user(val, va)) {
1214 MIPS_FPU_EMU_INC_STATS(errors);
1215 *fault_addr = va;
1216 return SIGSEGV;
1217 }
1218 break;
1219
1220 case madd_s_op:
1221 handler = fpemu_sp_madd;
1222 goto scoptop;
1223 case msub_s_op:
1224 handler = fpemu_sp_msub;
1225 goto scoptop;
1226 case nmadd_s_op:
1227 handler = fpemu_sp_nmadd;
1228 goto scoptop;
1229 case nmsub_s_op:
1230 handler = fpemu_sp_nmsub;
1231 goto scoptop;
1232
1233 scoptop:
1234 SPFROMREG(fr, MIPSInst_FR(ir));
1235 SPFROMREG(fs, MIPSInst_FS(ir));
1236 SPFROMREG(ft, MIPSInst_FT(ir));
1237 fd = (*handler) (fr, fs, ft);
1238 SPTOREG(fd, MIPSInst_FD(ir));
1239
1240 copcsr:
1241 if (ieee754_cxtest(IEEE754_INEXACT)) {
1242 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1243 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1244 }
1245 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1246 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1247 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1248 }
1249 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1250 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1251 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1252 }
1253 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1254 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1255 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1256 }
1257
1258 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1259 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1260 /*printk ("SIGFPE: FPU csr = %08x\n",
1261 ctx->fcr31); */
1262 return SIGFPE;
1263 }
1264
1265 break;
1266
1267 default:
1268 return SIGILL;
1269 }
1270 break;
1271 }
1272
1273 case d_fmt:{ /* 1 */
1274 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1275 union ieee754dp fd, fr, fs, ft;
1276 u64 __user *va;
1277 u64 val;
1278
1279 switch (MIPSInst_FUNC(ir)) {
1280 case ldxc1_op:
1281 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1282 xcp->regs[MIPSInst_FT(ir)]);
1283
1284 MIPS_FPU_EMU_INC_STATS(loads);
1285 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1286 MIPS_FPU_EMU_INC_STATS(errors);
1287 *fault_addr = va;
1288 return SIGBUS;
1289 }
1290 if (__get_user(val, va)) {
1291 MIPS_FPU_EMU_INC_STATS(errors);
1292 *fault_addr = va;
1293 return SIGSEGV;
1294 }
1295 DITOREG(val, MIPSInst_FD(ir));
1296 break;
1297
1298 case sdxc1_op:
1299 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1300 xcp->regs[MIPSInst_FT(ir)]);
1301
1302 MIPS_FPU_EMU_INC_STATS(stores);
1303 DIFROMREG(val, MIPSInst_FS(ir));
1304 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1305 MIPS_FPU_EMU_INC_STATS(errors);
1306 *fault_addr = va;
1307 return SIGBUS;
1308 }
1309 if (__put_user(val, va)) {
1310 MIPS_FPU_EMU_INC_STATS(errors);
1311 *fault_addr = va;
1312 return SIGSEGV;
1313 }
1314 break;
1315
1316 case madd_d_op:
1317 handler = fpemu_dp_madd;
1318 goto dcoptop;
1319 case msub_d_op:
1320 handler = fpemu_dp_msub;
1321 goto dcoptop;
1322 case nmadd_d_op:
1323 handler = fpemu_dp_nmadd;
1324 goto dcoptop;
1325 case nmsub_d_op:
1326 handler = fpemu_dp_nmsub;
1327 goto dcoptop;
1328
1329 dcoptop:
1330 DPFROMREG(fr, MIPSInst_FR(ir));
1331 DPFROMREG(fs, MIPSInst_FS(ir));
1332 DPFROMREG(ft, MIPSInst_FT(ir));
1333 fd = (*handler) (fr, fs, ft);
1334 DPTOREG(fd, MIPSInst_FD(ir));
1335 goto copcsr;
1336
1337 default:
1338 return SIGILL;
1339 }
1340 break;
1341 }
1342
1343 case 0x3:
1344 if (MIPSInst_FUNC(ir) != pfetch_op)
1345 return SIGILL;
1346
1347 /* ignore prefx operation */
1348 break;
1349
1350 default:
1351 return SIGILL;
1352 }
1353
1354 return 0;
1355 }
1356
1357
1358
1359 /*
1360 * Emulate a single COP1 arithmetic instruction.
1361 */
1362 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1363 mips_instruction ir)
1364 {
1365 int rfmt; /* resulting format */
1366 unsigned rcsr = 0; /* resulting csr */
1367 unsigned int oldrm;
1368 unsigned int cbit;
1369 unsigned cond;
1370 union {
1371 union ieee754dp d;
1372 union ieee754sp s;
1373 int w;
1374 s64 l;
1375 } rv; /* resulting value */
1376 u64 bits;
1377
1378 MIPS_FPU_EMU_INC_STATS(cp1ops);
1379 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1380 case s_fmt: { /* 0 */
1381 union {
1382 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1383 union ieee754sp(*u) (union ieee754sp);
1384 } handler;
1385 union ieee754sp fs, ft;
1386
1387 switch (MIPSInst_FUNC(ir)) {
1388 /* binary ops */
1389 case fadd_op:
1390 handler.b = ieee754sp_add;
1391 goto scopbop;
1392 case fsub_op:
1393 handler.b = ieee754sp_sub;
1394 goto scopbop;
1395 case fmul_op:
1396 handler.b = ieee754sp_mul;
1397 goto scopbop;
1398 case fdiv_op:
1399 handler.b = ieee754sp_div;
1400 goto scopbop;
1401
1402 /* unary ops */
1403 case fsqrt_op:
1404 if (!cpu_has_mips_4_5_r)
1405 return SIGILL;
1406
1407 handler.u = ieee754sp_sqrt;
1408 goto scopuop;
1409
1410 /*
1411 * Note that on some MIPS IV implementations such as the
1412 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1413 * achieve full IEEE-754 accuracy - however this emulator does.
1414 */
1415 case frsqrt_op:
1416 if (!cpu_has_mips_4_5_r2)
1417 return SIGILL;
1418
1419 handler.u = fpemu_sp_rsqrt;
1420 goto scopuop;
1421
1422 case frecip_op:
1423 if (!cpu_has_mips_4_5_r2)
1424 return SIGILL;
1425
1426 handler.u = fpemu_sp_recip;
1427 goto scopuop;
1428
1429 case fmovc_op:
1430 if (!cpu_has_mips_4_5_r)
1431 return SIGILL;
1432
1433 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1434 if (((ctx->fcr31 & cond) != 0) !=
1435 ((MIPSInst_FT(ir) & 1) != 0))
1436 return 0;
1437 SPFROMREG(rv.s, MIPSInst_FS(ir));
1438 break;
1439
1440 case fmovz_op:
1441 if (!cpu_has_mips_4_5_r)
1442 return SIGILL;
1443
1444 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1445 return 0;
1446 SPFROMREG(rv.s, MIPSInst_FS(ir));
1447 break;
1448
1449 case fmovn_op:
1450 if (!cpu_has_mips_4_5_r)
1451 return SIGILL;
1452
1453 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1454 return 0;
1455 SPFROMREG(rv.s, MIPSInst_FS(ir));
1456 break;
1457
1458 case fabs_op:
1459 handler.u = ieee754sp_abs;
1460 goto scopuop;
1461
1462 case fneg_op:
1463 handler.u = ieee754sp_neg;
1464 goto scopuop;
1465
1466 case fmov_op:
1467 /* an easy one */
1468 SPFROMREG(rv.s, MIPSInst_FS(ir));
1469 goto copcsr;
1470
1471 /* binary op on handler */
1472 scopbop:
1473 SPFROMREG(fs, MIPSInst_FS(ir));
1474 SPFROMREG(ft, MIPSInst_FT(ir));
1475
1476 rv.s = (*handler.b) (fs, ft);
1477 goto copcsr;
1478 scopuop:
1479 SPFROMREG(fs, MIPSInst_FS(ir));
1480 rv.s = (*handler.u) (fs);
1481 goto copcsr;
1482 copcsr:
1483 if (ieee754_cxtest(IEEE754_INEXACT)) {
1484 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1485 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1486 }
1487 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1488 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1489 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1490 }
1491 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1492 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1493 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1494 }
1495 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1496 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1497 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1498 }
1499 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1500 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1501 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1502 }
1503 break;
1504
1505 /* unary conv ops */
1506 case fcvts_op:
1507 return SIGILL; /* not defined */
1508
1509 case fcvtd_op:
1510 SPFROMREG(fs, MIPSInst_FS(ir));
1511 rv.d = ieee754dp_fsp(fs);
1512 rfmt = d_fmt;
1513 goto copcsr;
1514
1515 case fcvtw_op:
1516 SPFROMREG(fs, MIPSInst_FS(ir));
1517 rv.w = ieee754sp_tint(fs);
1518 rfmt = w_fmt;
1519 goto copcsr;
1520
1521 case fround_op:
1522 case ftrunc_op:
1523 case fceil_op:
1524 case ffloor_op:
1525 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1526 return SIGILL;
1527
1528 oldrm = ieee754_csr.rm;
1529 SPFROMREG(fs, MIPSInst_FS(ir));
1530 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1531 rv.w = ieee754sp_tint(fs);
1532 ieee754_csr.rm = oldrm;
1533 rfmt = w_fmt;
1534 goto copcsr;
1535
1536 case fcvtl_op:
1537 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1538 return SIGILL;
1539
1540 SPFROMREG(fs, MIPSInst_FS(ir));
1541 rv.l = ieee754sp_tlong(fs);
1542 rfmt = l_fmt;
1543 goto copcsr;
1544
1545 case froundl_op:
1546 case ftruncl_op:
1547 case fceill_op:
1548 case ffloorl_op:
1549 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1550 return SIGILL;
1551
1552 oldrm = ieee754_csr.rm;
1553 SPFROMREG(fs, MIPSInst_FS(ir));
1554 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1555 rv.l = ieee754sp_tlong(fs);
1556 ieee754_csr.rm = oldrm;
1557 rfmt = l_fmt;
1558 goto copcsr;
1559
1560 default:
1561 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1562 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1563 union ieee754sp fs, ft;
1564
1565 SPFROMREG(fs, MIPSInst_FS(ir));
1566 SPFROMREG(ft, MIPSInst_FT(ir));
1567 rv.w = ieee754sp_cmp(fs, ft,
1568 cmptab[cmpop & 0x7], cmpop & 0x8);
1569 rfmt = -1;
1570 if ((cmpop & 0x8) && ieee754_cxtest
1571 (IEEE754_INVALID_OPERATION))
1572 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1573 else
1574 goto copcsr;
1575
1576 } else
1577 return SIGILL;
1578 break;
1579 }
1580 break;
1581 }
1582
1583 case d_fmt: {
1584 union ieee754dp fs, ft;
1585 union {
1586 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1587 union ieee754dp(*u) (union ieee754dp);
1588 } handler;
1589
1590 switch (MIPSInst_FUNC(ir)) {
1591 /* binary ops */
1592 case fadd_op:
1593 handler.b = ieee754dp_add;
1594 goto dcopbop;
1595 case fsub_op:
1596 handler.b = ieee754dp_sub;
1597 goto dcopbop;
1598 case fmul_op:
1599 handler.b = ieee754dp_mul;
1600 goto dcopbop;
1601 case fdiv_op:
1602 handler.b = ieee754dp_div;
1603 goto dcopbop;
1604
1605 /* unary ops */
1606 case fsqrt_op:
1607 if (!cpu_has_mips_2_3_4_5_r)
1608 return SIGILL;
1609
1610 handler.u = ieee754dp_sqrt;
1611 goto dcopuop;
1612 /*
1613 * Note that on some MIPS IV implementations such as the
1614 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1615 * achieve full IEEE-754 accuracy - however this emulator does.
1616 */
1617 case frsqrt_op:
1618 if (!cpu_has_mips_4_5_r2)
1619 return SIGILL;
1620
1621 handler.u = fpemu_dp_rsqrt;
1622 goto dcopuop;
1623 case frecip_op:
1624 if (!cpu_has_mips_4_5_r2)
1625 return SIGILL;
1626
1627 handler.u = fpemu_dp_recip;
1628 goto dcopuop;
1629 case fmovc_op:
1630 if (!cpu_has_mips_4_5_r)
1631 return SIGILL;
1632
1633 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1634 if (((ctx->fcr31 & cond) != 0) !=
1635 ((MIPSInst_FT(ir) & 1) != 0))
1636 return 0;
1637 DPFROMREG(rv.d, MIPSInst_FS(ir));
1638 break;
1639 case fmovz_op:
1640 if (!cpu_has_mips_4_5_r)
1641 return SIGILL;
1642
1643 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1644 return 0;
1645 DPFROMREG(rv.d, MIPSInst_FS(ir));
1646 break;
1647 case fmovn_op:
1648 if (!cpu_has_mips_4_5_r)
1649 return SIGILL;
1650
1651 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1652 return 0;
1653 DPFROMREG(rv.d, MIPSInst_FS(ir));
1654 break;
1655 case fabs_op:
1656 handler.u = ieee754dp_abs;
1657 goto dcopuop;
1658
1659 case fneg_op:
1660 handler.u = ieee754dp_neg;
1661 goto dcopuop;
1662
1663 case fmov_op:
1664 /* an easy one */
1665 DPFROMREG(rv.d, MIPSInst_FS(ir));
1666 goto copcsr;
1667
1668 /* binary op on handler */
1669 dcopbop:
1670 DPFROMREG(fs, MIPSInst_FS(ir));
1671 DPFROMREG(ft, MIPSInst_FT(ir));
1672
1673 rv.d = (*handler.b) (fs, ft);
1674 goto copcsr;
1675 dcopuop:
1676 DPFROMREG(fs, MIPSInst_FS(ir));
1677 rv.d = (*handler.u) (fs);
1678 goto copcsr;
1679
1680 /*
1681 * unary conv ops
1682 */
1683 case fcvts_op:
1684 DPFROMREG(fs, MIPSInst_FS(ir));
1685 rv.s = ieee754sp_fdp(fs);
1686 rfmt = s_fmt;
1687 goto copcsr;
1688
1689 case fcvtd_op:
1690 return SIGILL; /* not defined */
1691
1692 case fcvtw_op:
1693 DPFROMREG(fs, MIPSInst_FS(ir));
1694 rv.w = ieee754dp_tint(fs); /* wrong */
1695 rfmt = w_fmt;
1696 goto copcsr;
1697
1698 case fround_op:
1699 case ftrunc_op:
1700 case fceil_op:
1701 case ffloor_op:
1702 if (!cpu_has_mips_2_3_4_5_r)
1703 return SIGILL;
1704
1705 oldrm = ieee754_csr.rm;
1706 DPFROMREG(fs, MIPSInst_FS(ir));
1707 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1708 rv.w = ieee754dp_tint(fs);
1709 ieee754_csr.rm = oldrm;
1710 rfmt = w_fmt;
1711 goto copcsr;
1712
1713 case fcvtl_op:
1714 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1715 return SIGILL;
1716
1717 DPFROMREG(fs, MIPSInst_FS(ir));
1718 rv.l = ieee754dp_tlong(fs);
1719 rfmt = l_fmt;
1720 goto copcsr;
1721
1722 case froundl_op:
1723 case ftruncl_op:
1724 case fceill_op:
1725 case ffloorl_op:
1726 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1727 return SIGILL;
1728
1729 oldrm = ieee754_csr.rm;
1730 DPFROMREG(fs, MIPSInst_FS(ir));
1731 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1732 rv.l = ieee754dp_tlong(fs);
1733 ieee754_csr.rm = oldrm;
1734 rfmt = l_fmt;
1735 goto copcsr;
1736
1737 default:
1738 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1739 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1740 union ieee754dp fs, ft;
1741
1742 DPFROMREG(fs, MIPSInst_FS(ir));
1743 DPFROMREG(ft, MIPSInst_FT(ir));
1744 rv.w = ieee754dp_cmp(fs, ft,
1745 cmptab[cmpop & 0x7], cmpop & 0x8);
1746 rfmt = -1;
1747 if ((cmpop & 0x8)
1748 &&
1749 ieee754_cxtest
1750 (IEEE754_INVALID_OPERATION))
1751 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1752 else
1753 goto copcsr;
1754
1755 }
1756 else {
1757 return SIGILL;
1758 }
1759 break;
1760 }
1761 break;
1762
1763 case w_fmt:
1764 switch (MIPSInst_FUNC(ir)) {
1765 case fcvts_op:
1766 /* convert word to single precision real */
1767 SPFROMREG(fs, MIPSInst_FS(ir));
1768 rv.s = ieee754sp_fint(fs.bits);
1769 rfmt = s_fmt;
1770 goto copcsr;
1771 case fcvtd_op:
1772 /* convert word to double precision real */
1773 SPFROMREG(fs, MIPSInst_FS(ir));
1774 rv.d = ieee754dp_fint(fs.bits);
1775 rfmt = d_fmt;
1776 goto copcsr;
1777 default:
1778 return SIGILL;
1779 }
1780 break;
1781 }
1782
1783 case l_fmt:
1784
1785 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1786 return SIGILL;
1787
1788 DIFROMREG(bits, MIPSInst_FS(ir));
1789
1790 switch (MIPSInst_FUNC(ir)) {
1791 case fcvts_op:
1792 /* convert long to single precision real */
1793 rv.s = ieee754sp_flong(bits);
1794 rfmt = s_fmt;
1795 goto copcsr;
1796 case fcvtd_op:
1797 /* convert long to double precision real */
1798 rv.d = ieee754dp_flong(bits);
1799 rfmt = d_fmt;
1800 goto copcsr;
1801 default:
1802 return SIGILL;
1803 }
1804 break;
1805
1806 default:
1807 return SIGILL;
1808 }
1809
1810 /*
1811 * Update the fpu CSR register for this operation.
1812 * If an exception is required, generate a tidy SIGFPE exception,
1813 * without updating the result register.
1814 * Note: cause exception bits do not accumulate, they are rewritten
1815 * for each op; only the flag/sticky bits accumulate.
1816 */
1817 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1818 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1819 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1820 return SIGFPE;
1821 }
1822
1823 /*
1824 * Now we can safely write the result back to the register file.
1825 */
1826 switch (rfmt) {
1827 case -1:
1828
1829 if (cpu_has_mips_4_5_r)
1830 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1831 else
1832 cbit = FPU_CSR_COND;
1833 if (rv.w)
1834 ctx->fcr31 |= cbit;
1835 else
1836 ctx->fcr31 &= ~cbit;
1837 break;
1838
1839 case d_fmt:
1840 DPTOREG(rv.d, MIPSInst_FD(ir));
1841 break;
1842 case s_fmt:
1843 SPTOREG(rv.s, MIPSInst_FD(ir));
1844 break;
1845 case w_fmt:
1846 SITOREG(rv.w, MIPSInst_FD(ir));
1847 break;
1848 case l_fmt:
1849 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1850 return SIGILL;
1851
1852 DITOREG(rv.l, MIPSInst_FD(ir));
1853 break;
1854 default:
1855 return SIGILL;
1856 }
1857
1858 return 0;
1859 }
1860
1861 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1862 int has_fpu, void *__user *fault_addr)
1863 {
1864 unsigned long oldepc, prevepc;
1865 struct mm_decoded_insn dec_insn;
1866 u16 instr[4];
1867 u16 *instr_ptr;
1868 int sig = 0;
1869
1870 oldepc = xcp->cp0_epc;
1871 do {
1872 prevepc = xcp->cp0_epc;
1873
1874 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1875 /*
1876 * Get next 2 microMIPS instructions and convert them
1877 * into 32-bit instructions.
1878 */
1879 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1880 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1881 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1882 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1883 MIPS_FPU_EMU_INC_STATS(errors);
1884 return SIGBUS;
1885 }
1886 instr_ptr = instr;
1887
1888 /* Get first instruction. */
1889 if (mm_insn_16bit(*instr_ptr)) {
1890 /* Duplicate the half-word. */
1891 dec_insn.insn = (*instr_ptr << 16) |
1892 (*instr_ptr);
1893 /* 16-bit instruction. */
1894 dec_insn.pc_inc = 2;
1895 instr_ptr += 1;
1896 } else {
1897 dec_insn.insn = (*instr_ptr << 16) |
1898 *(instr_ptr+1);
1899 /* 32-bit instruction. */
1900 dec_insn.pc_inc = 4;
1901 instr_ptr += 2;
1902 }
1903 /* Get second instruction. */
1904 if (mm_insn_16bit(*instr_ptr)) {
1905 /* Duplicate the half-word. */
1906 dec_insn.next_insn = (*instr_ptr << 16) |
1907 (*instr_ptr);
1908 /* 16-bit instruction. */
1909 dec_insn.next_pc_inc = 2;
1910 } else {
1911 dec_insn.next_insn = (*instr_ptr << 16) |
1912 *(instr_ptr+1);
1913 /* 32-bit instruction. */
1914 dec_insn.next_pc_inc = 4;
1915 }
1916 dec_insn.micro_mips_mode = 1;
1917 } else {
1918 if ((get_user(dec_insn.insn,
1919 (mips_instruction __user *) xcp->cp0_epc)) ||
1920 (get_user(dec_insn.next_insn,
1921 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1922 MIPS_FPU_EMU_INC_STATS(errors);
1923 return SIGBUS;
1924 }
1925 dec_insn.pc_inc = 4;
1926 dec_insn.next_pc_inc = 4;
1927 dec_insn.micro_mips_mode = 0;
1928 }
1929
1930 if ((dec_insn.insn == 0) ||
1931 ((dec_insn.pc_inc == 2) &&
1932 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1933 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1934 else {
1935 /*
1936 * The 'ieee754_csr' is an alias of
1937 * ctx->fcr31. No need to copy ctx->fcr31 to
1938 * ieee754_csr. But ieee754_csr.rm is ieee
1939 * library modes. (not mips rounding mode)
1940 */
1941 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1942 }
1943
1944 if (has_fpu)
1945 break;
1946 if (sig)
1947 break;
1948
1949 cond_resched();
1950 } while (xcp->cp0_epc > prevepc);
1951
1952 /* SIGILL indicates a non-fpu instruction */
1953 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1954 /* but if EPC has advanced, then ignore it */
1955 sig = 0;
1956
1957 return sig;
1958 }
Linux with added FPC-III support