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watchdog: pic32-dmt: Remove .owner field for driver
[linux/fpc-iii.git] / drivers / edac / altera_edac.c
blob5b4d223d6d686bd89388dc04c5fe071722cc8ee9
1 /*
2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Adapted from the highbank_mc_edac driver.
18 */
19
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/edac.h>
23 #include <linux/genalloc.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regmap.h>
31 #include <linux/types.h>
32 #include <linux/uaccess.h>
33
34 #include "altera_edac.h"
35 #include "edac_core.h"
36 #include "edac_module.h"
37
38 #define EDAC_MOD_STR "altera_edac"
39 #define EDAC_VERSION "1"
40 #define EDAC_DEVICE "Altera"
41
42 static const struct altr_sdram_prv_data c5_data = {
43 .ecc_ctrl_offset = CV_CTLCFG_OFST,
44 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
45 .ecc_stat_offset = CV_DRAMSTS_OFST,
46 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
47 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
48 .ecc_saddr_offset = CV_ERRADDR_OFST,
49 .ecc_daddr_offset = CV_ERRADDR_OFST,
50 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
51 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
52 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
53 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
54 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
55 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
56 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
57 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
58 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
59 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
60 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
61 };
62
63 static const struct altr_sdram_prv_data a10_data = {
64 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
65 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
66 .ecc_stat_offset = A10_INTSTAT_OFST,
67 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
68 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
69 .ecc_saddr_offset = A10_SERRADDR_OFST,
70 .ecc_daddr_offset = A10_DERRADDR_OFST,
71 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
72 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
73 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
74 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
75 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
76 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
77 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
78 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
79 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
80 };
81
82 /*********************** EDAC Memory Controller Functions ****************/
83
84 /* The SDRAM controller uses the EDAC Memory Controller framework. */
85
86 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
87 {
88 struct mem_ctl_info *mci = dev_id;
89 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
90 const struct altr_sdram_prv_data *priv = drvdata->data;
91 u32 status, err_count = 1, err_addr;
92
93 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
94
95 if (status & priv->ecc_stat_ue_mask) {
96 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
97 &err_addr);
98 if (priv->ecc_uecnt_offset)
99 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
100 &err_count);
101 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
102 err_count, err_addr);
103 }
104 if (status & priv->ecc_stat_ce_mask) {
105 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
106 &err_addr);
107 if (priv->ecc_uecnt_offset)
108 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
109 &err_count);
110 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
111 err_addr >> PAGE_SHIFT,
112 err_addr & ~PAGE_MASK, 0,
113 0, 0, -1, mci->ctl_name, "");
114 /* Clear IRQ to resume */
115 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
116 priv->ecc_irq_clr_mask);
117
118 return IRQ_HANDLED;
119 }
120 return IRQ_NONE;
121 }
122
123 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
124 const char __user *data,
125 size_t count, loff_t *ppos)
126 {
127 struct mem_ctl_info *mci = file->private_data;
128 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
129 const struct altr_sdram_prv_data *priv = drvdata->data;
130 u32 *ptemp;
131 dma_addr_t dma_handle;
132 u32 reg, read_reg;
133
134 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
135 if (!ptemp) {
136 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
137 edac_printk(KERN_ERR, EDAC_MC,
138 "Inject: Buffer Allocation error\n");
139 return -ENOMEM;
140 }
141
142 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
143 &read_reg);
144 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
145
146 /* Error are injected by writing a word while the SBE or DBE
147 * bit in the CTLCFG register is set. Reading the word will
148 * trigger the SBE or DBE error and the corresponding IRQ.
149 */
150 if (count == 3) {
151 edac_printk(KERN_ALERT, EDAC_MC,
152 "Inject Double bit error\n");
153 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
154 (read_reg | priv->ue_set_mask));
155 } else {
156 edac_printk(KERN_ALERT, EDAC_MC,
157 "Inject Single bit error\n");
158 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
159 (read_reg | priv->ce_set_mask));
160 }
161
162 ptemp[0] = 0x5A5A5A5A;
163 ptemp[1] = 0xA5A5A5A5;
164
165 /* Clear the error injection bits */
166 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
167 /* Ensure it has been written out */
168 wmb();
169
170 /*
171 * To trigger the error, we need to read the data back
172 * (the data was written with errors above).
173 * The ACCESS_ONCE macros and printk are used to prevent the
174 * the compiler optimizing these reads out.
175 */
176 reg = ACCESS_ONCE(ptemp[0]);
177 read_reg = ACCESS_ONCE(ptemp[1]);
178 /* Force Read */
179 rmb();
180
181 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
182 reg, read_reg);
183
184 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
185
186 return count;
187 }
188
189 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
190 .open = simple_open,
191 .write = altr_sdr_mc_err_inject_write,
192 .llseek = generic_file_llseek,
193 };
194
195 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
196 {
197 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
198 return;
199
200 if (!mci->debugfs)
201 return;
202
203 edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
204 &altr_sdr_mc_debug_inject_fops);
205 }
206
207 /* Get total memory size from Open Firmware DTB */
208 static unsigned long get_total_mem(void)
209 {
210 struct device_node *np = NULL;
211 const unsigned int *reg, *reg_end;
212 int len, sw, aw;
213 unsigned long start, size, total_mem = 0;
214
215 for_each_node_by_type(np, "memory") {
216 aw = of_n_addr_cells(np);
217 sw = of_n_size_cells(np);
218 reg = (const unsigned int *)of_get_property(np, "reg", &len);
219 reg_end = reg + (len / sizeof(u32));
220
221 total_mem = 0;
222 do {
223 start = of_read_number(reg, aw);
224 reg += aw;
225 size = of_read_number(reg, sw);
226 reg += sw;
227 total_mem += size;
228 } while (reg < reg_end);
229 }
230 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
231 return total_mem;
232 }
233
234 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
235 { .compatible = "altr,sdram-edac", .data = &c5_data},
236 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
237 {},
238 };
239 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
240
241 static int a10_init(struct regmap *mc_vbase)
242 {
243 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
244 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
245 edac_printk(KERN_ERR, EDAC_MC,
246 "Error setting SB IRQ mode\n");
247 return -ENODEV;
248 }
249
250 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
251 edac_printk(KERN_ERR, EDAC_MC,
252 "Error setting trigger count\n");
253 return -ENODEV;
254 }
255
256 return 0;
257 }
258
259 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
260 {
261 void __iomem *sm_base;
262 int ret = 0;
263
264 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
265 dev_name(&pdev->dev))) {
266 edac_printk(KERN_ERR, EDAC_MC,
267 "Unable to request mem region\n");
268 return -EBUSY;
269 }
270
271 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
272 if (!sm_base) {
273 edac_printk(KERN_ERR, EDAC_MC,
274 "Unable to ioremap device\n");
275
276 ret = -ENOMEM;
277 goto release;
278 }
279
280 iowrite32(mask, sm_base);
281
282 iounmap(sm_base);
283
284 release:
285 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
286
287 return ret;
288 }
289
290 static int altr_sdram_probe(struct platform_device *pdev)
291 {
292 const struct of_device_id *id;
293 struct edac_mc_layer layers[2];
294 struct mem_ctl_info *mci;
295 struct altr_sdram_mc_data *drvdata;
296 const struct altr_sdram_prv_data *priv;
297 struct regmap *mc_vbase;
298 struct dimm_info *dimm;
299 u32 read_reg;
300 int irq, irq2, res = 0;
301 unsigned long mem_size, irqflags = 0;
302
303 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
304 if (!id)
305 return -ENODEV;
306
307 /* Grab the register range from the sdr controller in device tree */
308 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
309 "altr,sdr-syscon");
310 if (IS_ERR(mc_vbase)) {
311 edac_printk(KERN_ERR, EDAC_MC,
312 "regmap for altr,sdr-syscon lookup failed.\n");
313 return -ENODEV;
314 }
315
316 /* Check specific dependencies for the module */
317 priv = of_match_node(altr_sdram_ctrl_of_match,
318 pdev->dev.of_node)->data;
319
320 /* Validate the SDRAM controller has ECC enabled */
321 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
322 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
323 edac_printk(KERN_ERR, EDAC_MC,
324 "No ECC/ECC disabled [0x%08X]\n", read_reg);
325 return -ENODEV;
326 }
327
328 /* Grab memory size from device tree. */
329 mem_size = get_total_mem();
330 if (!mem_size) {
331 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
332 return -ENODEV;
333 }
334
335 /* Ensure the SDRAM Interrupt is disabled */
336 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
337 priv->ecc_irq_en_mask, 0)) {
338 edac_printk(KERN_ERR, EDAC_MC,
339 "Error disabling SDRAM ECC IRQ\n");
340 return -ENODEV;
341 }
342
343 /* Toggle to clear the SDRAM Error count */
344 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
345 priv->ecc_cnt_rst_mask,
346 priv->ecc_cnt_rst_mask)) {
347 edac_printk(KERN_ERR, EDAC_MC,
348 "Error clearing SDRAM ECC count\n");
349 return -ENODEV;
350 }
351
352 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
353 priv->ecc_cnt_rst_mask, 0)) {
354 edac_printk(KERN_ERR, EDAC_MC,
355 "Error clearing SDRAM ECC count\n");
356 return -ENODEV;
357 }
358
359 irq = platform_get_irq(pdev, 0);
360 if (irq < 0) {
361 edac_printk(KERN_ERR, EDAC_MC,
362 "No irq %d in DT\n", irq);
363 return -ENODEV;
364 }
365
366 /* Arria10 has a 2nd IRQ */
367 irq2 = platform_get_irq(pdev, 1);
368
369 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
370 layers[0].size = 1;
371 layers[0].is_virt_csrow = true;
372 layers[1].type = EDAC_MC_LAYER_CHANNEL;
373 layers[1].size = 1;
374 layers[1].is_virt_csrow = false;
375 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
376 sizeof(struct altr_sdram_mc_data));
377 if (!mci)
378 return -ENOMEM;
379
380 mci->pdev = &pdev->dev;
381 drvdata = mci->pvt_info;
382 drvdata->mc_vbase = mc_vbase;
383 drvdata->data = priv;
384 platform_set_drvdata(pdev, mci);
385
386 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
387 edac_printk(KERN_ERR, EDAC_MC,
388 "Unable to get managed device resource\n");
389 res = -ENOMEM;
390 goto free;
391 }
392
393 mci->mtype_cap = MEM_FLAG_DDR3;
394 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
395 mci->edac_cap = EDAC_FLAG_SECDED;
396 mci->mod_name = EDAC_MOD_STR;
397 mci->mod_ver = EDAC_VERSION;
398 mci->ctl_name = dev_name(&pdev->dev);
399 mci->scrub_mode = SCRUB_SW_SRC;
400 mci->dev_name = dev_name(&pdev->dev);
401
402 dimm = *mci->dimms;
403 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
404 dimm->grain = 8;
405 dimm->dtype = DEV_X8;
406 dimm->mtype = MEM_DDR3;
407 dimm->edac_mode = EDAC_SECDED;
408
409 res = edac_mc_add_mc(mci);
410 if (res < 0)
411 goto err;
412
413 /* Only the Arria10 has separate IRQs */
414 if (irq2 > 0) {
415 /* Arria10 specific initialization */
416 res = a10_init(mc_vbase);
417 if (res < 0)
418 goto err2;
419
420 res = devm_request_irq(&pdev->dev, irq2,
421 altr_sdram_mc_err_handler,
422 IRQF_SHARED, dev_name(&pdev->dev), mci);
423 if (res < 0) {
424 edac_mc_printk(mci, KERN_ERR,
425 "Unable to request irq %d\n", irq2);
426 res = -ENODEV;
427 goto err2;
428 }
429
430 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
431 if (res < 0)
432 goto err2;
433
434 irqflags = IRQF_SHARED;
435 }
436
437 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
438 irqflags, dev_name(&pdev->dev), mci);
439 if (res < 0) {
440 edac_mc_printk(mci, KERN_ERR,
441 "Unable to request irq %d\n", irq);
442 res = -ENODEV;
443 goto err2;
444 }
445
446 /* Infrastructure ready - enable the IRQ */
447 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
448 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
449 edac_mc_printk(mci, KERN_ERR,
450 "Error enabling SDRAM ECC IRQ\n");
451 res = -ENODEV;
452 goto err2;
453 }
454
455 altr_sdr_mc_create_debugfs_nodes(mci);
456
457 devres_close_group(&pdev->dev, NULL);
458
459 return 0;
460
461 err2:
462 edac_mc_del_mc(&pdev->dev);
463 err:
464 devres_release_group(&pdev->dev, NULL);
465 free:
466 edac_mc_free(mci);
467 edac_printk(KERN_ERR, EDAC_MC,
468 "EDAC Probe Failed; Error %d\n", res);
469
470 return res;
471 }
472
473 static int altr_sdram_remove(struct platform_device *pdev)
474 {
475 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
476
477 edac_mc_del_mc(&pdev->dev);
478 edac_mc_free(mci);
479 platform_set_drvdata(pdev, NULL);
480
481 return 0;
482 }
483
484 /*
485 * If you want to suspend, need to disable EDAC by removing it
486 * from the device tree or defconfig.
487 */
488 #ifdef CONFIG_PM
489 static int altr_sdram_prepare(struct device *dev)
490 {
491 pr_err("Suspend not allowed when EDAC is enabled.\n");
492
493 return -EPERM;
494 }
495
496 static const struct dev_pm_ops altr_sdram_pm_ops = {
497 .prepare = altr_sdram_prepare,
498 };
499 #endif
500
501 static struct platform_driver altr_sdram_edac_driver = {
502 .probe = altr_sdram_probe,
503 .remove = altr_sdram_remove,
504 .driver = {
505 .name = "altr_sdram_edac",
506 #ifdef CONFIG_PM
507 .pm = &altr_sdram_pm_ops,
508 #endif
509 .of_match_table = altr_sdram_ctrl_of_match,
510 },
511 };
512
513 module_platform_driver(altr_sdram_edac_driver);
514
515 /************************* EDAC Parent Probe *************************/
516
517 static const struct of_device_id altr_edac_device_of_match[];
518
519 static const struct of_device_id altr_edac_of_match[] = {
520 { .compatible = "altr,socfpga-ecc-manager" },
521 {},
522 };
523 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
524
525 static int altr_edac_probe(struct platform_device *pdev)
526 {
527 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
528 NULL, &pdev->dev);
529 return 0;
530 }
531
532 static struct platform_driver altr_edac_driver = {
533 .probe = altr_edac_probe,
534 .driver = {
535 .name = "socfpga_ecc_manager",
536 .of_match_table = altr_edac_of_match,
537 },
538 };
539 module_platform_driver(altr_edac_driver);
540
541 /************************* EDAC Device Functions *************************/
542
543 /*
544 * EDAC Device Functions (shared between various IPs).
545 * The discrete memories use the EDAC Device framework. The probe
546 * and error handling functions are very similar between memories
547 * so they are shared. The memory allocation and freeing for EDAC
548 * trigger testing are different for each memory.
549 */
550
551 const struct edac_device_prv_data ocramecc_data;
552 const struct edac_device_prv_data l2ecc_data;
553 const struct edac_device_prv_data a10_ocramecc_data;
554 const struct edac_device_prv_data a10_l2ecc_data;
555
556 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
557 {
558 irqreturn_t ret_value = IRQ_NONE;
559 struct edac_device_ctl_info *dci = dev_id;
560 struct altr_edac_device_dev *drvdata = dci->pvt_info;
561 const struct edac_device_prv_data *priv = drvdata->data;
562
563 if (irq == drvdata->sb_irq) {
564 if (priv->ce_clear_mask)
565 writel(priv->ce_clear_mask, drvdata->base);
566 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
567 ret_value = IRQ_HANDLED;
568 } else if (irq == drvdata->db_irq) {
569 if (priv->ue_clear_mask)
570 writel(priv->ue_clear_mask, drvdata->base);
571 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
572 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
573 ret_value = IRQ_HANDLED;
574 } else {
575 WARN_ON(1);
576 }
577
578 return ret_value;
579 }
580
581 static ssize_t altr_edac_device_trig(struct file *file,
582 const char __user *user_buf,
583 size_t count, loff_t *ppos)
584
585 {
586 u32 *ptemp, i, error_mask;
587 int result = 0;
588 u8 trig_type;
589 unsigned long flags;
590 struct edac_device_ctl_info *edac_dci = file->private_data;
591 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
592 const struct edac_device_prv_data *priv = drvdata->data;
593 void *generic_ptr = edac_dci->dev;
594
595 if (!user_buf || get_user(trig_type, user_buf))
596 return -EFAULT;
597
598 if (!priv->alloc_mem)
599 return -ENOMEM;
600
601 /*
602 * Note that generic_ptr is initialized to the device * but in
603 * some alloc_functions, this is overridden and returns data.
604 */
605 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
606 if (!ptemp) {
607 edac_printk(KERN_ERR, EDAC_DEVICE,
608 "Inject: Buffer Allocation error\n");
609 return -ENOMEM;
610 }
611
612 if (trig_type == ALTR_UE_TRIGGER_CHAR)
613 error_mask = priv->ue_set_mask;
614 else
615 error_mask = priv->ce_set_mask;
616
617 edac_printk(KERN_ALERT, EDAC_DEVICE,
618 "Trigger Error Mask (0x%X)\n", error_mask);
619
620 local_irq_save(flags);
621 /* write ECC corrupted data out. */
622 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
623 /* Read data so we're in the correct state */
624 rmb();
625 if (ACCESS_ONCE(ptemp[i]))
626 result = -1;
627 /* Toggle Error bit (it is latched), leave ECC enabled */
628 writel(error_mask, (drvdata->base + priv->set_err_ofst));
629 writel(priv->ecc_enable_mask, (drvdata->base +
630 priv->set_err_ofst));
631 ptemp[i] = i;
632 }
633 /* Ensure it has been written out */
634 wmb();
635 local_irq_restore(flags);
636
637 if (result)
638 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
639
640 /* Read out written data. ECC error caused here */
641 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
642 if (ACCESS_ONCE(ptemp[i]) != i)
643 edac_printk(KERN_ERR, EDAC_DEVICE,
644 "Read doesn't match written data\n");
645
646 if (priv->free_mem)
647 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
648
649 return count;
650 }
651
652 static const struct file_operations altr_edac_device_inject_fops = {
653 .open = simple_open,
654 .write = altr_edac_device_trig,
655 .llseek = generic_file_llseek,
656 };
657
658 static ssize_t altr_edac_a10_device_trig(struct file *file,
659 const char __user *user_buf,
660 size_t count, loff_t *ppos);
661
662 static const struct file_operations altr_edac_a10_device_inject_fops = {
663 .open = simple_open,
664 .write = altr_edac_a10_device_trig,
665 .llseek = generic_file_llseek,
666 };
667
668 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
669 const struct edac_device_prv_data *priv)
670 {
671 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
672
673 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
674 return;
675
676 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
677 if (!drvdata->debugfs_dir)
678 return;
679
680 if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR,
681 drvdata->debugfs_dir, edac_dci,
682 priv->inject_fops))
683 debugfs_remove_recursive(drvdata->debugfs_dir);
684 }
685
686 static const struct of_device_id altr_edac_device_of_match[] = {
687 #ifdef CONFIG_EDAC_ALTERA_L2C
688 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
689 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
690 #endif
691 #ifdef CONFIG_EDAC_ALTERA_OCRAM
692 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
693 { .compatible = "altr,socfpga-a10-ocram-ecc", .data = &a10_ocramecc_data },
694 #endif
695 {},
696 };
697 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
698
699 /*
700 * altr_edac_device_probe()
701 * This is a generic EDAC device driver that will support
702 * various Altera memory devices such as the L2 cache ECC and
703 * OCRAM ECC as well as the memories for other peripherals.
704 * Module specific initialization is done by passing the
705 * function index in the device tree.
706 */
707 static int altr_edac_device_probe(struct platform_device *pdev)
708 {
709 struct edac_device_ctl_info *dci;
710 struct altr_edac_device_dev *drvdata;
711 struct resource *r;
712 int res = 0;
713 struct device_node *np = pdev->dev.of_node;
714 char *ecc_name = (char *)np->name;
715 static int dev_instance;
716
717 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
718 edac_printk(KERN_ERR, EDAC_DEVICE,
719 "Unable to open devm\n");
720 return -ENOMEM;
721 }
722
723 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
724 if (!r) {
725 edac_printk(KERN_ERR, EDAC_DEVICE,
726 "Unable to get mem resource\n");
727 res = -ENODEV;
728 goto fail;
729 }
730
731 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
732 dev_name(&pdev->dev))) {
733 edac_printk(KERN_ERR, EDAC_DEVICE,
734 "%s:Error requesting mem region\n", ecc_name);
735 res = -EBUSY;
736 goto fail;
737 }
738
739 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
740 1, ecc_name, 1, 0, NULL, 0,
741 dev_instance++);
742
743 if (!dci) {
744 edac_printk(KERN_ERR, EDAC_DEVICE,
745 "%s: Unable to allocate EDAC device\n", ecc_name);
746 res = -ENOMEM;
747 goto fail;
748 }
749
750 drvdata = dci->pvt_info;
751 dci->dev = &pdev->dev;
752 platform_set_drvdata(pdev, dci);
753 drvdata->edac_dev_name = ecc_name;
754
755 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
756 if (!drvdata->base)
757 goto fail1;
758
759 /* Get driver specific data for this EDAC device */
760 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
761
762 /* Check specific dependencies for the module */
763 if (drvdata->data->setup) {
764 res = drvdata->data->setup(drvdata);
765 if (res)
766 goto fail1;
767 }
768
769 drvdata->sb_irq = platform_get_irq(pdev, 0);
770 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
771 altr_edac_device_handler,
772 0, dev_name(&pdev->dev), dci);
773 if (res)
774 goto fail1;
775
776 drvdata->db_irq = platform_get_irq(pdev, 1);
777 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
778 altr_edac_device_handler,
779 0, dev_name(&pdev->dev), dci);
780 if (res)
781 goto fail1;
782
783 dci->mod_name = "Altera ECC Manager";
784 dci->dev_name = drvdata->edac_dev_name;
785
786 res = edac_device_add_device(dci);
787 if (res)
788 goto fail1;
789
790 altr_create_edacdev_dbgfs(dci, drvdata->data);
791
792 devres_close_group(&pdev->dev, NULL);
793
794 return 0;
795
796 fail1:
797 edac_device_free_ctl_info(dci);
798 fail:
799 devres_release_group(&pdev->dev, NULL);
800 edac_printk(KERN_ERR, EDAC_DEVICE,
801 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
802
803 return res;
804 }
805
806 static int altr_edac_device_remove(struct platform_device *pdev)
807 {
808 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
809 struct altr_edac_device_dev *drvdata = dci->pvt_info;
810
811 debugfs_remove_recursive(drvdata->debugfs_dir);
812 edac_device_del_device(&pdev->dev);
813 edac_device_free_ctl_info(dci);
814
815 return 0;
816 }
817
818 static struct platform_driver altr_edac_device_driver = {
819 .probe = altr_edac_device_probe,
820 .remove = altr_edac_device_remove,
821 .driver = {
822 .name = "altr_edac_device",
823 .of_match_table = altr_edac_device_of_match,
824 },
825 };
826 module_platform_driver(altr_edac_device_driver);
827
828 /*********************** OCRAM EDAC Device Functions *********************/
829
830 #ifdef CONFIG_EDAC_ALTERA_OCRAM
831 /*
832 * Test for memory's ECC dependencies upon entry because platform specific
833 * startup should have initialized the memory and enabled the ECC.
834 * Can't turn on ECC here because accessing un-initialized memory will
835 * cause CE/UE errors possibly causing an ABORT.
836 */
837 static int altr_check_ecc_deps(struct altr_edac_device_dev *device)
838 {
839 void __iomem *base = device->base;
840 const struct edac_device_prv_data *prv = device->data;
841
842 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
843 return 0;
844
845 edac_printk(KERN_ERR, EDAC_DEVICE,
846 "%s: No ECC present or ECC disabled.\n",
847 device->edac_dev_name);
848 return -ENODEV;
849 }
850
851 static void *ocram_alloc_mem(size_t size, void **other)
852 {
853 struct device_node *np;
854 struct gen_pool *gp;
855 void *sram_addr;
856
857 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
858 if (!np)
859 return NULL;
860
861 gp = of_gen_pool_get(np, "iram", 0);
862 of_node_put(np);
863 if (!gp)
864 return NULL;
865
866 sram_addr = (void *)gen_pool_alloc(gp, size);
867 if (!sram_addr)
868 return NULL;
869
870 memset(sram_addr, 0, size);
871 /* Ensure data is written out */
872 wmb();
873
874 /* Remember this handle for freeing later */
875 *other = gp;
876
877 return sram_addr;
878 }
879
880 static void ocram_free_mem(void *p, size_t size, void *other)
881 {
882 gen_pool_free((struct gen_pool *)other, (u32)p, size);
883 }
884
885 static irqreturn_t altr_edac_a10_ecc_irq(struct altr_edac_device_dev *dci,
886 bool sberr)
887 {
888 void __iomem *base = dci->base;
889
890 if (sberr) {
891 writel(ALTR_A10_ECC_SERRPENA,
892 base + ALTR_A10_ECC_INTSTAT_OFST);
893 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
894 } else {
895 writel(ALTR_A10_ECC_DERRPENA,
896 base + ALTR_A10_ECC_INTSTAT_OFST);
897 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
898 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
899 }
900 return IRQ_HANDLED;
901 }
902
903 const struct edac_device_prv_data ocramecc_data = {
904 .setup = altr_check_ecc_deps,
905 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
906 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
907 .dbgfs_name = "altr_ocram_trigger",
908 .alloc_mem = ocram_alloc_mem,
909 .free_mem = ocram_free_mem,
910 .ecc_enable_mask = ALTR_OCR_ECC_EN,
911 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
912 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
913 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
914 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
915 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
916 .inject_fops = &altr_edac_device_inject_fops,
917 };
918
919 const struct edac_device_prv_data a10_ocramecc_data = {
920 .setup = altr_check_ecc_deps,
921 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
922 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
923 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
924 .dbgfs_name = "altr_ocram_trigger",
925 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
926 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
927 .ce_set_mask = ALTR_A10_ECC_TSERRA,
928 .ue_set_mask = ALTR_A10_ECC_TDERRA,
929 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
930 .ecc_irq_handler = altr_edac_a10_ecc_irq,
931 .inject_fops = &altr_edac_a10_device_inject_fops,
932 };
933
934 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
935
936 /********************* L2 Cache EDAC Device Functions ********************/
937
938 #ifdef CONFIG_EDAC_ALTERA_L2C
939
940 static void *l2_alloc_mem(size_t size, void **other)
941 {
942 struct device *dev = *other;
943 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
944
945 if (!ptemp)
946 return NULL;
947
948 /* Make sure everything is written out */
949 wmb();
950
951 /*
952 * Clean all cache levels up to LoC (includes L2)
953 * This ensures the corrupted data is written into
954 * L2 cache for readback test (which causes ECC error).
955 */
956 flush_cache_all();
957
958 return ptemp;
959 }
960
961 static void l2_free_mem(void *p, size_t size, void *other)
962 {
963 struct device *dev = other;
964
965 if (dev && p)
966 devm_kfree(dev, p);
967 }
968
969 /*
970 * altr_l2_check_deps()
971 * Test for L2 cache ECC dependencies upon entry because
972 * platform specific startup should have initialized the L2
973 * memory and enabled the ECC.
974 * Bail if ECC is not enabled.
975 * Note that L2 Cache Enable is forced at build time.
976 */
977 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
978 {
979 void __iomem *base = device->base;
980 const struct edac_device_prv_data *prv = device->data;
981
982 if ((readl(base) & prv->ecc_enable_mask) ==
983 prv->ecc_enable_mask)
984 return 0;
985
986 edac_printk(KERN_ERR, EDAC_DEVICE,
987 "L2: No ECC present, or ECC disabled\n");
988 return -ENODEV;
989 }
990
991 static irqreturn_t altr_edac_a10_l2_irq(struct altr_edac_device_dev *dci,
992 bool sberr)
993 {
994 if (sberr) {
995 regmap_write(dci->edac->ecc_mgr_map,
996 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
997 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
998 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
999 } else {
1000 regmap_write(dci->edac->ecc_mgr_map,
1001 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1002 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1003 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1004 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1005 }
1006 return IRQ_HANDLED;
1007 }
1008
1009 const struct edac_device_prv_data l2ecc_data = {
1010 .setup = altr_l2_check_deps,
1011 .ce_clear_mask = 0,
1012 .ue_clear_mask = 0,
1013 .dbgfs_name = "altr_l2_trigger",
1014 .alloc_mem = l2_alloc_mem,
1015 .free_mem = l2_free_mem,
1016 .ecc_enable_mask = ALTR_L2_ECC_EN,
1017 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1018 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1019 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1020 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1021 .inject_fops = &altr_edac_device_inject_fops,
1022 };
1023
1024 const struct edac_device_prv_data a10_l2ecc_data = {
1025 .setup = altr_l2_check_deps,
1026 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1027 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1028 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1029 .dbgfs_name = "altr_l2_trigger",
1030 .alloc_mem = l2_alloc_mem,
1031 .free_mem = l2_free_mem,
1032 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1033 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1034 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1035 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1036 .ecc_irq_handler = altr_edac_a10_l2_irq,
1037 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1038 .inject_fops = &altr_edac_device_inject_fops,
1039 };
1040
1041 #endif /* CONFIG_EDAC_ALTERA_L2C */
1042
1043 /********************* Arria10 EDAC Device Functions *************************/
1044
1045 /*
1046 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1047 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1048 * manager manages the IRQs and the children.
1049 * Based on xgene_edac.c peripheral code.
1050 */
1051
1052 static ssize_t altr_edac_a10_device_trig(struct file *file,
1053 const char __user *user_buf,
1054 size_t count, loff_t *ppos)
1055 {
1056 struct edac_device_ctl_info *edac_dci = file->private_data;
1057 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1058 const struct edac_device_prv_data *priv = drvdata->data;
1059 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1060 unsigned long flags;
1061 u8 trig_type;
1062
1063 if (!user_buf || get_user(trig_type, user_buf))
1064 return -EFAULT;
1065
1066 local_irq_save(flags);
1067 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1068 writel(priv->ue_set_mask, set_addr);
1069 else
1070 writel(priv->ce_set_mask, set_addr);
1071 /* Ensure the interrupt test bits are set */
1072 wmb();
1073 local_irq_restore(flags);
1074
1075 return count;
1076 }
1077
1078 static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id)
1079 {
1080 irqreturn_t rc = IRQ_NONE;
1081 struct altr_arria10_edac *edac = dev_id;
1082 struct altr_edac_device_dev *dci;
1083 int irq_status;
1084 bool sberr = (irq == edac->sb_irq) ? 1 : 0;
1085 int sm_offset = sberr ? A10_SYSMGR_ECC_INTSTAT_SERR_OFST :
1086 A10_SYSMGR_ECC_INTSTAT_DERR_OFST;
1087
1088 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1089
1090 if ((irq != edac->sb_irq) && (irq != edac->db_irq)) {
1091 WARN_ON(1);
1092 } else {
1093 list_for_each_entry(dci, &edac->a10_ecc_devices, next) {
1094 if (irq_status & dci->data->irq_status_mask)
1095 rc = dci->data->ecc_irq_handler(dci, sberr);
1096 }
1097 }
1098
1099 return rc;
1100 }
1101
1102 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1103 struct device_node *np)
1104 {
1105 struct edac_device_ctl_info *dci;
1106 struct altr_edac_device_dev *altdev;
1107 char *ecc_name = (char *)np->name;
1108 struct resource res;
1109 int edac_idx;
1110 int rc = 0;
1111 const struct edac_device_prv_data *prv;
1112 /* Get matching node and check for valid result */
1113 const struct of_device_id *pdev_id =
1114 of_match_node(altr_edac_device_of_match, np);
1115 if (IS_ERR_OR_NULL(pdev_id))
1116 return -ENODEV;
1117
1118 /* Get driver specific data for this EDAC device */
1119 prv = pdev_id->data;
1120 if (IS_ERR_OR_NULL(prv))
1121 return -ENODEV;
1122
1123 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1124 return -ENOMEM;
1125
1126 rc = of_address_to_resource(np, 0, &res);
1127 if (rc < 0) {
1128 edac_printk(KERN_ERR, EDAC_DEVICE,
1129 "%s: no resource address\n", ecc_name);
1130 goto err_release_group;
1131 }
1132
1133 edac_idx = edac_device_alloc_index();
1134 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1135 1, ecc_name, 1, 0, NULL, 0,
1136 edac_idx);
1137
1138 if (!dci) {
1139 edac_printk(KERN_ERR, EDAC_DEVICE,
1140 "%s: Unable to allocate EDAC device\n", ecc_name);
1141 rc = -ENOMEM;
1142 goto err_release_group;
1143 }
1144
1145 altdev = dci->pvt_info;
1146 dci->dev = edac->dev;
1147 altdev->edac_dev_name = ecc_name;
1148 altdev->edac_idx = edac_idx;
1149 altdev->edac = edac;
1150 altdev->edac_dev = dci;
1151 altdev->data = prv;
1152 altdev->ddev = *edac->dev;
1153 dci->dev = &altdev->ddev;
1154 dci->ctl_name = "Altera ECC Manager";
1155 dci->mod_name = ecc_name;
1156 dci->dev_name = ecc_name;
1157
1158 altdev->base = devm_ioremap_resource(edac->dev, &res);
1159 if (IS_ERR(altdev->base)) {
1160 rc = PTR_ERR(altdev->base);
1161 goto err_release_group1;
1162 }
1163
1164 /* Check specific dependencies for the module */
1165 if (altdev->data->setup) {
1166 rc = altdev->data->setup(altdev);
1167 if (rc)
1168 goto err_release_group1;
1169 }
1170
1171 rc = edac_device_add_device(dci);
1172 if (rc) {
1173 dev_err(edac->dev, "edac_device_add_device failed\n");
1174 rc = -ENOMEM;
1175 goto err_release_group1;
1176 }
1177
1178 altr_create_edacdev_dbgfs(dci, prv);
1179
1180 list_add(&altdev->next, &edac->a10_ecc_devices);
1181
1182 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1183
1184 return 0;
1185
1186 err_release_group1:
1187 edac_device_free_ctl_info(dci);
1188 err_release_group:
1189 edac_printk(KERN_ALERT, EDAC_DEVICE, "%s: %d\n", __func__, __LINE__);
1190 devres_release_group(edac->dev, NULL);
1191 edac_printk(KERN_ERR, EDAC_DEVICE,
1192 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1193
1194 return rc;
1195 }
1196
1197 static int altr_edac_a10_probe(struct platform_device *pdev)
1198 {
1199 struct altr_arria10_edac *edac;
1200 struct device_node *child;
1201 int rc;
1202
1203 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
1204 if (!edac)
1205 return -ENOMEM;
1206
1207 edac->dev = &pdev->dev;
1208 platform_set_drvdata(pdev, edac);
1209 INIT_LIST_HEAD(&edac->a10_ecc_devices);
1210
1211 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1212 "altr,sysmgr-syscon");
1213 if (IS_ERR(edac->ecc_mgr_map)) {
1214 edac_printk(KERN_ERR, EDAC_DEVICE,
1215 "Unable to get syscon altr,sysmgr-syscon\n");
1216 return PTR_ERR(edac->ecc_mgr_map);
1217 }
1218
1219 edac->sb_irq = platform_get_irq(pdev, 0);
1220 rc = devm_request_irq(&pdev->dev, edac->sb_irq,
1221 altr_edac_a10_irq_handler,
1222 IRQF_SHARED, dev_name(&pdev->dev), edac);
1223 if (rc) {
1224 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1225 return rc;
1226 }
1227
1228 edac->db_irq = platform_get_irq(pdev, 1);
1229 rc = devm_request_irq(&pdev->dev, edac->db_irq,
1230 altr_edac_a10_irq_handler,
1231 IRQF_SHARED, dev_name(&pdev->dev), edac);
1232 if (rc) {
1233 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1234 return rc;
1235 }
1236
1237 for_each_child_of_node(pdev->dev.of_node, child) {
1238 if (!of_device_is_available(child))
1239 continue;
1240 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
1241 altr_edac_a10_device_add(edac, child);
1242 else if (of_device_is_compatible(child,
1243 "altr,socfpga-a10-ocram-ecc"))
1244 altr_edac_a10_device_add(edac, child);
1245 }
1246
1247 return 0;
1248 }
1249
1250 static const struct of_device_id altr_edac_a10_of_match[] = {
1251 { .compatible = "altr,socfpga-a10-ecc-manager" },
1252 {},
1253 };
1254 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
1255
1256 static struct platform_driver altr_edac_a10_driver = {
1257 .probe = altr_edac_a10_probe,
1258 .driver = {
1259 .name = "socfpga_a10_ecc_manager",
1260 .of_match_table = altr_edac_a10_of_match,
1261 },
1262 };
1263 module_platform_driver(altr_edac_a10_driver);
1264
1265 MODULE_LICENSE("GPL v2");
1266 MODULE_AUTHOR("Thor Thayer");
1267 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
Linux with added FPC-III support