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staging: most: core: add a match function for the bus
[linux/fpc-iii.git] / drivers / dma / txx9dmac.c
blob4d8c7b9078fd7864f36a9ec605b43652e6267e4b
1 /*
2 * Driver for the TXx9 SoC DMA Controller
3 *
4 * Copyright (C) 2009 Atsushi Nemoto
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/scatterlist.h>
18
19 #include "dmaengine.h"
20 #include "txx9dmac.h"
21
22 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
23 {
24 return container_of(chan, struct txx9dmac_chan, chan);
25 }
26
27 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
28 {
29 return dc->ch_regs;
30 }
31
32 static struct txx9dmac_cregs32 __iomem *__dma_regs32(
33 const struct txx9dmac_chan *dc)
34 {
35 return dc->ch_regs;
36 }
37
38 #define channel64_readq(dc, name) \
39 __raw_readq(&(__dma_regs(dc)->name))
40 #define channel64_writeq(dc, name, val) \
41 __raw_writeq((val), &(__dma_regs(dc)->name))
42 #define channel64_readl(dc, name) \
43 __raw_readl(&(__dma_regs(dc)->name))
44 #define channel64_writel(dc, name, val) \
45 __raw_writel((val), &(__dma_regs(dc)->name))
46
47 #define channel32_readl(dc, name) \
48 __raw_readl(&(__dma_regs32(dc)->name))
49 #define channel32_writel(dc, name, val) \
50 __raw_writel((val), &(__dma_regs32(dc)->name))
51
52 #define channel_readq(dc, name) channel64_readq(dc, name)
53 #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
54 #define channel_readl(dc, name) \
55 (is_dmac64(dc) ? \
56 channel64_readl(dc, name) : channel32_readl(dc, name))
57 #define channel_writel(dc, name, val) \
58 (is_dmac64(dc) ? \
59 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
60
61 static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
62 {
63 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
64 return channel64_readq(dc, CHAR);
65 else
66 return channel64_readl(dc, CHAR);
67 }
68
69 static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
70 {
71 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
72 channel64_writeq(dc, CHAR, val);
73 else
74 channel64_writel(dc, CHAR, val);
75 }
76
77 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
78 {
79 #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
80 channel64_writel(dc, CHAR, 0);
81 channel64_writel(dc, __pad_CHAR, 0);
82 #else
83 channel64_writeq(dc, CHAR, 0);
84 #endif
85 }
86
87 static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
88 {
89 if (is_dmac64(dc))
90 return channel64_read_CHAR(dc);
91 else
92 return channel32_readl(dc, CHAR);
93 }
94
95 static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
96 {
97 if (is_dmac64(dc))
98 channel64_write_CHAR(dc, val);
99 else
100 channel32_writel(dc, CHAR, val);
101 }
102
103 static struct txx9dmac_regs __iomem *__txx9dmac_regs(
104 const struct txx9dmac_dev *ddev)
105 {
106 return ddev->regs;
107 }
108
109 static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
110 const struct txx9dmac_dev *ddev)
111 {
112 return ddev->regs;
113 }
114
115 #define dma64_readl(ddev, name) \
116 __raw_readl(&(__txx9dmac_regs(ddev)->name))
117 #define dma64_writel(ddev, name, val) \
118 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
119
120 #define dma32_readl(ddev, name) \
121 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
122 #define dma32_writel(ddev, name, val) \
123 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
124
125 #define dma_readl(ddev, name) \
126 (__is_dmac64(ddev) ? \
127 dma64_readl(ddev, name) : dma32_readl(ddev, name))
128 #define dma_writel(ddev, name, val) \
129 (__is_dmac64(ddev) ? \
130 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
131
132 static struct device *chan2dev(struct dma_chan *chan)
133 {
134 return &chan->dev->device;
135 }
136 static struct device *chan2parent(struct dma_chan *chan)
137 {
138 return chan->dev->device.parent;
139 }
140
141 static struct txx9dmac_desc *
142 txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
143 {
144 return container_of(txd, struct txx9dmac_desc, txd);
145 }
146
147 static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
148 const struct txx9dmac_desc *desc)
149 {
150 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
151 }
152
153 static void desc_write_CHAR(const struct txx9dmac_chan *dc,
154 struct txx9dmac_desc *desc, dma_addr_t val)
155 {
156 if (is_dmac64(dc))
157 desc->hwdesc.CHAR = val;
158 else
159 desc->hwdesc32.CHAR = val;
160 }
161
162 #define TXX9_DMA_MAX_COUNT 0x04000000
163
164 #define TXX9_DMA_INITIAL_DESC_COUNT 64
165
166 static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
167 {
168 return list_entry(dc->active_list.next,
169 struct txx9dmac_desc, desc_node);
170 }
171
172 static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
173 {
174 return list_entry(dc->active_list.prev,
175 struct txx9dmac_desc, desc_node);
176 }
177
178 static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
179 {
180 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
181 }
182
183 static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
184 {
185 if (!list_empty(&desc->tx_list))
186 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
187 return desc;
188 }
189
190 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
191
192 static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
193 gfp_t flags)
194 {
195 struct txx9dmac_dev *ddev = dc->ddev;
196 struct txx9dmac_desc *desc;
197
198 desc = kzalloc(sizeof(*desc), flags);
199 if (!desc)
200 return NULL;
201 INIT_LIST_HEAD(&desc->tx_list);
202 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
203 desc->txd.tx_submit = txx9dmac_tx_submit;
204 /* txd.flags will be overwritten in prep funcs */
205 desc->txd.flags = DMA_CTRL_ACK;
206 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
207 ddev->descsize, DMA_TO_DEVICE);
208 return desc;
209 }
210
211 static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
212 {
213 struct txx9dmac_desc *desc, *_desc;
214 struct txx9dmac_desc *ret = NULL;
215 unsigned int i = 0;
216
217 spin_lock_bh(&dc->lock);
218 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
219 if (async_tx_test_ack(&desc->txd)) {
220 list_del(&desc->desc_node);
221 ret = desc;
222 break;
223 }
224 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
225 i++;
226 }
227 spin_unlock_bh(&dc->lock);
228
229 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
230 i);
231 if (!ret) {
232 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
233 if (ret) {
234 spin_lock_bh(&dc->lock);
235 dc->descs_allocated++;
236 spin_unlock_bh(&dc->lock);
237 } else
238 dev_err(chan2dev(&dc->chan),
239 "not enough descriptors available\n");
240 }
241 return ret;
242 }
243
244 static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
245 struct txx9dmac_desc *desc)
246 {
247 struct txx9dmac_dev *ddev = dc->ddev;
248 struct txx9dmac_desc *child;
249
250 list_for_each_entry(child, &desc->tx_list, desc_node)
251 dma_sync_single_for_cpu(chan2parent(&dc->chan),
252 child->txd.phys, ddev->descsize,
253 DMA_TO_DEVICE);
254 dma_sync_single_for_cpu(chan2parent(&dc->chan),
255 desc->txd.phys, ddev->descsize,
256 DMA_TO_DEVICE);
257 }
258
259 /*
260 * Move a descriptor, including any children, to the free list.
261 * `desc' must not be on any lists.
262 */
263 static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
264 struct txx9dmac_desc *desc)
265 {
266 if (desc) {
267 struct txx9dmac_desc *child;
268
269 txx9dmac_sync_desc_for_cpu(dc, desc);
270
271 spin_lock_bh(&dc->lock);
272 list_for_each_entry(child, &desc->tx_list, desc_node)
273 dev_vdbg(chan2dev(&dc->chan),
274 "moving child desc %p to freelist\n",
275 child);
276 list_splice_init(&desc->tx_list, &dc->free_list);
277 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
278 desc);
279 list_add(&desc->desc_node, &dc->free_list);
280 spin_unlock_bh(&dc->lock);
281 }
282 }
283
284 /*----------------------------------------------------------------------*/
285
286 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
287 {
288 if (is_dmac64(dc))
289 dev_err(chan2dev(&dc->chan),
290 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
291 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
292 (u64)channel64_read_CHAR(dc),
293 channel64_readq(dc, SAR),
294 channel64_readq(dc, DAR),
295 channel64_readl(dc, CNTR),
296 channel64_readl(dc, SAIR),
297 channel64_readl(dc, DAIR),
298 channel64_readl(dc, CCR),
299 channel64_readl(dc, CSR));
300 else
301 dev_err(chan2dev(&dc->chan),
302 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
303 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
304 channel32_readl(dc, CHAR),
305 channel32_readl(dc, SAR),
306 channel32_readl(dc, DAR),
307 channel32_readl(dc, CNTR),
308 channel32_readl(dc, SAIR),
309 channel32_readl(dc, DAIR),
310 channel32_readl(dc, CCR),
311 channel32_readl(dc, CSR));
312 }
313
314 static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
315 {
316 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
317 if (is_dmac64(dc)) {
318 channel64_clear_CHAR(dc);
319 channel_writeq(dc, SAR, 0);
320 channel_writeq(dc, DAR, 0);
321 } else {
322 channel_writel(dc, CHAR, 0);
323 channel_writel(dc, SAR, 0);
324 channel_writel(dc, DAR, 0);
325 }
326 channel_writel(dc, CNTR, 0);
327 channel_writel(dc, SAIR, 0);
328 channel_writel(dc, DAIR, 0);
329 channel_writel(dc, CCR, 0);
330 mmiowb();
331 }
332
333 /* Called with dc->lock held and bh disabled */
334 static void txx9dmac_dostart(struct txx9dmac_chan *dc,
335 struct txx9dmac_desc *first)
336 {
337 struct txx9dmac_slave *ds = dc->chan.private;
338 u32 sai, dai;
339
340 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
341 first->txd.cookie, first);
342 /* ASSERT: channel is idle */
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
344 dev_err(chan2dev(&dc->chan),
345 "BUG: Attempted to start non-idle channel\n");
346 txx9dmac_dump_regs(dc);
347 /* The tasklet will hopefully advance the queue... */
348 return;
349 }
350
351 if (is_dmac64(dc)) {
352 channel64_writel(dc, CNTR, 0);
353 channel64_writel(dc, CSR, 0xffffffff);
354 if (ds) {
355 if (ds->tx_reg) {
356 sai = ds->reg_width;
357 dai = 0;
358 } else {
359 sai = 0;
360 dai = ds->reg_width;
361 }
362 } else {
363 sai = 8;
364 dai = 8;
365 }
366 channel64_writel(dc, SAIR, sai);
367 channel64_writel(dc, DAIR, dai);
368 /* All 64-bit DMAC supports SMPCHN */
369 channel64_writel(dc, CCR, dc->ccr);
370 /* Writing a non zero value to CHAR will assert XFACT */
371 channel64_write_CHAR(dc, first->txd.phys);
372 } else {
373 channel32_writel(dc, CNTR, 0);
374 channel32_writel(dc, CSR, 0xffffffff);
375 if (ds) {
376 if (ds->tx_reg) {
377 sai = ds->reg_width;
378 dai = 0;
379 } else {
380 sai = 0;
381 dai = ds->reg_width;
382 }
383 } else {
384 sai = 4;
385 dai = 4;
386 }
387 channel32_writel(dc, SAIR, sai);
388 channel32_writel(dc, DAIR, dai);
389 if (txx9_dma_have_SMPCHN()) {
390 channel32_writel(dc, CCR, dc->ccr);
391 /* Writing a non zero value to CHAR will assert XFACT */
392 channel32_writel(dc, CHAR, first->txd.phys);
393 } else {
394 channel32_writel(dc, CHAR, first->txd.phys);
395 channel32_writel(dc, CCR, dc->ccr);
396 }
397 }
398 }
399
400 /*----------------------------------------------------------------------*/
401
402 static void
403 txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
404 struct txx9dmac_desc *desc)
405 {
406 struct dmaengine_desc_callback cb;
407 struct dma_async_tx_descriptor *txd = &desc->txd;
408
409 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
410 txd->cookie, desc);
411
412 dma_cookie_complete(txd);
413 dmaengine_desc_get_callback(txd, &cb);
414
415 txx9dmac_sync_desc_for_cpu(dc, desc);
416 list_splice_init(&desc->tx_list, &dc->free_list);
417 list_move(&desc->desc_node, &dc->free_list);
418
419 dma_descriptor_unmap(txd);
420 /*
421 * The API requires that no submissions are done from a
422 * callback, so we don't need to drop the lock here
423 */
424 dmaengine_desc_callback_invoke(&cb, NULL);
425 dma_run_dependencies(txd);
426 }
427
428 static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
429 {
430 struct txx9dmac_dev *ddev = dc->ddev;
431 struct txx9dmac_desc *desc;
432 struct txx9dmac_desc *prev = NULL;
433
434 BUG_ON(!list_empty(list));
435 do {
436 desc = txx9dmac_first_queued(dc);
437 if (prev) {
438 desc_write_CHAR(dc, prev, desc->txd.phys);
439 dma_sync_single_for_device(chan2parent(&dc->chan),
440 prev->txd.phys, ddev->descsize,
441 DMA_TO_DEVICE);
442 }
443 prev = txx9dmac_last_child(desc);
444 list_move_tail(&desc->desc_node, list);
445 /* Make chain-completion interrupt happen */
446 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
447 !txx9dmac_chan_INTENT(dc))
448 break;
449 } while (!list_empty(&dc->queue));
450 }
451
452 static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
453 {
454 struct txx9dmac_desc *desc, *_desc;
455 LIST_HEAD(list);
456
457 /*
458 * Submit queued descriptors ASAP, i.e. before we go through
459 * the completed ones.
460 */
461 list_splice_init(&dc->active_list, &list);
462 if (!list_empty(&dc->queue)) {
463 txx9dmac_dequeue(dc, &dc->active_list);
464 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
465 }
466
467 list_for_each_entry_safe(desc, _desc, &list, desc_node)
468 txx9dmac_descriptor_complete(dc, desc);
469 }
470
471 static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
472 struct txx9dmac_hwdesc *desc)
473 {
474 if (is_dmac64(dc)) {
475 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
476 dev_crit(chan2dev(&dc->chan),
477 " desc: ch%#llx s%#llx d%#llx c%#x\n",
478 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
479 #else
480 dev_crit(chan2dev(&dc->chan),
481 " desc: ch%#llx s%#llx d%#llx c%#x"
482 " si%#x di%#x cc%#x cs%#x\n",
483 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
484 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
485 #endif
486 } else {
487 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
488 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
489 dev_crit(chan2dev(&dc->chan),
490 " desc: ch%#x s%#x d%#x c%#x\n",
491 d->CHAR, d->SAR, d->DAR, d->CNTR);
492 #else
493 dev_crit(chan2dev(&dc->chan),
494 " desc: ch%#x s%#x d%#x c%#x"
495 " si%#x di%#x cc%#x cs%#x\n",
496 d->CHAR, d->SAR, d->DAR, d->CNTR,
497 d->SAIR, d->DAIR, d->CCR, d->CSR);
498 #endif
499 }
500 }
501
502 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
503 {
504 struct txx9dmac_desc *bad_desc;
505 struct txx9dmac_desc *child;
506 u32 errors;
507
508 /*
509 * The descriptor currently at the head of the active list is
510 * borked. Since we don't have any way to report errors, we'll
511 * just have to scream loudly and try to carry on.
512 */
513 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
514 txx9dmac_dump_regs(dc);
515
516 bad_desc = txx9dmac_first_active(dc);
517 list_del_init(&bad_desc->desc_node);
518
519 /* Clear all error flags and try to restart the controller */
520 errors = csr & (TXX9_DMA_CSR_ABCHC |
521 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
522 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
523 channel_writel(dc, CSR, errors);
524
525 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
526 txx9dmac_dequeue(dc, &dc->active_list);
527 if (!list_empty(&dc->active_list))
528 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
529
530 dev_crit(chan2dev(&dc->chan),
531 "Bad descriptor submitted for DMA! (cookie: %d)\n",
532 bad_desc->txd.cookie);
533 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
534 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
535 txx9dmac_dump_desc(dc, &child->hwdesc);
536 /* Pretend the descriptor completed successfully */
537 txx9dmac_descriptor_complete(dc, bad_desc);
538 }
539
540 static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
541 {
542 dma_addr_t chain;
543 struct txx9dmac_desc *desc, *_desc;
544 struct txx9dmac_desc *child;
545 u32 csr;
546
547 if (is_dmac64(dc)) {
548 chain = channel64_read_CHAR(dc);
549 csr = channel64_readl(dc, CSR);
550 channel64_writel(dc, CSR, csr);
551 } else {
552 chain = channel32_readl(dc, CHAR);
553 csr = channel32_readl(dc, CSR);
554 channel32_writel(dc, CSR, csr);
555 }
556 /* For dynamic chain, we should look at XFACT instead of NCHNC */
557 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
558 /* Everything we've submitted is done */
559 txx9dmac_complete_all(dc);
560 return;
561 }
562 if (!(csr & TXX9_DMA_CSR_CHNEN))
563 chain = 0; /* last descriptor of this chain */
564
565 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
566 (u64)chain);
567
568 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
569 if (desc_read_CHAR(dc, desc) == chain) {
570 /* This one is currently in progress */
571 if (csr & TXX9_DMA_CSR_ABCHC)
572 goto scan_done;
573 return;
574 }
575
576 list_for_each_entry(child, &desc->tx_list, desc_node)
577 if (desc_read_CHAR(dc, child) == chain) {
578 /* Currently in progress */
579 if (csr & TXX9_DMA_CSR_ABCHC)
580 goto scan_done;
581 return;
582 }
583
584 /*
585 * No descriptors so far seem to be in progress, i.e.
586 * this one must be done.
587 */
588 txx9dmac_descriptor_complete(dc, desc);
589 }
590 scan_done:
591 if (csr & TXX9_DMA_CSR_ABCHC) {
592 txx9dmac_handle_error(dc, csr);
593 return;
594 }
595
596 dev_err(chan2dev(&dc->chan),
597 "BUG: All descriptors done, but channel not idle!\n");
598
599 /* Try to continue after resetting the channel... */
600 txx9dmac_reset_chan(dc);
601
602 if (!list_empty(&dc->queue)) {
603 txx9dmac_dequeue(dc, &dc->active_list);
604 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
605 }
606 }
607
608 static void txx9dmac_chan_tasklet(unsigned long data)
609 {
610 int irq;
611 u32 csr;
612 struct txx9dmac_chan *dc;
613
614 dc = (struct txx9dmac_chan *)data;
615 csr = channel_readl(dc, CSR);
616 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
617
618 spin_lock(&dc->lock);
619 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
620 TXX9_DMA_CSR_NTRNFC))
621 txx9dmac_scan_descriptors(dc);
622 spin_unlock(&dc->lock);
623 irq = dc->irq;
624
625 enable_irq(irq);
626 }
627
628 static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
629 {
630 struct txx9dmac_chan *dc = dev_id;
631
632 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
633 channel_readl(dc, CSR));
634
635 tasklet_schedule(&dc->tasklet);
636 /*
637 * Just disable the interrupts. We'll turn them back on in the
638 * softirq handler.
639 */
640 disable_irq_nosync(irq);
641
642 return IRQ_HANDLED;
643 }
644
645 static void txx9dmac_tasklet(unsigned long data)
646 {
647 int irq;
648 u32 csr;
649 struct txx9dmac_chan *dc;
650
651 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
652 u32 mcr;
653 int i;
654
655 mcr = dma_readl(ddev, MCR);
656 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
657 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
658 if ((mcr >> (24 + i)) & 0x11) {
659 dc = ddev->chan[i];
660 csr = channel_readl(dc, CSR);
661 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
662 csr);
663 spin_lock(&dc->lock);
664 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
665 TXX9_DMA_CSR_NTRNFC))
666 txx9dmac_scan_descriptors(dc);
667 spin_unlock(&dc->lock);
668 }
669 }
670 irq = ddev->irq;
671
672 enable_irq(irq);
673 }
674
675 static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
676 {
677 struct txx9dmac_dev *ddev = dev_id;
678
679 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
680 dma_readl(ddev, MCR));
681
682 tasklet_schedule(&ddev->tasklet);
683 /*
684 * Just disable the interrupts. We'll turn them back on in the
685 * softirq handler.
686 */
687 disable_irq_nosync(irq);
688
689 return IRQ_HANDLED;
690 }
691
692 /*----------------------------------------------------------------------*/
693
694 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
695 {
696 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
697 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
698 dma_cookie_t cookie;
699
700 spin_lock_bh(&dc->lock);
701 cookie = dma_cookie_assign(tx);
702
703 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
704 desc->txd.cookie, desc);
705
706 list_add_tail(&desc->desc_node, &dc->queue);
707 spin_unlock_bh(&dc->lock);
708
709 return cookie;
710 }
711
712 static struct dma_async_tx_descriptor *
713 txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
714 size_t len, unsigned long flags)
715 {
716 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
717 struct txx9dmac_dev *ddev = dc->ddev;
718 struct txx9dmac_desc *desc;
719 struct txx9dmac_desc *first;
720 struct txx9dmac_desc *prev;
721 size_t xfer_count;
722 size_t offset;
723
724 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
725 (u64)dest, (u64)src, len, flags);
726
727 if (unlikely(!len)) {
728 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
729 return NULL;
730 }
731
732 prev = first = NULL;
733
734 for (offset = 0; offset < len; offset += xfer_count) {
735 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
736 /*
737 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
738 * ERT-TX49H4-016 (slightly conservative)
739 */
740 if (__is_dmac64(ddev)) {
741 if (xfer_count > 0x100 &&
742 (xfer_count & 0xff) >= 0xfa &&
743 (xfer_count & 0xff) <= 0xff)
744 xfer_count -= 0x20;
745 } else {
746 if (xfer_count > 0x80 &&
747 (xfer_count & 0x7f) >= 0x7e &&
748 (xfer_count & 0x7f) <= 0x7f)
749 xfer_count -= 0x20;
750 }
751
752 desc = txx9dmac_desc_get(dc);
753 if (!desc) {
754 txx9dmac_desc_put(dc, first);
755 return NULL;
756 }
757
758 if (__is_dmac64(ddev)) {
759 desc->hwdesc.SAR = src + offset;
760 desc->hwdesc.DAR = dest + offset;
761 desc->hwdesc.CNTR = xfer_count;
762 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
763 dc->ccr | TXX9_DMA_CCR_XFACT);
764 } else {
765 desc->hwdesc32.SAR = src + offset;
766 desc->hwdesc32.DAR = dest + offset;
767 desc->hwdesc32.CNTR = xfer_count;
768 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
769 dc->ccr | TXX9_DMA_CCR_XFACT);
770 }
771
772 /*
773 * The descriptors on tx_list are not reachable from
774 * the dc->queue list or dc->active_list after a
775 * submit. If we put all descriptors on active_list,
776 * calling of callback on the completion will be more
777 * complex.
778 */
779 if (!first) {
780 first = desc;
781 } else {
782 desc_write_CHAR(dc, prev, desc->txd.phys);
783 dma_sync_single_for_device(chan2parent(&dc->chan),
784 prev->txd.phys, ddev->descsize,
785 DMA_TO_DEVICE);
786 list_add_tail(&desc->desc_node, &first->tx_list);
787 }
788 prev = desc;
789 }
790
791 /* Trigger interrupt after last block */
792 if (flags & DMA_PREP_INTERRUPT)
793 txx9dmac_desc_set_INTENT(ddev, prev);
794
795 desc_write_CHAR(dc, prev, 0);
796 dma_sync_single_for_device(chan2parent(&dc->chan),
797 prev->txd.phys, ddev->descsize,
798 DMA_TO_DEVICE);
799
800 first->txd.flags = flags;
801 first->len = len;
802
803 return &first->txd;
804 }
805
806 static struct dma_async_tx_descriptor *
807 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
808 unsigned int sg_len, enum dma_transfer_direction direction,
809 unsigned long flags, void *context)
810 {
811 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
812 struct txx9dmac_dev *ddev = dc->ddev;
813 struct txx9dmac_slave *ds = chan->private;
814 struct txx9dmac_desc *prev;
815 struct txx9dmac_desc *first;
816 unsigned int i;
817 struct scatterlist *sg;
818
819 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
820
821 BUG_ON(!ds || !ds->reg_width);
822 if (ds->tx_reg)
823 BUG_ON(direction != DMA_MEM_TO_DEV);
824 else
825 BUG_ON(direction != DMA_DEV_TO_MEM);
826 if (unlikely(!sg_len))
827 return NULL;
828
829 prev = first = NULL;
830
831 for_each_sg(sgl, sg, sg_len, i) {
832 struct txx9dmac_desc *desc;
833 dma_addr_t mem;
834 u32 sai, dai;
835
836 desc = txx9dmac_desc_get(dc);
837 if (!desc) {
838 txx9dmac_desc_put(dc, first);
839 return NULL;
840 }
841
842 mem = sg_dma_address(sg);
843
844 if (__is_dmac64(ddev)) {
845 if (direction == DMA_MEM_TO_DEV) {
846 desc->hwdesc.SAR = mem;
847 desc->hwdesc.DAR = ds->tx_reg;
848 } else {
849 desc->hwdesc.SAR = ds->rx_reg;
850 desc->hwdesc.DAR = mem;
851 }
852 desc->hwdesc.CNTR = sg_dma_len(sg);
853 } else {
854 if (direction == DMA_MEM_TO_DEV) {
855 desc->hwdesc32.SAR = mem;
856 desc->hwdesc32.DAR = ds->tx_reg;
857 } else {
858 desc->hwdesc32.SAR = ds->rx_reg;
859 desc->hwdesc32.DAR = mem;
860 }
861 desc->hwdesc32.CNTR = sg_dma_len(sg);
862 }
863 if (direction == DMA_MEM_TO_DEV) {
864 sai = ds->reg_width;
865 dai = 0;
866 } else {
867 sai = 0;
868 dai = ds->reg_width;
869 }
870 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
871 dc->ccr | TXX9_DMA_CCR_XFACT);
872
873 if (!first) {
874 first = desc;
875 } else {
876 desc_write_CHAR(dc, prev, desc->txd.phys);
877 dma_sync_single_for_device(chan2parent(&dc->chan),
878 prev->txd.phys,
879 ddev->descsize,
880 DMA_TO_DEVICE);
881 list_add_tail(&desc->desc_node, &first->tx_list);
882 }
883 prev = desc;
884 }
885
886 /* Trigger interrupt after last block */
887 if (flags & DMA_PREP_INTERRUPT)
888 txx9dmac_desc_set_INTENT(ddev, prev);
889
890 desc_write_CHAR(dc, prev, 0);
891 dma_sync_single_for_device(chan2parent(&dc->chan),
892 prev->txd.phys, ddev->descsize,
893 DMA_TO_DEVICE);
894
895 first->txd.flags = flags;
896 first->len = 0;
897
898 return &first->txd;
899 }
900
901 static int txx9dmac_terminate_all(struct dma_chan *chan)
902 {
903 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
904 struct txx9dmac_desc *desc, *_desc;
905 LIST_HEAD(list);
906
907 dev_vdbg(chan2dev(chan), "terminate_all\n");
908 spin_lock_bh(&dc->lock);
909
910 txx9dmac_reset_chan(dc);
911
912 /* active_list entries will end up before queued entries */
913 list_splice_init(&dc->queue, &list);
914 list_splice_init(&dc->active_list, &list);
915
916 spin_unlock_bh(&dc->lock);
917
918 /* Flush all pending and queued descriptors */
919 list_for_each_entry_safe(desc, _desc, &list, desc_node)
920 txx9dmac_descriptor_complete(dc, desc);
921
922 return 0;
923 }
924
925 static enum dma_status
926 txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
927 struct dma_tx_state *txstate)
928 {
929 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
930 enum dma_status ret;
931
932 ret = dma_cookie_status(chan, cookie, txstate);
933 if (ret == DMA_COMPLETE)
934 return DMA_COMPLETE;
935
936 spin_lock_bh(&dc->lock);
937 txx9dmac_scan_descriptors(dc);
938 spin_unlock_bh(&dc->lock);
939
940 return dma_cookie_status(chan, cookie, txstate);
941 }
942
943 static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
944 struct txx9dmac_desc *prev)
945 {
946 struct txx9dmac_dev *ddev = dc->ddev;
947 struct txx9dmac_desc *desc;
948 LIST_HEAD(list);
949
950 prev = txx9dmac_last_child(prev);
951 txx9dmac_dequeue(dc, &list);
952 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
953 desc_write_CHAR(dc, prev, desc->txd.phys);
954 dma_sync_single_for_device(chan2parent(&dc->chan),
955 prev->txd.phys, ddev->descsize,
956 DMA_TO_DEVICE);
957 mmiowb();
958 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
959 channel_read_CHAR(dc) == prev->txd.phys)
960 /* Restart chain DMA */
961 channel_write_CHAR(dc, desc->txd.phys);
962 list_splice_tail(&list, &dc->active_list);
963 }
964
965 static void txx9dmac_issue_pending(struct dma_chan *chan)
966 {
967 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
968
969 spin_lock_bh(&dc->lock);
970
971 if (!list_empty(&dc->active_list))
972 txx9dmac_scan_descriptors(dc);
973 if (!list_empty(&dc->queue)) {
974 if (list_empty(&dc->active_list)) {
975 txx9dmac_dequeue(dc, &dc->active_list);
976 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
977 } else if (txx9_dma_have_SMPCHN()) {
978 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
979
980 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
981 txx9dmac_chan_INTENT(dc))
982 txx9dmac_chain_dynamic(dc, prev);
983 }
984 }
985
986 spin_unlock_bh(&dc->lock);
987 }
988
989 static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
990 {
991 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
992 struct txx9dmac_slave *ds = chan->private;
993 struct txx9dmac_desc *desc;
994 int i;
995
996 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
997
998 /* ASSERT: channel is idle */
999 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1000 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1001 return -EIO;
1002 }
1003
1004 dma_cookie_init(chan);
1005
1006 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1007 txx9dmac_chan_set_SMPCHN(dc);
1008 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1009 dc->ccr |= TXX9_DMA_CCR_INTENC;
1010 if (chan->device->device_prep_dma_memcpy) {
1011 if (ds)
1012 return -EINVAL;
1013 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1014 } else {
1015 if (!ds ||
1016 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1017 return -EINVAL;
1018 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1019 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1020 txx9dmac_chan_set_INTENT(dc);
1021 }
1022
1023 spin_lock_bh(&dc->lock);
1024 i = dc->descs_allocated;
1025 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1026 spin_unlock_bh(&dc->lock);
1027
1028 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1029 if (!desc) {
1030 dev_info(chan2dev(chan),
1031 "only allocated %d descriptors\n", i);
1032 spin_lock_bh(&dc->lock);
1033 break;
1034 }
1035 txx9dmac_desc_put(dc, desc);
1036
1037 spin_lock_bh(&dc->lock);
1038 i = ++dc->descs_allocated;
1039 }
1040 spin_unlock_bh(&dc->lock);
1041
1042 dev_dbg(chan2dev(chan),
1043 "alloc_chan_resources allocated %d descriptors\n", i);
1044
1045 return i;
1046 }
1047
1048 static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1049 {
1050 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1051 struct txx9dmac_dev *ddev = dc->ddev;
1052 struct txx9dmac_desc *desc, *_desc;
1053 LIST_HEAD(list);
1054
1055 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1056 dc->descs_allocated);
1057
1058 /* ASSERT: channel is idle */
1059 BUG_ON(!list_empty(&dc->active_list));
1060 BUG_ON(!list_empty(&dc->queue));
1061 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1062
1063 spin_lock_bh(&dc->lock);
1064 list_splice_init(&dc->free_list, &list);
1065 dc->descs_allocated = 0;
1066 spin_unlock_bh(&dc->lock);
1067
1068 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1069 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1070 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1071 ddev->descsize, DMA_TO_DEVICE);
1072 kfree(desc);
1073 }
1074
1075 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1076 }
1077
1078 /*----------------------------------------------------------------------*/
1079
1080 static void txx9dmac_off(struct txx9dmac_dev *ddev)
1081 {
1082 dma_writel(ddev, MCR, 0);
1083 mmiowb();
1084 }
1085
1086 static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1087 {
1088 struct txx9dmac_chan_platform_data *cpdata =
1089 dev_get_platdata(&pdev->dev);
1090 struct platform_device *dmac_dev = cpdata->dmac_dev;
1091 struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1092 struct txx9dmac_chan *dc;
1093 int err;
1094 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1095 int irq;
1096
1097 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1098 if (!dc)
1099 return -ENOMEM;
1100
1101 dc->dma.dev = &pdev->dev;
1102 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1103 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1104 dc->dma.device_terminate_all = txx9dmac_terminate_all;
1105 dc->dma.device_tx_status = txx9dmac_tx_status;
1106 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1107 if (pdata && pdata->memcpy_chan == ch) {
1108 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1109 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1110 } else {
1111 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1112 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1113 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1114 }
1115
1116 INIT_LIST_HEAD(&dc->dma.channels);
1117 dc->ddev = platform_get_drvdata(dmac_dev);
1118 if (dc->ddev->irq < 0) {
1119 irq = platform_get_irq(pdev, 0);
1120 if (irq < 0)
1121 return irq;
1122 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1123 (unsigned long)dc);
1124 dc->irq = irq;
1125 err = devm_request_irq(&pdev->dev, dc->irq,
1126 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1127 if (err)
1128 return err;
1129 } else
1130 dc->irq = -1;
1131 dc->ddev->chan[ch] = dc;
1132 dc->chan.device = &dc->dma;
1133 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1134 dma_cookie_init(&dc->chan);
1135
1136 if (is_dmac64(dc))
1137 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1138 else
1139 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1140 spin_lock_init(&dc->lock);
1141
1142 INIT_LIST_HEAD(&dc->active_list);
1143 INIT_LIST_HEAD(&dc->queue);
1144 INIT_LIST_HEAD(&dc->free_list);
1145
1146 txx9dmac_reset_chan(dc);
1147
1148 platform_set_drvdata(pdev, dc);
1149
1150 err = dma_async_device_register(&dc->dma);
1151 if (err)
1152 return err;
1153 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1154 dc->dma.dev_id,
1155 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1156 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1157
1158 return 0;
1159 }
1160
1161 static int txx9dmac_chan_remove(struct platform_device *pdev)
1162 {
1163 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1164
1165
1166 dma_async_device_unregister(&dc->dma);
1167 if (dc->irq >= 0) {
1168 devm_free_irq(&pdev->dev, dc->irq, dc);
1169 tasklet_kill(&dc->tasklet);
1170 }
1171 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1172 return 0;
1173 }
1174
1175 static int __init txx9dmac_probe(struct platform_device *pdev)
1176 {
1177 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1178 struct resource *io;
1179 struct txx9dmac_dev *ddev;
1180 u32 mcr;
1181 int err;
1182
1183 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 if (!io)
1185 return -EINVAL;
1186
1187 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1188 if (!ddev)
1189 return -ENOMEM;
1190
1191 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1192 dev_name(&pdev->dev)))
1193 return -EBUSY;
1194
1195 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1196 if (!ddev->regs)
1197 return -ENOMEM;
1198 ddev->have_64bit_regs = pdata->have_64bit_regs;
1199 if (__is_dmac64(ddev))
1200 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1201 else
1202 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1203
1204 /* force dma off, just in case */
1205 txx9dmac_off(ddev);
1206
1207 ddev->irq = platform_get_irq(pdev, 0);
1208 if (ddev->irq >= 0) {
1209 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1210 (unsigned long)ddev);
1211 err = devm_request_irq(&pdev->dev, ddev->irq,
1212 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1213 if (err)
1214 return err;
1215 }
1216
1217 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1218 if (pdata && pdata->memcpy_chan >= 0)
1219 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1220 dma_writel(ddev, MCR, mcr);
1221
1222 platform_set_drvdata(pdev, ddev);
1223 return 0;
1224 }
1225
1226 static int txx9dmac_remove(struct platform_device *pdev)
1227 {
1228 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1229
1230 txx9dmac_off(ddev);
1231 if (ddev->irq >= 0) {
1232 devm_free_irq(&pdev->dev, ddev->irq, ddev);
1233 tasklet_kill(&ddev->tasklet);
1234 }
1235 return 0;
1236 }
1237
1238 static void txx9dmac_shutdown(struct platform_device *pdev)
1239 {
1240 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1241
1242 txx9dmac_off(ddev);
1243 }
1244
1245 static int txx9dmac_suspend_noirq(struct device *dev)
1246 {
1247 struct platform_device *pdev = to_platform_device(dev);
1248 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1249
1250 txx9dmac_off(ddev);
1251 return 0;
1252 }
1253
1254 static int txx9dmac_resume_noirq(struct device *dev)
1255 {
1256 struct platform_device *pdev = to_platform_device(dev);
1257 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1258 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1259 u32 mcr;
1260
1261 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1262 if (pdata && pdata->memcpy_chan >= 0)
1263 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1264 dma_writel(ddev, MCR, mcr);
1265 return 0;
1266
1267 }
1268
1269 static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1270 .suspend_noirq = txx9dmac_suspend_noirq,
1271 .resume_noirq = txx9dmac_resume_noirq,
1272 };
1273
1274 static struct platform_driver txx9dmac_chan_driver = {
1275 .remove = txx9dmac_chan_remove,
1276 .driver = {
1277 .name = "txx9dmac-chan",
1278 },
1279 };
1280
1281 static struct platform_driver txx9dmac_driver = {
1282 .remove = txx9dmac_remove,
1283 .shutdown = txx9dmac_shutdown,
1284 .driver = {
1285 .name = "txx9dmac",
1286 .pm = &txx9dmac_dev_pm_ops,
1287 },
1288 };
1289
1290 static int __init txx9dmac_init(void)
1291 {
1292 int rc;
1293
1294 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1295 if (!rc) {
1296 rc = platform_driver_probe(&txx9dmac_chan_driver,
1297 txx9dmac_chan_probe);
1298 if (rc)
1299 platform_driver_unregister(&txx9dmac_driver);
1300 }
1301 return rc;
1302 }
1303 module_init(txx9dmac_init);
1304
1305 static void __exit txx9dmac_exit(void)
1306 {
1307 platform_driver_unregister(&txx9dmac_chan_driver);
1308 platform_driver_unregister(&txx9dmac_driver);
1309 }
1310 module_exit(txx9dmac_exit);
1311
1312 MODULE_LICENSE("GPL");
1313 MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1314 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1315 MODULE_ALIAS("platform:txx9dmac");
1316 MODULE_ALIAS("platform:txx9dmac-chan");
Linux with added FPC-III support