2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/input.h>
21 #include <linux/delay.h>
23 #include <linux/spi/flash.h>
24 #include <linux/spi/spi.h>
25 #include <linux/mfd/mc13892.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/consumer.h>
29 #include <mach/common.h>
30 #include <mach/hardware.h>
31 #include <mach/iomux-mx51.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/ulpi.h>
35 #include <mach/ulpi.h>
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
42 #include "devices-imx51.h"
44 #include "cpu_op-mx51.h"
46 #define MX51_USB_CTRL_1_OFFSET 0x10
47 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
50 #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
51 #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
53 #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
54 #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
56 #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
58 static iomux_v3_cfg_t mx51efika_pads
[] = {
60 MX51_PAD_UART1_RXD__UART1_RXD
,
61 MX51_PAD_UART1_TXD__UART1_TXD
,
62 MX51_PAD_UART1_RTS__UART1_RTS
,
63 MX51_PAD_UART1_CTS__UART1_CTS
,
66 MX51_PAD_SD1_CMD__SD1_CMD
,
67 MX51_PAD_SD1_CLK__SD1_CLK
,
68 MX51_PAD_SD1_DATA0__SD1_DATA0
,
69 MX51_PAD_SD1_DATA1__SD1_DATA1
,
70 MX51_PAD_SD1_DATA2__SD1_DATA2
,
71 MX51_PAD_SD1_DATA3__SD1_DATA3
,
74 MX51_PAD_SD2_CMD__SD2_CMD
,
75 MX51_PAD_SD2_CLK__SD2_CLK
,
76 MX51_PAD_SD2_DATA0__SD2_DATA0
,
77 MX51_PAD_SD2_DATA1__SD2_DATA1
,
78 MX51_PAD_SD2_DATA2__SD2_DATA2
,
79 MX51_PAD_SD2_DATA3__SD2_DATA3
,
82 MX51_PAD_GPIO1_0__SD1_CD
,
83 MX51_PAD_GPIO1_1__SD1_WP
,
84 MX51_PAD_GPIO1_7__SD2_WP
,
85 MX51_PAD_GPIO1_8__SD2_CD
,
88 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI
,
89 MX51_PAD_CSPI1_MISO__ECSPI1_MISO
,
90 MX51_PAD_CSPI1_SS0__GPIO4_24
,
91 MX51_PAD_CSPI1_SS1__GPIO4_25
,
92 MX51_PAD_CSPI1_RDY__ECSPI1_RDY
,
93 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK
,
94 MX51_PAD_GPIO1_6__GPIO1_6
,
97 MX51_PAD_USBH1_CLK__USBH1_CLK
,
98 MX51_PAD_USBH1_DIR__USBH1_DIR
,
99 MX51_PAD_USBH1_NXT__USBH1_NXT
,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0
,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1
,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2
,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3
,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4
,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5
,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6
,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7
,
110 MX51_PAD_GPIO1_5__GPIO1_5
,
113 MX51_PAD_EIM_A22__GPIO2_16
,
114 MX51_PAD_EIM_A16__GPIO2_10
,
117 MX51_PAD_EIM_D27__GPIO2_9
,
121 static const struct imxuart_platform_data uart_pdata
= {
122 .flags
= IMXUART_HAVE_RTSCTS
,
125 /* This function is board specific as the bit mask for the plldiv will also
126 * be different for other Freescale SoCs, thus a common bitmask is not
127 * possible and cannot get place in /plat-mxc/ehci.c.
129 static int initialize_otg_port(struct platform_device
*pdev
)
132 void __iomem
*usb_base
;
133 void __iomem
*usbother_base
;
134 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
137 usbother_base
= (void __iomem
*)(usb_base
+ MX5_USBOTHER_REGS_OFFSET
);
139 /* Set the PHY clock to 19.2MHz */
140 v
= __raw_readl(usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
141 v
&= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
142 v
|= MX51_USB_PLL_DIV_19_2_MHZ
;
143 __raw_writel(v
, usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
148 return mx51_initialize_usb_hw(pdev
->id
, MXC_EHCI_INTERNAL_PHY
);
151 static const struct mxc_usbh_platform_data dr_utmi_config __initconst
= {
152 .init
= initialize_otg_port
,
153 .portsc
= MXC_EHCI_UTMI_16BIT
,
156 static int initialize_usbh1_port(struct platform_device
*pdev
)
158 iomux_v3_cfg_t usbh1stp
= MX51_PAD_USBH1_STP__USBH1_STP
;
159 iomux_v3_cfg_t usbh1gpio
= MX51_PAD_USBH1_STP__GPIO1_27
;
161 void __iomem
*usb_base
;
162 void __iomem
*socregs_base
;
164 mxc_iomux_v3_setup_pad(usbh1gpio
);
165 gpio_request(EFIKAMX_USBH1_STP
, "usbh1_stp");
166 gpio_direction_output(EFIKAMX_USBH1_STP
, 0);
168 gpio_set_value(EFIKAMX_USBH1_STP
, 1);
171 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
172 socregs_base
= (void __iomem
*)(usb_base
+ MX5_USBOTHER_REGS_OFFSET
);
174 /* The clock for the USBH1 ULPI port will come externally */
176 v
= __raw_readl(socregs_base
+ MX51_USB_CTRL_1_OFFSET
);
177 __raw_writel(v
| MX51_USB_CTRL_UH1_EXT_CLK_EN
,
178 socregs_base
+ MX51_USB_CTRL_1_OFFSET
);
182 gpio_free(EFIKAMX_USBH1_STP
);
183 mxc_iomux_v3_setup_pad(usbh1stp
);
187 return mx51_initialize_usb_hw(pdev
->id
, MXC_EHCI_ITC_NO_THRESHOLD
);
190 static struct mxc_usbh_platform_data usbh1_config __initdata
= {
191 .init
= initialize_usbh1_port
,
192 .portsc
= MXC_EHCI_MODE_ULPI
,
195 static void mx51_efika_hubreset(void)
197 gpio_request(EFIKAMX_USB_HUB_RESET
, "usb_hub_rst");
198 gpio_direction_output(EFIKAMX_USB_HUB_RESET
, 1);
200 gpio_set_value(EFIKAMX_USB_HUB_RESET
, 0);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET
, 1);
205 static void __init
mx51_efika_usb(void)
207 mx51_efika_hubreset();
209 /* pulling it low, means no USB at all... */
210 gpio_request(EFIKA_USB_PHY_RESET
, "usb_phy_reset");
211 gpio_direction_output(EFIKA_USB_PHY_RESET
, 0);
213 gpio_set_value(EFIKA_USB_PHY_RESET
, 1);
215 usbh1_config
.otg
= imx_otg_ulpi_create(ULPI_OTG_DRVVBUS
|
216 ULPI_OTG_DRVVBUS_EXT
| ULPI_OTG_EXTVBUSIND
);
218 imx51_add_mxc_ehci_otg(&dr_utmi_config
);
219 if (usbh1_config
.otg
)
220 imx51_add_mxc_ehci_hs(1, &usbh1_config
);
223 static struct mtd_partition mx51_efika_spi_nor_partitions
[] = {
231 .offset
= MTDPART_OFS_APPEND
,
236 static struct flash_platform_data mx51_efika_spi_flash_data
= {
238 .parts
= mx51_efika_spi_nor_partitions
,
239 .nr_parts
= ARRAY_SIZE(mx51_efika_spi_nor_partitions
),
240 .type
= "sst25vf032b",
243 static struct regulator_consumer_supply sw1_consumers
[] = {
249 static struct regulator_consumer_supply vdig_consumers
[] = {
251 REGULATOR_SUPPLY("VDDA", "1-000a"),
252 REGULATOR_SUPPLY("VDDD", "1-000a"),
255 static struct regulator_consumer_supply vvideo_consumers
[] = {
257 REGULATOR_SUPPLY("VDDIO", "1-000a"),
260 static struct regulator_consumer_supply vsd_consumers
[] = {
261 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
262 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
265 static struct regulator_consumer_supply pwgt1_consumer
[] = {
271 static struct regulator_consumer_supply pwgt2_consumer
[] = {
277 static struct regulator_consumer_supply coincell_consumer
[] = {
279 .supply
= "coincell",
283 static struct regulator_init_data sw1_init
= {
288 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
289 .valid_modes_mask
= 0,
294 .mode
= REGULATOR_MODE_NORMAL
,
298 .num_consumer_supplies
= ARRAY_SIZE(sw1_consumers
),
299 .consumer_supplies
= sw1_consumers
,
302 static struct regulator_init_data sw2_init
= {
307 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
312 .mode
= REGULATOR_MODE_NORMAL
,
318 static struct regulator_init_data sw3_init
= {
323 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
329 static struct regulator_init_data sw4_init
= {
334 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
340 static struct regulator_init_data viohi_init
= {
348 static struct regulator_init_data vusb_init
= {
356 static struct regulator_init_data swbst_init
= {
362 static struct regulator_init_data vdig_init
= {
368 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
372 .num_consumer_supplies
= ARRAY_SIZE(vdig_consumers
),
373 .consumer_supplies
= vdig_consumers
,
376 static struct regulator_init_data vpll_init
= {
382 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
388 static struct regulator_init_data vusb2_init
= {
393 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
399 static struct regulator_init_data vvideo_init
= {
405 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
409 .num_consumer_supplies
= ARRAY_SIZE(vvideo_consumers
),
410 .consumer_supplies
= vvideo_consumers
,
413 static struct regulator_init_data vaudio_init
= {
419 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
424 static struct regulator_init_data vsd_init
= {
430 REGULATOR_CHANGE_VOLTAGE
,
433 .num_consumer_supplies
= ARRAY_SIZE(vsd_consumers
),
434 .consumer_supplies
= vsd_consumers
,
437 static struct regulator_init_data vcam_init
= {
443 REGULATOR_CHANGE_VOLTAGE
|
444 REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS
,
445 .valid_modes_mask
= REGULATOR_MODE_FAST
| REGULATOR_MODE_NORMAL
,
450 static struct regulator_init_data vgen1_init
= {
456 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
462 static struct regulator_init_data vgen2_init
= {
468 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
474 static struct regulator_init_data vgen3_init
= {
480 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
486 static struct regulator_init_data gpo1_init
= {
492 static struct regulator_init_data gpo2_init
= {
498 static struct regulator_init_data gpo3_init
= {
504 static struct regulator_init_data gpo4_init
= {
510 static struct regulator_init_data pwgt1_init
= {
512 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
515 .num_consumer_supplies
= ARRAY_SIZE(pwgt1_consumer
),
516 .consumer_supplies
= pwgt1_consumer
,
519 static struct regulator_init_data pwgt2_init
= {
521 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
524 .num_consumer_supplies
= ARRAY_SIZE(pwgt2_consumer
),
525 .consumer_supplies
= pwgt2_consumer
,
528 static struct regulator_init_data vcoincell_init
= {
534 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
536 .num_consumer_supplies
= ARRAY_SIZE(coincell_consumer
),
537 .consumer_supplies
= coincell_consumer
,
540 static struct mc13xxx_regulator_init_data mx51_efika_regulators
[] = {
541 { .id
= MC13892_SW1
, .init_data
= &sw1_init
},
542 { .id
= MC13892_SW2
, .init_data
= &sw2_init
},
543 { .id
= MC13892_SW3
, .init_data
= &sw3_init
},
544 { .id
= MC13892_SW4
, .init_data
= &sw4_init
},
545 { .id
= MC13892_SWBST
, .init_data
= &swbst_init
},
546 { .id
= MC13892_VIOHI
, .init_data
= &viohi_init
},
547 { .id
= MC13892_VPLL
, .init_data
= &vpll_init
},
548 { .id
= MC13892_VDIG
, .init_data
= &vdig_init
},
549 { .id
= MC13892_VSD
, .init_data
= &vsd_init
},
550 { .id
= MC13892_VUSB2
, .init_data
= &vusb2_init
},
551 { .id
= MC13892_VVIDEO
, .init_data
= &vvideo_init
},
552 { .id
= MC13892_VAUDIO
, .init_data
= &vaudio_init
},
553 { .id
= MC13892_VCAM
, .init_data
= &vcam_init
},
554 { .id
= MC13892_VGEN1
, .init_data
= &vgen1_init
},
555 { .id
= MC13892_VGEN2
, .init_data
= &vgen2_init
},
556 { .id
= MC13892_VGEN3
, .init_data
= &vgen3_init
},
557 { .id
= MC13892_VUSB
, .init_data
= &vusb_init
},
558 { .id
= MC13892_GPO1
, .init_data
= &gpo1_init
},
559 { .id
= MC13892_GPO2
, .init_data
= &gpo2_init
},
560 { .id
= MC13892_GPO3
, .init_data
= &gpo3_init
},
561 { .id
= MC13892_GPO4
, .init_data
= &gpo4_init
},
562 { .id
= MC13892_PWGT1SPI
, .init_data
= &pwgt1_init
},
563 { .id
= MC13892_PWGT2SPI
, .init_data
= &pwgt2_init
},
564 { .id
= MC13892_VCOINCELL
, .init_data
= &vcoincell_init
},
567 static struct mc13xxx_platform_data mx51_efika_mc13892_data
= {
568 .flags
= MC13XXX_USE_RTC
,
570 .num_regulators
= ARRAY_SIZE(mx51_efika_regulators
),
571 .regulators
= mx51_efika_regulators
,
575 static struct spi_board_info mx51_efika_spi_board_info
[] __initdata
= {
577 .modalias
= "m25p80",
578 .max_speed_hz
= 25000000,
581 .platform_data
= &mx51_efika_spi_flash_data
,
585 .modalias
= "mc13892",
586 .max_speed_hz
= 1000000,
589 .platform_data
= &mx51_efika_mc13892_data
,
590 /* irq number is run-time assigned */
594 static int mx51_efika_spi_cs
[] = {
599 static const struct spi_imx_master mx51_efika_spi_pdata __initconst
= {
600 .chipselect
= mx51_efika_spi_cs
,
601 .num_chipselect
= ARRAY_SIZE(mx51_efika_spi_cs
),
604 void __init
efika_board_common_init(void)
606 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads
,
607 ARRAY_SIZE(mx51efika_pads
));
608 imx51_add_imx_uart(0, &uart_pdata
);
611 /* FIXME: comes from original code. check this. */
612 if (mx51_revision() < IMX_CHIP_REVISION_2_0
)
613 sw2_init
.constraints
.state_mem
.uV
= 1100000;
614 else if (mx51_revision() == IMX_CHIP_REVISION_2_0
) {
615 sw2_init
.constraints
.state_mem
.uV
= 1250000;
616 sw1_init
.constraints
.state_mem
.uV
= 1000000;
618 if (machine_is_mx51_efikasb())
619 vgen1_init
.constraints
.max_uV
= 1200000;
621 gpio_request(EFIKAMX_PMIC
, "pmic irq");
622 gpio_direction_input(EFIKAMX_PMIC
);
623 mx51_efika_spi_board_info
[1].irq
= gpio_to_irq(EFIKAMX_PMIC
);
624 spi_register_board_info(mx51_efika_spi_board_info
,
625 ARRAY_SIZE(mx51_efika_spi_board_info
));
626 imx51_add_ecspi(0, &mx51_efika_spi_pdata
);
628 imx51_add_pata_imx();
630 #if defined(CONFIG_CPU_FREQ_IMX)
631 get_cpu_op
= mx51_get_cpu_op
;