drm/omap: Fix error handling path in 'omap_dmm_probe()'
[linux/fpc-iii.git] / drivers / clocksource / timer-sp.h
blob050d88561e9c6b346259ff9cb476ea798cf57834
1 /*
2 * ARM timer implementation, found in Integrator, Versatile and Realview
3 * platforms. Not all platforms support all registers and bits in these
4 * registers, so we mark them with A for Integrator AP, C for Integrator
5 * CP, V for Versatile and R for Realview.
7 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
8 * can have 16-bit or 32-bit selectable via a bit in the control register.
10 * Every SP804 contains two identical timers.
12 #define TIMER_1_BASE 0x00
13 #define TIMER_2_BASE 0x20
15 #define TIMER_LOAD 0x00 /* ACVR rw */
16 #define TIMER_VALUE 0x04 /* ACVR ro */
17 #define TIMER_CTRL 0x08 /* ACVR rw */
18 #define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */
19 #define TIMER_CTRL_32BIT (1 << 1) /* CVR */
20 #define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */
21 #define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */
22 #define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */
23 #define TIMER_CTRL_IE (1 << 5) /* VR */
24 #define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */
25 #define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */
27 #define TIMER_INTCLR 0x0c /* ACVR wo */
28 #define TIMER_RIS 0x10 /* CVR ro */
29 #define TIMER_MIS 0x14 /* CVR ro */
30 #define TIMER_BGLOAD 0x18 /* CVR rw */