Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
[linux/fpc-iii.git] / arch / powerpc / kernel / fpu.S
blobe0ada05f2df31f16f61e07259bce6d4549d8aa25
1 /*
2  *  FPU support code, moved here from head.S so that it can be used
3  *  by chips which use other head-whatever.S files.
4  *
5  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7  *    Copyright (C) 1996 Paul Mackerras.
8  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9  *
10  *  This program is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU General Public License
12  *  as published by the Free Software Foundation; either version
13  *  2 of the License, or (at your option) any later version.
14  *
15  */
17 #include <asm/reg.h>
18 #include <asm/page.h>
19 #include <asm/mmu.h>
20 #include <asm/pgtable.h>
21 #include <asm/cputable.h>
22 #include <asm/cache.h>
23 #include <asm/thread_info.h>
24 #include <asm/ppc_asm.h>
25 #include <asm/asm-offsets.h>
26 #include <asm/ptrace.h>
28 #ifdef CONFIG_VSX
29 #define __REST_32FPVSRS(n,c,base)                                       \
30 BEGIN_FTR_SECTION                                                       \
31         b       2f;                                                     \
32 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
33         REST_32FPRS(n,base);                                            \
34         b       3f;                                                     \
35 2:      REST_32VSRS(n,c,base);                                          \
38 #define __SAVE_32FPVSRS(n,c,base)                                       \
39 BEGIN_FTR_SECTION                                                       \
40         b       2f;                                                     \
41 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
42         SAVE_32FPRS(n,base);                                            \
43         b       3f;                                                     \
44 2:      SAVE_32VSRS(n,c,base);                                          \
46 #else
47 #define __REST_32FPVSRS(n,b,base)       REST_32FPRS(n, base)
48 #define __SAVE_32FPVSRS(n,b,base)       SAVE_32FPRS(n, base)
49 #endif
50 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
51 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
54  * This task wants to use the FPU now.
55  * On UP, disable FP for the task which had the FPU previously,
56  * and save its floating-point registers in its thread_struct.
57  * Load up this task's FP registers from its thread_struct,
58  * enable the FPU for the current task and return to the task.
59  */
60 _GLOBAL(load_up_fpu)
61         mfmsr   r5
62         ori     r5,r5,MSR_FP
63 #ifdef CONFIG_VSX
64 BEGIN_FTR_SECTION
65         oris    r5,r5,MSR_VSX@h
66 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
67 #endif
68         SYNC
69         MTMSRD(r5)                      /* enable use of fpu now */
70         isync
72  * For SMP, we don't do lazy FPU switching because it just gets too
73  * horrendously complex, especially when a task switches from one CPU
74  * to another.  Instead we call giveup_fpu in switch_to.
75  */
76 #ifndef CONFIG_SMP
77         LOAD_REG_ADDRBASE(r3, last_task_used_math)
78         toreal(r3)
79         PPC_LL  r4,ADDROFF(last_task_used_math)(r3)
80         PPC_LCMPI       0,r4,0
81         beq     1f
82         toreal(r4)
83         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
84         SAVE_32FPVSRS(0, R5, R4)
85         mffs    fr0
86         stfd    fr0,THREAD_FPSCR(r4)
87         PPC_LL  r5,PT_REGS(r4)
88         toreal(r5)
89         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
90         li      r10,MSR_FP|MSR_FE0|MSR_FE1
91         andc    r4,r4,r10               /* disable FP for previous task */
92         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
94 #endif /* CONFIG_SMP */
95         /* enable use of FP after return */
96 #ifdef CONFIG_PPC32
97         mfspr   r5,SPRN_SPRG_THREAD             /* current task's THREAD (phys) */
98         lwz     r4,THREAD_FPEXC_MODE(r5)
99         ori     r9,r9,MSR_FP            /* enable FP for current */
100         or      r9,r9,r4
101 #else
102         ld      r4,PACACURRENT(r13)
103         addi    r5,r4,THREAD            /* Get THREAD */
104         lwz     r4,THREAD_FPEXC_MODE(r5)
105         ori     r12,r12,MSR_FP
106         or      r12,r12,r4
107         std     r12,_MSR(r1)
108 #endif
109         lfd     fr0,THREAD_FPSCR(r5)
110         MTFSF_L(fr0)
111         REST_32FPVSRS(0, R4, R5)
112 #ifndef CONFIG_SMP
113         subi    r4,r5,THREAD
114         fromreal(r4)
115         PPC_STL r4,ADDROFF(last_task_used_math)(r3)
116 #endif /* CONFIG_SMP */
117         /* restore registers and return */
118         /* we haven't used ctr or xer or lr */
119         blr
122  * giveup_fpu(tsk)
123  * Disable FP for the task given as the argument,
124  * and save the floating-point registers in its thread_struct.
125  * Enables the FPU for use in the kernel on return.
126  */
127 _GLOBAL(giveup_fpu)
128         mfmsr   r5
129         ori     r5,r5,MSR_FP
130 #ifdef CONFIG_VSX
131 BEGIN_FTR_SECTION
132         oris    r5,r5,MSR_VSX@h
133 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
134 #endif
135         SYNC_601
136         ISYNC_601
137         MTMSRD(r5)                      /* enable use of fpu now */
138         SYNC_601
139         isync
140         PPC_LCMPI       0,r3,0
141         beqlr-                          /* if no previous owner, done */
142         addi    r3,r3,THREAD            /* want THREAD of task */
143         PPC_LL  r5,PT_REGS(r3)
144         PPC_LCMPI       0,r5,0
145         SAVE_32FPVSRS(0, R4 ,R3)
146         mffs    fr0
147         stfd    fr0,THREAD_FPSCR(r3)
148         beq     1f
149         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
150         li      r3,MSR_FP|MSR_FE0|MSR_FE1
151 #ifdef CONFIG_VSX
152 BEGIN_FTR_SECTION
153         oris    r3,r3,MSR_VSX@h
154 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
155 #endif
156         andc    r4,r4,r3                /* disable FP for previous task */
157         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
159 #ifndef CONFIG_SMP
160         li      r5,0
161         LOAD_REG_ADDRBASE(r4,last_task_used_math)
162         PPC_STL r5,ADDROFF(last_task_used_math)(r4)
163 #endif /* CONFIG_SMP */
164         blr
167  * These are used in the alignment trap handler when emulating
168  * single-precision loads and stores.
169  */
171 _GLOBAL(cvt_fd)
172         lfs     0,0(r3)
173         stfd    0,0(r4)
174         blr
176 _GLOBAL(cvt_df)
177         lfd     0,0(r3)
178         stfs    0,0(r4)
179         blr