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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / spi / spi-sh-msiof.c
blob03b566848da63dca6ed155eccc1381f5ebf735dd
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
33
34 #include <asm/unaligned.h>
35
36
37 struct sh_msiof_chipdata {
38 u16 tx_fifo_size;
39 u16 rx_fifo_size;
40 u16 master_flags;
41 };
42
43 struct sh_msiof_spi_priv {
44 struct spi_master *master;
45 void __iomem *mapbase;
46 struct clk *clk;
47 struct platform_device *pdev;
48 const struct sh_msiof_chipdata *chipdata;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 unsigned int tx_fifo_size;
52 unsigned int rx_fifo_size;
53 void *tx_dma_page;
54 void *rx_dma_page;
55 dma_addr_t tx_dma_addr;
56 dma_addr_t rx_dma_addr;
57 };
58
59 #define TMDR1 0x00 /* Transmit Mode Register 1 */
60 #define TMDR2 0x04 /* Transmit Mode Register 2 */
61 #define TMDR3 0x08 /* Transmit Mode Register 3 */
62 #define RMDR1 0x10 /* Receive Mode Register 1 */
63 #define RMDR2 0x14 /* Receive Mode Register 2 */
64 #define RMDR3 0x18 /* Receive Mode Register 3 */
65 #define TSCR 0x20 /* Transmit Clock Select Register */
66 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
67 #define CTR 0x28 /* Control Register */
68 #define FCTR 0x30 /* FIFO Control Register */
69 #define STR 0x40 /* Status Register */
70 #define IER 0x44 /* Interrupt Enable Register */
71 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
72 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
73 #define TFDR 0x50 /* Transmit FIFO Data Register */
74 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
75 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
76 #define RFDR 0x60 /* Receive FIFO Data Register */
77
78 /* TMDR1 and RMDR1 */
79 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
80 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
81 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
82 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
83 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
84 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
85 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
86 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
87 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
88 #define MDR1_FLD_SHIFT 2
89 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
90 /* TMDR1 */
91 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
92
93 /* TMDR2 and RMDR2 */
94 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
95 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
96 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
97
98 /* TSCR and RSCR */
99 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
100 #define SCR_BRPS(i) (((i) - 1) << 8)
101 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
102 #define SCR_BRDV_DIV_2 0x0000
103 #define SCR_BRDV_DIV_4 0x0001
104 #define SCR_BRDV_DIV_8 0x0002
105 #define SCR_BRDV_DIV_16 0x0003
106 #define SCR_BRDV_DIV_32 0x0004
107 #define SCR_BRDV_DIV_1 0x0007
108
109 /* CTR */
110 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
111 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
112 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
113 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
114 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
115 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
116 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
117 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
118 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
119 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
120 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
121 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
122 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
123 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
124 #define CTR_TXE 0x00000200 /* Transmit Enable */
125 #define CTR_RXE 0x00000100 /* Receive Enable */
126
127 /* FCTR */
128 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
129 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
130 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
131 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
132 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
133 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
134 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
135 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
136 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
137 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
138 #define FCTR_TFUA_SHIFT 20
139 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
140 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
141 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
142 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
143 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
144 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
145 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
146 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
147 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
148 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
149 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
150 #define FCTR_RFUA_SHIFT 4
151 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
152
153 /* STR */
154 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
155 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
156 #define STR_TEOF 0x00800000 /* Frame Transmission End */
157 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
158 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
159 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
160 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
161 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
162 #define STR_REOF 0x00000080 /* Frame Reception End */
163 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
164 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
165 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
166
167 /* IER */
168 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
169 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
170 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
171 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
172 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
173 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
174 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
175 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
176 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
177 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
178 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
179 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
180 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
181 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
182
183
184 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
185 {
186 switch (reg_offs) {
187 case TSCR:
188 case RSCR:
189 return ioread16(p->mapbase + reg_offs);
190 default:
191 return ioread32(p->mapbase + reg_offs);
192 }
193 }
194
195 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
196 u32 value)
197 {
198 switch (reg_offs) {
199 case TSCR:
200 case RSCR:
201 iowrite16(value, p->mapbase + reg_offs);
202 break;
203 default:
204 iowrite32(value, p->mapbase + reg_offs);
205 break;
206 }
207 }
208
209 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
210 u32 clr, u32 set)
211 {
212 u32 mask = clr | set;
213 u32 data;
214 int k;
215
216 data = sh_msiof_read(p, CTR);
217 data &= ~clr;
218 data |= set;
219 sh_msiof_write(p, CTR, data);
220
221 for (k = 100; k > 0; k--) {
222 if ((sh_msiof_read(p, CTR) & mask) == set)
223 break;
224
225 udelay(10);
226 }
227
228 return k > 0 ? 0 : -ETIMEDOUT;
229 }
230
231 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
232 {
233 struct sh_msiof_spi_priv *p = data;
234
235 /* just disable the interrupt and wake up */
236 sh_msiof_write(p, IER, 0);
237 complete(&p->done);
238
239 return IRQ_HANDLED;
240 }
241
242 static struct {
243 unsigned short div;
244 unsigned short brdv;
245 } const sh_msiof_spi_div_table[] = {
246 { 1, SCR_BRDV_DIV_1 },
247 { 2, SCR_BRDV_DIV_2 },
248 { 4, SCR_BRDV_DIV_4 },
249 { 8, SCR_BRDV_DIV_8 },
250 { 16, SCR_BRDV_DIV_16 },
251 { 32, SCR_BRDV_DIV_32 },
252 };
253
254 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
255 unsigned long parent_rate, u32 spi_hz)
256 {
257 unsigned long div = 1024;
258 u32 brps, scr;
259 size_t k;
260
261 if (!WARN_ON(!spi_hz || !parent_rate))
262 div = DIV_ROUND_UP(parent_rate, spi_hz);
263
264 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
265 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
266 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
267 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
268 continue;
269 if (brps <= 32) /* max of brdv is 32 */
270 break;
271 }
272
273 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
274
275 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
276 sh_msiof_write(p, TSCR, scr);
277 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
278 sh_msiof_write(p, RSCR, scr);
279 }
280
281 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
282 {
283 /*
284 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
285 * b'000 : 0
286 * b'001 : 100
287 * b'010 : 200
288 * b'011 (SYNCDL only) : 300
289 * b'101 : 50
290 * b'110 : 150
291 */
292 if (dtdl_or_syncdl % 100)
293 return dtdl_or_syncdl / 100 + 5;
294 else
295 return dtdl_or_syncdl / 100;
296 }
297
298 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
299 {
300 u32 val;
301
302 if (!p->info)
303 return 0;
304
305 /* check if DTDL and SYNCDL is allowed value */
306 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
307 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
308 return 0;
309 }
310
311 /* check if the sum of DTDL and SYNCDL becomes an integer value */
312 if ((p->info->dtdl + p->info->syncdl) % 100) {
313 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
314 return 0;
315 }
316
317 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
318 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
319
320 return val;
321 }
322
323 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
324 u32 cpol, u32 cpha,
325 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
326 {
327 u32 tmp;
328 int edge;
329
330 /*
331 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
332 * 0 0 10 10 1 1
333 * 0 1 10 10 0 0
334 * 1 0 11 11 0 0
335 * 1 1 11 11 1 1
336 */
337 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
338 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
339 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
340 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
341 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
342 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
343 /* These bits are reserved if RX needs TX */
344 tmp &= ~0x0000ffff;
345 }
346 sh_msiof_write(p, RMDR1, tmp);
347
348 tmp = 0;
349 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
350 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
351
352 edge = cpol ^ !cpha;
353
354 tmp |= edge << CTR_TEDG_SHIFT;
355 tmp |= edge << CTR_REDG_SHIFT;
356 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
357 sh_msiof_write(p, CTR, tmp);
358 }
359
360 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
361 const void *tx_buf, void *rx_buf,
362 u32 bits, u32 words)
363 {
364 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
365
366 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
367 sh_msiof_write(p, TMDR2, dr2);
368 else
369 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
370
371 if (rx_buf)
372 sh_msiof_write(p, RMDR2, dr2);
373 }
374
375 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
376 {
377 sh_msiof_write(p, STR,
378 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
379 }
380
381 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
382 const void *tx_buf, int words, int fs)
383 {
384 const u8 *buf_8 = tx_buf;
385 int k;
386
387 for (k = 0; k < words; k++)
388 sh_msiof_write(p, TFDR, buf_8[k] << fs);
389 }
390
391 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
392 const void *tx_buf, int words, int fs)
393 {
394 const u16 *buf_16 = tx_buf;
395 int k;
396
397 for (k = 0; k < words; k++)
398 sh_msiof_write(p, TFDR, buf_16[k] << fs);
399 }
400
401 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
402 const void *tx_buf, int words, int fs)
403 {
404 const u16 *buf_16 = tx_buf;
405 int k;
406
407 for (k = 0; k < words; k++)
408 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
409 }
410
411 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
412 const void *tx_buf, int words, int fs)
413 {
414 const u32 *buf_32 = tx_buf;
415 int k;
416
417 for (k = 0; k < words; k++)
418 sh_msiof_write(p, TFDR, buf_32[k] << fs);
419 }
420
421 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
422 const void *tx_buf, int words, int fs)
423 {
424 const u32 *buf_32 = tx_buf;
425 int k;
426
427 for (k = 0; k < words; k++)
428 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
429 }
430
431 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
432 const void *tx_buf, int words, int fs)
433 {
434 const u32 *buf_32 = tx_buf;
435 int k;
436
437 for (k = 0; k < words; k++)
438 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
439 }
440
441 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
442 const void *tx_buf, int words, int fs)
443 {
444 const u32 *buf_32 = tx_buf;
445 int k;
446
447 for (k = 0; k < words; k++)
448 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
449 }
450
451 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
452 void *rx_buf, int words, int fs)
453 {
454 u8 *buf_8 = rx_buf;
455 int k;
456
457 for (k = 0; k < words; k++)
458 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
459 }
460
461 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
462 void *rx_buf, int words, int fs)
463 {
464 u16 *buf_16 = rx_buf;
465 int k;
466
467 for (k = 0; k < words; k++)
468 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
469 }
470
471 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
472 void *rx_buf, int words, int fs)
473 {
474 u16 *buf_16 = rx_buf;
475 int k;
476
477 for (k = 0; k < words; k++)
478 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
479 }
480
481 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
482 void *rx_buf, int words, int fs)
483 {
484 u32 *buf_32 = rx_buf;
485 int k;
486
487 for (k = 0; k < words; k++)
488 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
489 }
490
491 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
492 void *rx_buf, int words, int fs)
493 {
494 u32 *buf_32 = rx_buf;
495 int k;
496
497 for (k = 0; k < words; k++)
498 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
499 }
500
501 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
502 void *rx_buf, int words, int fs)
503 {
504 u32 *buf_32 = rx_buf;
505 int k;
506
507 for (k = 0; k < words; k++)
508 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
509 }
510
511 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
512 void *rx_buf, int words, int fs)
513 {
514 u32 *buf_32 = rx_buf;
515 int k;
516
517 for (k = 0; k < words; k++)
518 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
519 }
520
521 static int sh_msiof_spi_setup(struct spi_device *spi)
522 {
523 struct device_node *np = spi->master->dev.of_node;
524 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
525
526 pm_runtime_get_sync(&p->pdev->dev);
527
528 if (!np) {
529 /*
530 * Use spi->controller_data for CS (same strategy as spi_gpio),
531 * if any. otherwise let HW control CS
532 */
533 spi->cs_gpio = (uintptr_t)spi->controller_data;
534 }
535
536 /* Configure pins before deasserting CS */
537 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
538 !!(spi->mode & SPI_CPHA),
539 !!(spi->mode & SPI_3WIRE),
540 !!(spi->mode & SPI_LSB_FIRST),
541 !!(spi->mode & SPI_CS_HIGH));
542
543 if (spi->cs_gpio >= 0)
544 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
545
546
547 pm_runtime_put(&p->pdev->dev);
548
549 return 0;
550 }
551
552 static int sh_msiof_prepare_message(struct spi_master *master,
553 struct spi_message *msg)
554 {
555 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
556 const struct spi_device *spi = msg->spi;
557
558 /* Configure pins before asserting CS */
559 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
560 !!(spi->mode & SPI_CPHA),
561 !!(spi->mode & SPI_3WIRE),
562 !!(spi->mode & SPI_LSB_FIRST),
563 !!(spi->mode & SPI_CS_HIGH));
564 return 0;
565 }
566
567 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
568 {
569 int ret;
570
571 /* setup clock and rx/tx signals */
572 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
573 if (rx_buf && !ret)
574 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
575 if (!ret)
576 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
577
578 /* start by setting frame bit */
579 if (!ret)
580 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
581
582 return ret;
583 }
584
585 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
586 {
587 int ret;
588
589 /* shut down frame, rx/tx and clock signals */
590 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
591 if (!ret)
592 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
593 if (rx_buf && !ret)
594 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
595 if (!ret)
596 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
597
598 return ret;
599 }
600
601 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
602 void (*tx_fifo)(struct sh_msiof_spi_priv *,
603 const void *, int, int),
604 void (*rx_fifo)(struct sh_msiof_spi_priv *,
605 void *, int, int),
606 const void *tx_buf, void *rx_buf,
607 int words, int bits)
608 {
609 int fifo_shift;
610 int ret;
611
612 /* limit maximum word transfer to rx/tx fifo size */
613 if (tx_buf)
614 words = min_t(int, words, p->tx_fifo_size);
615 if (rx_buf)
616 words = min_t(int, words, p->rx_fifo_size);
617
618 /* the fifo contents need shifting */
619 fifo_shift = 32 - bits;
620
621 /* default FIFO watermarks for PIO */
622 sh_msiof_write(p, FCTR, 0);
623
624 /* setup msiof transfer mode registers */
625 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
626 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
627
628 /* write tx fifo */
629 if (tx_buf)
630 tx_fifo(p, tx_buf, words, fifo_shift);
631
632 reinit_completion(&p->done);
633
634 ret = sh_msiof_spi_start(p, rx_buf);
635 if (ret) {
636 dev_err(&p->pdev->dev, "failed to start hardware\n");
637 goto stop_ier;
638 }
639
640 /* wait for tx fifo to be emptied / rx fifo to be filled */
641 if (!wait_for_completion_timeout(&p->done, HZ)) {
642 dev_err(&p->pdev->dev, "PIO timeout\n");
643 ret = -ETIMEDOUT;
644 goto stop_reset;
645 }
646
647 /* read rx fifo */
648 if (rx_buf)
649 rx_fifo(p, rx_buf, words, fifo_shift);
650
651 /* clear status bits */
652 sh_msiof_reset_str(p);
653
654 ret = sh_msiof_spi_stop(p, rx_buf);
655 if (ret) {
656 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
657 return ret;
658 }
659
660 return words;
661
662 stop_reset:
663 sh_msiof_reset_str(p);
664 sh_msiof_spi_stop(p, rx_buf);
665 stop_ier:
666 sh_msiof_write(p, IER, 0);
667 return ret;
668 }
669
670 static void sh_msiof_dma_complete(void *arg)
671 {
672 struct sh_msiof_spi_priv *p = arg;
673
674 sh_msiof_write(p, IER, 0);
675 complete(&p->done);
676 }
677
678 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
679 void *rx, unsigned int len)
680 {
681 u32 ier_bits = 0;
682 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
683 dma_cookie_t cookie;
684 int ret;
685
686 /* First prepare and submit the DMA request(s), as this may fail */
687 if (rx) {
688 ier_bits |= IER_RDREQE | IER_RDMAE;
689 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
690 p->rx_dma_addr, len, DMA_FROM_DEVICE,
691 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
692 if (!desc_rx)
693 return -EAGAIN;
694
695 desc_rx->callback = sh_msiof_dma_complete;
696 desc_rx->callback_param = p;
697 cookie = dmaengine_submit(desc_rx);
698 if (dma_submit_error(cookie))
699 return cookie;
700 }
701
702 if (tx) {
703 ier_bits |= IER_TDREQE | IER_TDMAE;
704 dma_sync_single_for_device(p->master->dma_tx->device->dev,
705 p->tx_dma_addr, len, DMA_TO_DEVICE);
706 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
707 p->tx_dma_addr, len, DMA_TO_DEVICE,
708 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
709 if (!desc_tx) {
710 ret = -EAGAIN;
711 goto no_dma_tx;
712 }
713
714 if (rx) {
715 /* No callback */
716 desc_tx->callback = NULL;
717 } else {
718 desc_tx->callback = sh_msiof_dma_complete;
719 desc_tx->callback_param = p;
720 }
721 cookie = dmaengine_submit(desc_tx);
722 if (dma_submit_error(cookie)) {
723 ret = cookie;
724 goto no_dma_tx;
725 }
726 }
727
728 /* 1 stage FIFO watermarks for DMA */
729 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
730
731 /* setup msiof transfer mode registers (32-bit words) */
732 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
733
734 sh_msiof_write(p, IER, ier_bits);
735
736 reinit_completion(&p->done);
737
738 /* Now start DMA */
739 if (rx)
740 dma_async_issue_pending(p->master->dma_rx);
741 if (tx)
742 dma_async_issue_pending(p->master->dma_tx);
743
744 ret = sh_msiof_spi_start(p, rx);
745 if (ret) {
746 dev_err(&p->pdev->dev, "failed to start hardware\n");
747 goto stop_dma;
748 }
749
750 /* wait for tx fifo to be emptied / rx fifo to be filled */
751 if (!wait_for_completion_timeout(&p->done, HZ)) {
752 dev_err(&p->pdev->dev, "DMA timeout\n");
753 ret = -ETIMEDOUT;
754 goto stop_reset;
755 }
756
757 /* clear status bits */
758 sh_msiof_reset_str(p);
759
760 ret = sh_msiof_spi_stop(p, rx);
761 if (ret) {
762 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
763 return ret;
764 }
765
766 if (rx)
767 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
768 p->rx_dma_addr, len,
769 DMA_FROM_DEVICE);
770
771 return 0;
772
773 stop_reset:
774 sh_msiof_reset_str(p);
775 sh_msiof_spi_stop(p, rx);
776 stop_dma:
777 if (tx)
778 dmaengine_terminate_all(p->master->dma_tx);
779 no_dma_tx:
780 if (rx)
781 dmaengine_terminate_all(p->master->dma_rx);
782 sh_msiof_write(p, IER, 0);
783 return ret;
784 }
785
786 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
787 {
788 /* src or dst can be unaligned, but not both */
789 if ((unsigned long)src & 3) {
790 while (words--) {
791 *dst++ = swab32(get_unaligned(src));
792 src++;
793 }
794 } else if ((unsigned long)dst & 3) {
795 while (words--) {
796 put_unaligned(swab32(*src++), dst);
797 dst++;
798 }
799 } else {
800 while (words--)
801 *dst++ = swab32(*src++);
802 }
803 }
804
805 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
806 {
807 /* src or dst can be unaligned, but not both */
808 if ((unsigned long)src & 3) {
809 while (words--) {
810 *dst++ = swahw32(get_unaligned(src));
811 src++;
812 }
813 } else if ((unsigned long)dst & 3) {
814 while (words--) {
815 put_unaligned(swahw32(*src++), dst);
816 dst++;
817 }
818 } else {
819 while (words--)
820 *dst++ = swahw32(*src++);
821 }
822 }
823
824 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
825 {
826 memcpy(dst, src, words * 4);
827 }
828
829 static int sh_msiof_transfer_one(struct spi_master *master,
830 struct spi_device *spi,
831 struct spi_transfer *t)
832 {
833 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
834 void (*copy32)(u32 *, const u32 *, unsigned int);
835 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
836 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
837 const void *tx_buf = t->tx_buf;
838 void *rx_buf = t->rx_buf;
839 unsigned int len = t->len;
840 unsigned int bits = t->bits_per_word;
841 unsigned int bytes_per_word;
842 unsigned int words;
843 int n;
844 bool swab;
845 int ret;
846
847 /* setup clocks (clock already enabled in chipselect()) */
848 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
849
850 while (master->dma_tx && len > 15) {
851 /*
852 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
853 * words, with byte resp. word swapping.
854 */
855 unsigned int l = 0;
856
857 if (tx_buf)
858 l = min(len, p->tx_fifo_size * 4);
859 if (rx_buf)
860 l = min(len, p->rx_fifo_size * 4);
861
862 if (bits <= 8) {
863 if (l & 3)
864 break;
865 copy32 = copy_bswap32;
866 } else if (bits <= 16) {
867 if (l & 3)
868 break;
869 copy32 = copy_wswap32;
870 } else {
871 copy32 = copy_plain32;
872 }
873
874 if (tx_buf)
875 copy32(p->tx_dma_page, tx_buf, l / 4);
876
877 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
878 if (ret == -EAGAIN) {
879 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
880 dev_driver_string(&p->pdev->dev),
881 dev_name(&p->pdev->dev));
882 break;
883 }
884 if (ret)
885 return ret;
886
887 if (rx_buf) {
888 copy32(rx_buf, p->rx_dma_page, l / 4);
889 rx_buf += l;
890 }
891 if (tx_buf)
892 tx_buf += l;
893
894 len -= l;
895 if (!len)
896 return 0;
897 }
898
899 if (bits <= 8 && len > 15 && !(len & 3)) {
900 bits = 32;
901 swab = true;
902 } else {
903 swab = false;
904 }
905
906 /* setup bytes per word and fifo read/write functions */
907 if (bits <= 8) {
908 bytes_per_word = 1;
909 tx_fifo = sh_msiof_spi_write_fifo_8;
910 rx_fifo = sh_msiof_spi_read_fifo_8;
911 } else if (bits <= 16) {
912 bytes_per_word = 2;
913 if ((unsigned long)tx_buf & 0x01)
914 tx_fifo = sh_msiof_spi_write_fifo_16u;
915 else
916 tx_fifo = sh_msiof_spi_write_fifo_16;
917
918 if ((unsigned long)rx_buf & 0x01)
919 rx_fifo = sh_msiof_spi_read_fifo_16u;
920 else
921 rx_fifo = sh_msiof_spi_read_fifo_16;
922 } else if (swab) {
923 bytes_per_word = 4;
924 if ((unsigned long)tx_buf & 0x03)
925 tx_fifo = sh_msiof_spi_write_fifo_s32u;
926 else
927 tx_fifo = sh_msiof_spi_write_fifo_s32;
928
929 if ((unsigned long)rx_buf & 0x03)
930 rx_fifo = sh_msiof_spi_read_fifo_s32u;
931 else
932 rx_fifo = sh_msiof_spi_read_fifo_s32;
933 } else {
934 bytes_per_word = 4;
935 if ((unsigned long)tx_buf & 0x03)
936 tx_fifo = sh_msiof_spi_write_fifo_32u;
937 else
938 tx_fifo = sh_msiof_spi_write_fifo_32;
939
940 if ((unsigned long)rx_buf & 0x03)
941 rx_fifo = sh_msiof_spi_read_fifo_32u;
942 else
943 rx_fifo = sh_msiof_spi_read_fifo_32;
944 }
945
946 /* transfer in fifo sized chunks */
947 words = len / bytes_per_word;
948
949 while (words > 0) {
950 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
951 words, bits);
952 if (n < 0)
953 return n;
954
955 if (tx_buf)
956 tx_buf += n * bytes_per_word;
957 if (rx_buf)
958 rx_buf += n * bytes_per_word;
959 words -= n;
960 }
961
962 return 0;
963 }
964
965 static const struct sh_msiof_chipdata sh_data = {
966 .tx_fifo_size = 64,
967 .rx_fifo_size = 64,
968 .master_flags = 0,
969 };
970
971 static const struct sh_msiof_chipdata r8a779x_data = {
972 .tx_fifo_size = 64,
973 .rx_fifo_size = 64,
974 .master_flags = SPI_MASTER_MUST_TX,
975 };
976
977 static const struct of_device_id sh_msiof_match[] = {
978 { .compatible = "renesas,sh-msiof", .data = &sh_data },
979 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
980 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
981 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
982 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data },
983 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data },
984 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data },
985 {},
986 };
987 MODULE_DEVICE_TABLE(of, sh_msiof_match);
988
989 #ifdef CONFIG_OF
990 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
991 {
992 struct sh_msiof_spi_info *info;
993 struct device_node *np = dev->of_node;
994 u32 num_cs = 1;
995
996 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
997 if (!info)
998 return NULL;
999
1000 /* Parse the MSIOF properties */
1001 of_property_read_u32(np, "num-cs", &num_cs);
1002 of_property_read_u32(np, "renesas,tx-fifo-size",
1003 &info->tx_fifo_override);
1004 of_property_read_u32(np, "renesas,rx-fifo-size",
1005 &info->rx_fifo_override);
1006 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1007 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1008
1009 info->num_chipselect = num_cs;
1010
1011 return info;
1012 }
1013 #else
1014 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1015 {
1016 return NULL;
1017 }
1018 #endif
1019
1020 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1021 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1022 {
1023 dma_cap_mask_t mask;
1024 struct dma_chan *chan;
1025 struct dma_slave_config cfg;
1026 int ret;
1027
1028 dma_cap_zero(mask);
1029 dma_cap_set(DMA_SLAVE, mask);
1030
1031 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1032 (void *)(unsigned long)id, dev,
1033 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1034 if (!chan) {
1035 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1036 return NULL;
1037 }
1038
1039 memset(&cfg, 0, sizeof(cfg));
1040 cfg.direction = dir;
1041 if (dir == DMA_MEM_TO_DEV) {
1042 cfg.dst_addr = port_addr;
1043 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1044 } else {
1045 cfg.src_addr = port_addr;
1046 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1047 }
1048
1049 ret = dmaengine_slave_config(chan, &cfg);
1050 if (ret) {
1051 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1052 dma_release_channel(chan);
1053 return NULL;
1054 }
1055
1056 return chan;
1057 }
1058
1059 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1060 {
1061 struct platform_device *pdev = p->pdev;
1062 struct device *dev = &pdev->dev;
1063 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1064 unsigned int dma_tx_id, dma_rx_id;
1065 const struct resource *res;
1066 struct spi_master *master;
1067 struct device *tx_dev, *rx_dev;
1068
1069 if (dev->of_node) {
1070 /* In the OF case we will get the slave IDs from the DT */
1071 dma_tx_id = 0;
1072 dma_rx_id = 0;
1073 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1074 dma_tx_id = info->dma_tx_id;
1075 dma_rx_id = info->dma_rx_id;
1076 } else {
1077 /* The driver assumes no error */
1078 return 0;
1079 }
1080
1081 /* The DMA engine uses the second register set, if present */
1082 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1083 if (!res)
1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085
1086 master = p->master;
1087 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1088 dma_tx_id,
1089 res->start + TFDR);
1090 if (!master->dma_tx)
1091 return -ENODEV;
1092
1093 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1094 dma_rx_id,
1095 res->start + RFDR);
1096 if (!master->dma_rx)
1097 goto free_tx_chan;
1098
1099 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1100 if (!p->tx_dma_page)
1101 goto free_rx_chan;
1102
1103 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1104 if (!p->rx_dma_page)
1105 goto free_tx_page;
1106
1107 tx_dev = master->dma_tx->device->dev;
1108 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1109 DMA_TO_DEVICE);
1110 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1111 goto free_rx_page;
1112
1113 rx_dev = master->dma_rx->device->dev;
1114 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1115 DMA_FROM_DEVICE);
1116 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1117 goto unmap_tx_page;
1118
1119 dev_info(dev, "DMA available");
1120 return 0;
1121
1122 unmap_tx_page:
1123 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1124 free_rx_page:
1125 free_page((unsigned long)p->rx_dma_page);
1126 free_tx_page:
1127 free_page((unsigned long)p->tx_dma_page);
1128 free_rx_chan:
1129 dma_release_channel(master->dma_rx);
1130 free_tx_chan:
1131 dma_release_channel(master->dma_tx);
1132 master->dma_tx = NULL;
1133 return -ENODEV;
1134 }
1135
1136 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1137 {
1138 struct spi_master *master = p->master;
1139 struct device *dev;
1140
1141 if (!master->dma_tx)
1142 return;
1143
1144 dev = &p->pdev->dev;
1145 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1146 PAGE_SIZE, DMA_FROM_DEVICE);
1147 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1148 PAGE_SIZE, DMA_TO_DEVICE);
1149 free_page((unsigned long)p->rx_dma_page);
1150 free_page((unsigned long)p->tx_dma_page);
1151 dma_release_channel(master->dma_rx);
1152 dma_release_channel(master->dma_tx);
1153 }
1154
1155 static int sh_msiof_spi_probe(struct platform_device *pdev)
1156 {
1157 struct resource *r;
1158 struct spi_master *master;
1159 const struct of_device_id *of_id;
1160 struct sh_msiof_spi_priv *p;
1161 int i;
1162 int ret;
1163
1164 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1165 if (master == NULL) {
1166 dev_err(&pdev->dev, "failed to allocate spi master\n");
1167 return -ENOMEM;
1168 }
1169
1170 p = spi_master_get_devdata(master);
1171
1172 platform_set_drvdata(pdev, p);
1173 p->master = master;
1174
1175 of_id = of_match_device(sh_msiof_match, &pdev->dev);
1176 if (of_id) {
1177 p->chipdata = of_id->data;
1178 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
1179 } else {
1180 p->chipdata = (const void *)pdev->id_entry->driver_data;
1181 p->info = dev_get_platdata(&pdev->dev);
1182 }
1183
1184 if (!p->info) {
1185 dev_err(&pdev->dev, "failed to obtain device info\n");
1186 ret = -ENXIO;
1187 goto err1;
1188 }
1189
1190 init_completion(&p->done);
1191
1192 p->clk = devm_clk_get(&pdev->dev, NULL);
1193 if (IS_ERR(p->clk)) {
1194 dev_err(&pdev->dev, "cannot get clock\n");
1195 ret = PTR_ERR(p->clk);
1196 goto err1;
1197 }
1198
1199 i = platform_get_irq(pdev, 0);
1200 if (i < 0) {
1201 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1202 ret = -ENOENT;
1203 goto err1;
1204 }
1205
1206 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1208 if (IS_ERR(p->mapbase)) {
1209 ret = PTR_ERR(p->mapbase);
1210 goto err1;
1211 }
1212
1213 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1214 dev_name(&pdev->dev), p);
1215 if (ret) {
1216 dev_err(&pdev->dev, "unable to request irq\n");
1217 goto err1;
1218 }
1219
1220 p->pdev = pdev;
1221 pm_runtime_enable(&pdev->dev);
1222
1223 /* Platform data may override FIFO sizes */
1224 p->tx_fifo_size = p->chipdata->tx_fifo_size;
1225 p->rx_fifo_size = p->chipdata->rx_fifo_size;
1226 if (p->info->tx_fifo_override)
1227 p->tx_fifo_size = p->info->tx_fifo_override;
1228 if (p->info->rx_fifo_override)
1229 p->rx_fifo_size = p->info->rx_fifo_override;
1230
1231 /* init master code */
1232 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1233 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1234 master->flags = p->chipdata->master_flags;
1235 master->bus_num = pdev->id;
1236 master->dev.of_node = pdev->dev.of_node;
1237 master->num_chipselect = p->info->num_chipselect;
1238 master->setup = sh_msiof_spi_setup;
1239 master->prepare_message = sh_msiof_prepare_message;
1240 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1241 master->auto_runtime_pm = true;
1242 master->transfer_one = sh_msiof_transfer_one;
1243
1244 ret = sh_msiof_request_dma(p);
1245 if (ret < 0)
1246 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1247
1248 ret = devm_spi_register_master(&pdev->dev, master);
1249 if (ret < 0) {
1250 dev_err(&pdev->dev, "spi_register_master error.\n");
1251 goto err2;
1252 }
1253
1254 return 0;
1255
1256 err2:
1257 sh_msiof_release_dma(p);
1258 pm_runtime_disable(&pdev->dev);
1259 err1:
1260 spi_master_put(master);
1261 return ret;
1262 }
1263
1264 static int sh_msiof_spi_remove(struct platform_device *pdev)
1265 {
1266 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1267
1268 sh_msiof_release_dma(p);
1269 pm_runtime_disable(&pdev->dev);
1270 return 0;
1271 }
1272
1273 static const struct platform_device_id spi_driver_ids[] = {
1274 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1275 {},
1276 };
1277 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1278
1279 #ifdef CONFIG_PM_SLEEP
1280 static int sh_msiof_spi_suspend(struct device *dev)
1281 {
1282 struct platform_device *pdev = to_platform_device(dev);
1283 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1284
1285 return spi_master_suspend(p->master);
1286 }
1287
1288 static int sh_msiof_spi_resume(struct device *dev)
1289 {
1290 struct platform_device *pdev = to_platform_device(dev);
1291 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1292
1293 return spi_master_resume(p->master);
1294 }
1295
1296 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1297 sh_msiof_spi_resume);
1298 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1299 #else
1300 #define DEV_PM_OPS NULL
1301 #endif /* CONFIG_PM_SLEEP */
1302
1303 static struct platform_driver sh_msiof_spi_drv = {
1304 .probe = sh_msiof_spi_probe,
1305 .remove = sh_msiof_spi_remove,
1306 .id_table = spi_driver_ids,
1307 .driver = {
1308 .name = "spi_sh_msiof",
1309 .pm = DEV_PM_OPS,
1310 .of_match_table = of_match_ptr(sh_msiof_match),
1311 },
1312 };
1313 module_platform_driver(sh_msiof_spi_drv);
1314
1315 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1316 MODULE_AUTHOR("Magnus Damm");
1317 MODULE_LICENSE("GPL v2");
1318 MODULE_ALIAS("platform:spi_sh_msiof");
Linux with added FPC-III support