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ceph: define 'end/complete' in readdir reply as bit flags
[linux/fpc-iii.git] / sound / soc / codecs / max98090.c
blob584aab83e4783b12232cc94000431efacbc39d95
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/clk.h>
21 #include <sound/jack.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/max98090.h>
27 #include "max98090.h"
28
29 /* Allows for sparsely populated register maps */
30 static const struct reg_default max98090_reg[] = {
31 { 0x00, 0x00 }, /* 00 Software Reset */
32 { 0x03, 0x04 }, /* 03 Interrupt Masks */
33 { 0x04, 0x00 }, /* 04 System Clock Quick */
34 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
35 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
36 { 0x07, 0x00 }, /* 07 DAC Path Quick */
37 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
38 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
39 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
40 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
41 { 0x0C, 0x00 }, /* 0C Reserved */
42 { 0x0D, 0x00 }, /* 0D Input Config */
43 { 0x0E, 0x1B }, /* 0E Line Input Level */
44 { 0x0F, 0x00 }, /* 0F Line Config */
45
46 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
47 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
48 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
49 { 0x13, 0x00 }, /* 13 Digital Mic Config */
50 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
51 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
52 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
53 { 0x17, 0x03 }, /* 17 Left ADC Level */
54 { 0x18, 0x03 }, /* 18 Right ADC Level */
55 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
56 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
57 { 0x1B, 0x00 }, /* 1B System Clock */
58 { 0x1C, 0x00 }, /* 1C Clock Mode */
59 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
60 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
61 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
62
63 { 0x20, 0x00 }, /* 20 Any Clock 4 */
64 { 0x21, 0x00 }, /* 21 Master Mode */
65 { 0x22, 0x00 }, /* 22 Interface Format */
66 { 0x23, 0x00 }, /* 23 TDM Format 1*/
67 { 0x24, 0x00 }, /* 24 TDM Format 2*/
68 { 0x25, 0x00 }, /* 25 I/O Configuration */
69 { 0x26, 0x80 }, /* 26 Filter Config */
70 { 0x27, 0x00 }, /* 27 DAI Playback Level */
71 { 0x28, 0x00 }, /* 28 EQ Playback Level */
72 { 0x29, 0x00 }, /* 29 Left HP Mixer */
73 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
74 { 0x2B, 0x00 }, /* 2B HP Control */
75 { 0x2C, 0x1A }, /* 2C Left HP Volume */
76 { 0x2D, 0x1A }, /* 2D Right HP Volume */
77 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
78 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
79
80 { 0x30, 0x00 }, /* 30 Spk Control */
81 { 0x31, 0x2C }, /* 31 Left Spk Volume */
82 { 0x32, 0x2C }, /* 32 Right Spk Volume */
83 { 0x33, 0x00 }, /* 33 ALC Timing */
84 { 0x34, 0x00 }, /* 34 ALC Compressor */
85 { 0x35, 0x00 }, /* 35 ALC Expander */
86 { 0x36, 0x00 }, /* 36 ALC Gain */
87 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
88 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
89 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
90 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
91 { 0x3B, 0x00 }, /* 3B Line OutR Control */
92 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
93 { 0x3D, 0x00 }, /* 3D Jack Detect */
94 { 0x3E, 0x00 }, /* 3E Input Enable */
95 { 0x3F, 0x00 }, /* 3F Output Enable */
96
97 { 0x40, 0x00 }, /* 40 Level Control */
98 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
99 { 0x42, 0x00 }, /* 42 Bias Control */
100 { 0x43, 0x00 }, /* 43 DAC Control */
101 { 0x44, 0x06 }, /* 44 ADC Control */
102 { 0x45, 0x00 }, /* 45 Device Shutdown */
103 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
104 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
105 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
106 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
107 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
108 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
109 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
112 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
113
114 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
115 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
116 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
117 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
118 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
119 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
120 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
121 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
122 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
123 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
124 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
125 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
128 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
129 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
130
131 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
132 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
133 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
134 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
135 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
136 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
137 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
138 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
139 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
140 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
141 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
144 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
145 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
146 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
147
148 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
149 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
150 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
151 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
152 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
153 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
154 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
155 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
156 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
157 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
160 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
161 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
162 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
163 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
164
165 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
166 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
167 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
168 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
169 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
170 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
171 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
172 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
173 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
176 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
177 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
178 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
179 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
180 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
181
182 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
183 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
184 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
185 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
186 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
187 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
188 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
189 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
192 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
193 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
194 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
195 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
196 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
197 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
198
199 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
200 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
201 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
202 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
203 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
204 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
205 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
208 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
209 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
210 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
211 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
212 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
213 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
214 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
215
216 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
217 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
218 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
219 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
220 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
221 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
224 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
225 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
226 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
227 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
228 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
229 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
230 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
231 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
232
233 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
234 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
235 { 0xC2, 0x00 }, /* C2 Sample Rate */
236 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
237 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
238 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
239 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
240 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
241 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
242 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
243 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
244 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
245 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
246 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
247 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
248 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
249
250 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
251 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
252 };
253
254 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
255 {
256 switch (reg) {
257 case M98090_REG_SOFTWARE_RESET:
258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
261 return true;
262 default:
263 return false;
264 }
265 }
266
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
268 {
269 switch (reg) {
270 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
271 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
272 case M98090_REG_REVISION_ID:
273 return true;
274 default:
275 return false;
276 }
277 }
278
279 static int max98090_reset(struct max98090_priv *max98090)
280 {
281 int ret;
282
283 /* Reset the codec by writing to this write-only reset register */
284 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
285 M98090_SWRESET_MASK);
286 if (ret < 0) {
287 dev_err(max98090->codec->dev,
288 "Failed to reset codec: %d\n", ret);
289 return ret;
290 }
291
292 msleep(20);
293 return ret;
294 }
295
296 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
297 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
298 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
299 );
300
301 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
302
303 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
304 -600, 600, 0);
305
306 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
307 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
309 );
310
311 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
313
314 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
316
317 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
318
319 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
320 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
321 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
322 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
323 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
324
325 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
326 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
327 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
328 );
329
330 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
331 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
332 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
333 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
334 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
335 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
336 );
337
338 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
339 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
340 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
341 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
342 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
343 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
344 );
345
346 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
347 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
348 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
349 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
350 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
351 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
352 );
353
354 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356 {
357 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
358 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
359 struct soc_mixer_control *mc =
360 (struct soc_mixer_control *)kcontrol->private_value;
361 unsigned int mask = (1 << fls(mc->max)) - 1;
362 unsigned int val = snd_soc_read(codec, mc->reg);
363 unsigned int *select;
364
365 switch (mc->reg) {
366 case M98090_REG_MIC1_INPUT_LEVEL:
367 select = &(max98090->pa1en);
368 break;
369 case M98090_REG_MIC2_INPUT_LEVEL:
370 select = &(max98090->pa2en);
371 break;
372 case M98090_REG_ADC_SIDETONE:
373 select = &(max98090->sidetone);
374 break;
375 default:
376 return -EINVAL;
377 }
378
379 val = (val >> mc->shift) & mask;
380
381 if (val >= 1) {
382 /* If on, return the volume */
383 val = val - 1;
384 *select = val;
385 } else {
386 /* If off, return last stored value */
387 val = *select;
388 }
389
390 ucontrol->value.integer.value[0] = val;
391 return 0;
392 }
393
394 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
395 struct snd_ctl_elem_value *ucontrol)
396 {
397 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
398 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
399 struct soc_mixer_control *mc =
400 (struct soc_mixer_control *)kcontrol->private_value;
401 unsigned int mask = (1 << fls(mc->max)) - 1;
402 unsigned int sel = ucontrol->value.integer.value[0];
403 unsigned int val = snd_soc_read(codec, mc->reg);
404 unsigned int *select;
405
406 switch (mc->reg) {
407 case M98090_REG_MIC1_INPUT_LEVEL:
408 select = &(max98090->pa1en);
409 break;
410 case M98090_REG_MIC2_INPUT_LEVEL:
411 select = &(max98090->pa2en);
412 break;
413 case M98090_REG_ADC_SIDETONE:
414 select = &(max98090->sidetone);
415 break;
416 default:
417 return -EINVAL;
418 }
419
420 val = (val >> mc->shift) & mask;
421
422 *select = sel;
423
424 /* Setting a volume is only valid if it is already On */
425 if (val >= 1) {
426 sel = sel + 1;
427 } else {
428 /* Write what was already there */
429 sel = val;
430 }
431
432 snd_soc_update_bits(codec, mc->reg,
433 mask << mc->shift,
434 sel << mc->shift);
435
436 return 0;
437 }
438
439 static const char *max98090_perf_pwr_text[] =
440 { "High Performance", "Low Power" };
441 static const char *max98090_pwr_perf_text[] =
442 { "Low Power", "High Performance" };
443
444 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
445 M98090_REG_BIAS_CONTROL,
446 M98090_VCM_MODE_SHIFT,
447 max98090_pwr_perf_text);
448
449 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
450
451 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
452 M98090_REG_ADC_CONTROL,
453 M98090_OSR128_SHIFT,
454 max98090_osr128_text);
455
456 static const char *max98090_mode_text[] = { "Voice", "Music" };
457
458 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
459 M98090_REG_FILTER_CONFIG,
460 M98090_MODE_SHIFT,
461 max98090_mode_text);
462
463 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
464 M98090_REG_FILTER_CONFIG,
465 M98090_FLT_DMIC34MODE_SHIFT,
466 max98090_mode_text);
467
468 static const char *max98090_drcatk_text[] =
469 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
470
471 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
472 M98090_REG_DRC_TIMING,
473 M98090_DRCATK_SHIFT,
474 max98090_drcatk_text);
475
476 static const char *max98090_drcrls_text[] =
477 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
478
479 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
480 M98090_REG_DRC_TIMING,
481 M98090_DRCRLS_SHIFT,
482 max98090_drcrls_text);
483
484 static const char *max98090_alccmp_text[] =
485 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
486
487 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
488 M98090_REG_DRC_COMPRESSOR,
489 M98090_DRCCMP_SHIFT,
490 max98090_alccmp_text);
491
492 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
493
494 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
495 M98090_REG_DRC_EXPANDER,
496 M98090_DRCEXP_SHIFT,
497 max98090_drcexp_text);
498
499 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
500 M98090_REG_DAC_CONTROL,
501 M98090_PERFMODE_SHIFT,
502 max98090_perf_pwr_text);
503
504 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
505 M98090_REG_DAC_CONTROL,
506 M98090_DACHP_SHIFT,
507 max98090_pwr_perf_text);
508
509 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
510 M98090_REG_ADC_CONTROL,
511 M98090_ADCHP_SHIFT,
512 max98090_pwr_perf_text);
513
514 static const struct snd_kcontrol_new max98090_snd_controls[] = {
515 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
516
517 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
519
520 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
521 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
523 max98090_put_enab_tlv, max98090_micboost_tlv),
524
525 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
526 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
528 max98090_put_enab_tlv, max98090_micboost_tlv),
529
530 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
532 max98090_mic_tlv),
533
534 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
536 max98090_mic_tlv),
537
538 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
539 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
541
542 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
543 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
545
546 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
548 max98090_line_tlv),
549
550 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
552 max98090_line_tlv),
553
554 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
556 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
558
559 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
561 max98090_avg_tlv),
562 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
564 max98090_avg_tlv),
565
566 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
568 max98090_av_tlv),
569 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
571 max98090_av_tlv),
572
573 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
574 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
576 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
577
578 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
580 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
582 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
586 SOC_ENUM("Filter Mode", max98090_mode_enum),
587 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
589 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
591 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
593 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
594 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
596 max98090_put_enab_tlv, max98090_sdg_tlv),
597 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
599 max98090_dvg_tlv),
600 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
602 max98090_dv_tlv),
603 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
610 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
612 1),
613 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
615 max98090_dv_tlv),
616
617 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
619 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
620 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
621 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
623 max98090_alcmakeup_tlv),
624 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
625 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
626 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
627 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
629 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
630 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
632
633 SOC_ENUM("DAC HP Playback Performance Mode",
634 max98090_dac_perfmode_enum),
635 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
636
637 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
638 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
640 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
641 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
643
644 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
645 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
647 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
648 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
650
651 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
652 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
654 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
655 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
657
658 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
659 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
661
662 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
663 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
665 0, max98090_spk_tlv),
666
667 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
668 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
670
671 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
672 M98090_HPLM_SHIFT, 1, 1),
673 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
674 M98090_HPRM_SHIFT, 1, 1),
675
676 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
677 M98090_SPLM_SHIFT, 1, 1),
678 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
679 M98090_SPRM_SHIFT, 1, 1),
680
681 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
682 M98090_RCVLM_SHIFT, 1, 1),
683 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
684 M98090_RCVRM_SHIFT, 1, 1),
685
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
688 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
690 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
692
693 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
694 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
696 };
697
698 static const struct snd_kcontrol_new max98091_snd_controls[] = {
699
700 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
701 M98090_DMIC34_ZEROPAD_SHIFT,
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
703
704 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
705 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
706 M98090_FLT_DMIC34HPF_SHIFT,
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
708
709 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
711 max98090_avg_tlv),
712 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
714 max98090_avg_tlv),
715
716 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
718 max98090_av_tlv),
719 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
721 max98090_av_tlv),
722
723 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
724 M98090_REG_DMIC34_BIQUAD_BASE, 15),
725 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
727
728 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
729 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
731 };
732
733 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
734 struct snd_kcontrol *kcontrol, int event)
735 {
736 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
737 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
738
739 unsigned int val = snd_soc_read(codec, w->reg);
740
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
742 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
743 else
744 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
745
746 if (val >= 1) {
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
748 max98090->pa1en = val - 1; /* Update for volatile */
749 } else {
750 max98090->pa2en = val - 1; /* Update for volatile */
751 }
752 }
753
754 switch (event) {
755 case SND_SOC_DAPM_POST_PMU:
756 /* If turning on, set to most recently selected volume */
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
758 val = max98090->pa1en + 1;
759 else
760 val = max98090->pa2en + 1;
761 break;
762 case SND_SOC_DAPM_POST_PMD:
763 /* If turning off, turn off */
764 val = 0;
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
771 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
772 val << M98090_MIC_PA1EN_SHIFT);
773 else
774 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
775 val << M98090_MIC_PA2EN_SHIFT);
776
777 return 0;
778 }
779
780 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
781 struct snd_kcontrol *kcontrol, int event)
782 {
783 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
784 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
785
786 if (event & SND_SOC_DAPM_POST_PMU)
787 max98090->shdn_pending = true;
788
789 return 0;
790
791 }
792
793 static const char *mic1_mux_text[] = { "IN12", "IN56" };
794
795 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
796 M98090_REG_INPUT_MODE,
797 M98090_EXTMIC1_SHIFT,
798 mic1_mux_text);
799
800 static const struct snd_kcontrol_new max98090_mic1_mux =
801 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
802
803 static const char *mic2_mux_text[] = { "IN34", "IN56" };
804
805 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
806 M98090_REG_INPUT_MODE,
807 M98090_EXTMIC2_SHIFT,
808 mic2_mux_text);
809
810 static const struct snd_kcontrol_new max98090_mic2_mux =
811 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
812
813 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
814
815 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
816
817 static const struct snd_kcontrol_new max98090_dmic_mux =
818 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
819
820 static const char *max98090_micpre_text[] = { "Off", "On" };
821
822 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
823 M98090_REG_MIC1_INPUT_LEVEL,
824 M98090_MIC_PA1EN_SHIFT,
825 max98090_micpre_text);
826
827 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
828 M98090_REG_MIC2_INPUT_LEVEL,
829 M98090_MIC_PA2EN_SHIFT,
830 max98090_micpre_text);
831
832 /* LINEA mixer switch */
833 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
834 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
835 M98090_IN1SEEN_SHIFT, 1, 0),
836 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
837 M98090_IN3SEEN_SHIFT, 1, 0),
838 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
839 M98090_IN5SEEN_SHIFT, 1, 0),
840 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
841 M98090_IN34DIFF_SHIFT, 1, 0),
842 };
843
844 /* LINEB mixer switch */
845 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
846 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
847 M98090_IN2SEEN_SHIFT, 1, 0),
848 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
849 M98090_IN4SEEN_SHIFT, 1, 0),
850 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
851 M98090_IN6SEEN_SHIFT, 1, 0),
852 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
853 M98090_IN56DIFF_SHIFT, 1, 0),
854 };
855
856 /* Left ADC mixer switch */
857 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
858 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
859 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
860 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
861 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
862 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
863 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
864 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
865 M98090_MIXADL_LINEA_SHIFT, 1, 0),
866 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
867 M98090_MIXADL_LINEB_SHIFT, 1, 0),
868 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
869 M98090_MIXADL_MIC1_SHIFT, 1, 0),
870 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
871 M98090_MIXADL_MIC2_SHIFT, 1, 0),
872 };
873
874 /* Right ADC mixer switch */
875 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
876 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
877 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
878 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
879 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
880 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
881 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
882 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
883 M98090_MIXADR_LINEA_SHIFT, 1, 0),
884 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
885 M98090_MIXADR_LINEB_SHIFT, 1, 0),
886 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
887 M98090_MIXADR_MIC1_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
889 M98090_MIXADR_MIC2_SHIFT, 1, 0),
890 };
891
892 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
893
894 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
895 M98090_REG_IO_CONFIGURATION,
896 M98090_LTEN_SHIFT,
897 lten_mux_text);
898
899 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
900 M98090_REG_IO_CONFIGURATION,
901 M98090_LTEN_SHIFT,
902 lten_mux_text);
903
904 static const struct snd_kcontrol_new max98090_ltenl_mux =
905 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
906
907 static const struct snd_kcontrol_new max98090_ltenr_mux =
908 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
909
910 static const char *lben_mux_text[] = { "Normal", "Loopback" };
911
912 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
913 M98090_REG_IO_CONFIGURATION,
914 M98090_LBEN_SHIFT,
915 lben_mux_text);
916
917 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
918 M98090_REG_IO_CONFIGURATION,
919 M98090_LBEN_SHIFT,
920 lben_mux_text);
921
922 static const struct snd_kcontrol_new max98090_lbenl_mux =
923 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
924
925 static const struct snd_kcontrol_new max98090_lbenr_mux =
926 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
927
928 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
929
930 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
931
932 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
933 M98090_REG_ADC_SIDETONE,
934 M98090_DSTSL_SHIFT,
935 stenl_mux_text);
936
937 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
938 M98090_REG_ADC_SIDETONE,
939 M98090_DSTSR_SHIFT,
940 stenr_mux_text);
941
942 static const struct snd_kcontrol_new max98090_stenl_mux =
943 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
944
945 static const struct snd_kcontrol_new max98090_stenr_mux =
946 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
947
948 /* Left speaker mixer switch */
949 static const struct
950 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
951 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
952 M98090_MIXSPL_DACL_SHIFT, 1, 0),
953 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
954 M98090_MIXSPL_DACR_SHIFT, 1, 0),
955 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
956 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
957 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
958 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
959 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
960 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
961 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
962 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
963 };
964
965 /* Right speaker mixer switch */
966 static const struct
967 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
968 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
969 M98090_MIXSPR_DACL_SHIFT, 1, 0),
970 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
971 M98090_MIXSPR_DACR_SHIFT, 1, 0),
972 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
973 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
974 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
975 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
976 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
977 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
978 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
979 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
980 };
981
982 /* Left headphone mixer switch */
983 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
984 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
985 M98090_MIXHPL_DACL_SHIFT, 1, 0),
986 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
987 M98090_MIXHPL_DACR_SHIFT, 1, 0),
988 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
989 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
990 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
991 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
992 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
993 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
994 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
995 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
996 };
997
998 /* Right headphone mixer switch */
999 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1000 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1001 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1002 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1003 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1004 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1005 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1006 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1007 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1009 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1011 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1012 };
1013
1014 /* Left receiver mixer switch */
1015 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1016 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1017 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1019 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1021 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1023 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1025 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1027 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1028 };
1029
1030 /* Right receiver mixer switch */
1031 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1032 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1033 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1034 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1035 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1037 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1039 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1041 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1043 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1044 };
1045
1046 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1047
1048 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1049 M98090_REG_LOUTR_MIXER,
1050 M98090_LINMOD_SHIFT,
1051 linmod_mux_text);
1052
1053 static const struct snd_kcontrol_new max98090_linmod_mux =
1054 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1055
1056 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1057
1058 /*
1059 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1060 */
1061 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1062 M98090_REG_HP_CONTROL,
1063 M98090_MIXHPLSEL_SHIFT,
1064 mixhpsel_mux_text);
1065
1066 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1067 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1068
1069 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1070 M98090_REG_HP_CONTROL,
1071 M98090_MIXHPRSEL_SHIFT,
1072 mixhpsel_mux_text);
1073
1074 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1075 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1076
1077 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1078 SND_SOC_DAPM_INPUT("MIC1"),
1079 SND_SOC_DAPM_INPUT("MIC2"),
1080 SND_SOC_DAPM_INPUT("DMICL"),
1081 SND_SOC_DAPM_INPUT("DMICR"),
1082 SND_SOC_DAPM_INPUT("IN1"),
1083 SND_SOC_DAPM_INPUT("IN2"),
1084 SND_SOC_DAPM_INPUT("IN3"),
1085 SND_SOC_DAPM_INPUT("IN4"),
1086 SND_SOC_DAPM_INPUT("IN5"),
1087 SND_SOC_DAPM_INPUT("IN6"),
1088 SND_SOC_DAPM_INPUT("IN12"),
1089 SND_SOC_DAPM_INPUT("IN34"),
1090 SND_SOC_DAPM_INPUT("IN56"),
1091
1092 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1093 M98090_MBEN_SHIFT, 0, NULL, 0),
1094 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1095 M98090_SHDNN_SHIFT, 0, NULL, 0),
1096 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1097 M98090_SDIEN_SHIFT, 0, NULL, 0),
1098 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1099 M98090_SDOEN_SHIFT, 0, NULL, 0),
1100 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1101 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1102 SND_SOC_DAPM_POST_PMU),
1103 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1104 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1105 SND_SOC_DAPM_POST_PMU),
1106 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1107 M98090_AHPF_SHIFT, 0, NULL, 0),
1108
1109 /*
1110 * Note: Sysclk and misc power supplies are taken care of by SHDN
1111 */
1112
1113 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1114 0, 0, &max98090_mic1_mux),
1115
1116 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1117 0, 0, &max98090_mic2_mux),
1118
1119 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1120
1121 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1122 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1123 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1124
1125 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1126 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1128
1129 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1130 &max98090_linea_mixer_controls[0],
1131 ARRAY_SIZE(max98090_linea_mixer_controls)),
1132
1133 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1134 &max98090_lineb_mixer_controls[0],
1135 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1136
1137 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1138 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1139 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1140 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1141
1142 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1143 &max98090_left_adc_mixer_controls[0],
1144 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1145
1146 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1147 &max98090_right_adc_mixer_controls[0],
1148 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1149
1150 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1151 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1152 SND_SOC_DAPM_POST_PMU),
1153 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1154 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1155 SND_SOC_DAPM_POST_PMU),
1156
1157 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1158 SND_SOC_NOPM, 0, 0),
1159 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1160 SND_SOC_NOPM, 0, 0),
1161
1162 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1163 0, 0, &max98090_lbenl_mux),
1164
1165 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1166 0, 0, &max98090_lbenr_mux),
1167
1168 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1169 0, 0, &max98090_ltenl_mux),
1170
1171 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1172 0, 0, &max98090_ltenr_mux),
1173
1174 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_stenl_mux),
1176
1177 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1178 0, 0, &max98090_stenr_mux),
1179
1180 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1181 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1182
1183 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1184 M98090_DALEN_SHIFT, 0),
1185 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1186 M98090_DAREN_SHIFT, 0),
1187
1188 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1189 &max98090_left_hp_mixer_controls[0],
1190 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1191
1192 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1193 &max98090_right_hp_mixer_controls[0],
1194 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1195
1196 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1197 &max98090_left_speaker_mixer_controls[0],
1198 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1199
1200 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1201 &max98090_right_speaker_mixer_controls[0],
1202 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1203
1204 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1205 &max98090_left_rcv_mixer_controls[0],
1206 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1207
1208 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1209 &max98090_right_rcv_mixer_controls[0],
1210 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1211
1212 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1213 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1214
1215 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1216 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1217
1218 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1219 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1220
1221 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1222 M98090_HPLEN_SHIFT, 0, NULL, 0),
1223 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1224 M98090_HPREN_SHIFT, 0, NULL, 0),
1225
1226 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1227 M98090_SPLEN_SHIFT, 0, NULL, 0),
1228 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1229 M98090_SPREN_SHIFT, 0, NULL, 0),
1230
1231 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1232 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1233 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1234 M98090_RCVREN_SHIFT, 0, NULL, 0),
1235
1236 SND_SOC_DAPM_OUTPUT("HPL"),
1237 SND_SOC_DAPM_OUTPUT("HPR"),
1238 SND_SOC_DAPM_OUTPUT("SPKL"),
1239 SND_SOC_DAPM_OUTPUT("SPKR"),
1240 SND_SOC_DAPM_OUTPUT("RCVL"),
1241 SND_SOC_DAPM_OUTPUT("RCVR"),
1242 };
1243
1244 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1245 SND_SOC_DAPM_INPUT("DMIC3"),
1246 SND_SOC_DAPM_INPUT("DMIC4"),
1247
1248 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1249 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1250 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1251 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1252 };
1253
1254 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1255 {"MIC1 Input", NULL, "MIC1"},
1256 {"MIC2 Input", NULL, "MIC2"},
1257
1258 {"DMICL", NULL, "DMICL_ENA"},
1259 {"DMICL", NULL, "DMICR_ENA"},
1260 {"DMICR", NULL, "DMICL_ENA"},
1261 {"DMICR", NULL, "DMICR_ENA"},
1262 {"DMICL", NULL, "AHPF"},
1263 {"DMICR", NULL, "AHPF"},
1264
1265 /* MIC1 input mux */
1266 {"MIC1 Mux", "IN12", "IN12"},
1267 {"MIC1 Mux", "IN56", "IN56"},
1268
1269 /* MIC2 input mux */
1270 {"MIC2 Mux", "IN34", "IN34"},
1271 {"MIC2 Mux", "IN56", "IN56"},
1272
1273 {"MIC1 Input", NULL, "MIC1 Mux"},
1274 {"MIC2 Input", NULL, "MIC2 Mux"},
1275
1276 /* Left ADC input mixer */
1277 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1278 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1279 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1280 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1281 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1282 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1283 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1284
1285 /* Right ADC input mixer */
1286 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1287 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1288 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1289 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1290 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1291 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1292 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1293
1294 /* Line A input mixer */
1295 {"LINEA Mixer", "IN1 Switch", "IN1"},
1296 {"LINEA Mixer", "IN3 Switch", "IN3"},
1297 {"LINEA Mixer", "IN5 Switch", "IN5"},
1298 {"LINEA Mixer", "IN34 Switch", "IN34"},
1299
1300 /* Line B input mixer */
1301 {"LINEB Mixer", "IN2 Switch", "IN2"},
1302 {"LINEB Mixer", "IN4 Switch", "IN4"},
1303 {"LINEB Mixer", "IN6 Switch", "IN6"},
1304 {"LINEB Mixer", "IN56 Switch", "IN56"},
1305
1306 {"LINEA Input", NULL, "LINEA Mixer"},
1307 {"LINEB Input", NULL, "LINEB Mixer"},
1308
1309 /* Inputs */
1310 {"ADCL", NULL, "Left ADC Mixer"},
1311 {"ADCR", NULL, "Right ADC Mixer"},
1312 {"ADCL", NULL, "SHDN"},
1313 {"ADCR", NULL, "SHDN"},
1314
1315 {"DMIC Mux", "ADC", "ADCL"},
1316 {"DMIC Mux", "ADC", "ADCR"},
1317 {"DMIC Mux", "DMIC", "DMICL"},
1318 {"DMIC Mux", "DMIC", "DMICR"},
1319
1320 {"LBENL Mux", "Normal", "DMIC Mux"},
1321 {"LBENL Mux", "Loopback", "LTENL Mux"},
1322 {"LBENR Mux", "Normal", "DMIC Mux"},
1323 {"LBENR Mux", "Loopback", "LTENR Mux"},
1324
1325 {"AIFOUTL", NULL, "LBENL Mux"},
1326 {"AIFOUTR", NULL, "LBENR Mux"},
1327 {"AIFOUTL", NULL, "SHDN"},
1328 {"AIFOUTR", NULL, "SHDN"},
1329 {"AIFOUTL", NULL, "SDOEN"},
1330 {"AIFOUTR", NULL, "SDOEN"},
1331
1332 {"LTENL Mux", "Normal", "AIFINL"},
1333 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1334 {"LTENR Mux", "Normal", "AIFINR"},
1335 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1336
1337 {"DACL", NULL, "LTENL Mux"},
1338 {"DACR", NULL, "LTENR Mux"},
1339
1340 {"STENL Mux", "Sidetone Left", "ADCL"},
1341 {"STENL Mux", "Sidetone Left", "DMICL"},
1342 {"STENR Mux", "Sidetone Right", "ADCR"},
1343 {"STENR Mux", "Sidetone Right", "DMICR"},
1344 {"DACL", NULL, "STENL Mux"},
1345 {"DACR", NULL, "STENR Mux"},
1346
1347 {"AIFINL", NULL, "SHDN"},
1348 {"AIFINR", NULL, "SHDN"},
1349 {"AIFINL", NULL, "SDIEN"},
1350 {"AIFINR", NULL, "SDIEN"},
1351 {"DACL", NULL, "SHDN"},
1352 {"DACR", NULL, "SHDN"},
1353
1354 /* Left headphone output mixer */
1355 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1356 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1357 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1358 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1359 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1360 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1361
1362 /* Right headphone output mixer */
1363 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1364 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1365 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1366 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1367 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1368 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1369
1370 /* Left speaker output mixer */
1371 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1372 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1373 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1374 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1375 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1376 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1377
1378 /* Right speaker output mixer */
1379 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1380 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1381 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1382 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1383 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1384 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1385
1386 /* Left Receiver output mixer */
1387 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1388 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1389 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1390 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1391 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1392 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1393
1394 /* Right Receiver output mixer */
1395 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1396 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1397 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1398 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1399 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1400 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1401
1402 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1403
1404 /*
1405 * Disable this for lowest power if bypassing
1406 * the DAC with an analog signal
1407 */
1408 {"HP Left Out", NULL, "DACL"},
1409 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1410
1411 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1412
1413 /*
1414 * Disable this for lowest power if bypassing
1415 * the DAC with an analog signal
1416 */
1417 {"HP Right Out", NULL, "DACR"},
1418 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1419
1420 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1421 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1422 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1423
1424 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1425 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1426 {"RCV Right Out", NULL, "LINMOD Mux"},
1427
1428 {"HPL", NULL, "HP Left Out"},
1429 {"HPR", NULL, "HP Right Out"},
1430 {"SPKL", NULL, "SPK Left Out"},
1431 {"SPKR", NULL, "SPK Right Out"},
1432 {"RCVL", NULL, "RCV Left Out"},
1433 {"RCVR", NULL, "RCV Right Out"},
1434 };
1435
1436 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1437 /* DMIC inputs */
1438 {"DMIC3", NULL, "DMIC3_ENA"},
1439 {"DMIC4", NULL, "DMIC4_ENA"},
1440 {"DMIC3", NULL, "AHPF"},
1441 {"DMIC4", NULL, "AHPF"},
1442 };
1443
1444 static int max98090_add_widgets(struct snd_soc_codec *codec)
1445 {
1446 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1447 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1448
1449 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1450 ARRAY_SIZE(max98090_snd_controls));
1451
1452 if (max98090->devtype == MAX98091) {
1453 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1454 ARRAY_SIZE(max98091_snd_controls));
1455 }
1456
1457 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1458 ARRAY_SIZE(max98090_dapm_widgets));
1459
1460 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1461 ARRAY_SIZE(max98090_dapm_routes));
1462
1463 if (max98090->devtype == MAX98091) {
1464 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1465 ARRAY_SIZE(max98091_dapm_widgets));
1466
1467 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1468 ARRAY_SIZE(max98091_dapm_routes));
1469 }
1470
1471 return 0;
1472 }
1473
1474 static const int pclk_rates[] = {
1475 12000000, 12000000, 13000000, 13000000,
1476 16000000, 16000000, 19200000, 19200000
1477 };
1478
1479 static const int lrclk_rates[] = {
1480 8000, 16000, 8000, 16000,
1481 8000, 16000, 8000, 16000
1482 };
1483
1484 static const int user_pclk_rates[] = {
1485 13000000, 13000000, 19200000, 19200000,
1486 };
1487
1488 static const int user_lrclk_rates[] = {
1489 44100, 48000, 44100, 48000,
1490 };
1491
1492 static const unsigned long long ni_value[] = {
1493 3528, 768, 441, 8
1494 };
1495
1496 static const unsigned long long mi_value[] = {
1497 8125, 1625, 1500, 25
1498 };
1499
1500 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1501 {
1502 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1503 unsigned long long ni;
1504 int i;
1505
1506 if (!max98090->sysclk) {
1507 dev_err(codec->dev, "No SYSCLK configured\n");
1508 return;
1509 }
1510
1511 if (!max98090->bclk || !max98090->lrclk) {
1512 dev_err(codec->dev, "No audio clocks configured\n");
1513 return;
1514 }
1515
1516 /* Skip configuration when operating as slave */
1517 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1518 M98090_MAS_MASK)) {
1519 return;
1520 }
1521
1522 /* Check for supported PCLK to LRCLK ratios */
1523 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1524 if ((pclk_rates[i] == max98090->sysclk) &&
1525 (lrclk_rates[i] == max98090->lrclk)) {
1526 dev_dbg(codec->dev,
1527 "Found supported PCLK to LRCLK rates 0x%x\n",
1528 i + 0x8);
1529
1530 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1531 M98090_FREQ_MASK,
1532 (i + 0x8) << M98090_FREQ_SHIFT);
1533 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1534 M98090_USE_M1_MASK, 0);
1535 return;
1536 }
1537 }
1538
1539 /* Check for user calculated MI and NI ratios */
1540 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1541 if ((user_pclk_rates[i] == max98090->sysclk) &&
1542 (user_lrclk_rates[i] == max98090->lrclk)) {
1543 dev_dbg(codec->dev,
1544 "Found user supported PCLK to LRCLK rates\n");
1545 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1546 i, ni_value[i], mi_value[i]);
1547
1548 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1549 M98090_FREQ_MASK, 0);
1550 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1551 M98090_USE_M1_MASK,
1552 1 << M98090_USE_M1_SHIFT);
1553
1554 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1555 (ni_value[i] >> 8) & 0x7F);
1556 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1557 ni_value[i] & 0xFF);
1558 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1559 (mi_value[i] >> 8) & 0x7F);
1560 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1561 mi_value[i] & 0xFF);
1562
1563 return;
1564 }
1565 }
1566
1567 /*
1568 * Calculate based on MI = 65536 (not as good as either method above)
1569 */
1570 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1571 M98090_FREQ_MASK, 0);
1572 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1573 M98090_USE_M1_MASK, 0);
1574
1575 /*
1576 * Configure NI when operating as master
1577 * Note: There is a small, but significant audio quality improvement
1578 * by calculating ni and mi.
1579 */
1580 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1581 * (unsigned long long int)max98090->lrclk;
1582 do_div(ni, (unsigned long long int)max98090->sysclk);
1583 dev_info(codec->dev, "No better method found\n");
1584 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1585 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1586 (ni >> 8) & 0x7F);
1587 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1588 }
1589
1590 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1591 unsigned int fmt)
1592 {
1593 struct snd_soc_codec *codec = codec_dai->codec;
1594 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1595 struct max98090_cdata *cdata;
1596 u8 regval;
1597
1598 max98090->dai_fmt = fmt;
1599 cdata = &max98090->dai[0];
1600
1601 if (fmt != cdata->fmt) {
1602 cdata->fmt = fmt;
1603
1604 regval = 0;
1605 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1606 case SND_SOC_DAIFMT_CBS_CFS:
1607 /* Set to slave mode PLL - MAS mode off */
1608 snd_soc_write(codec,
1609 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1610 snd_soc_write(codec,
1611 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1612 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1613 M98090_USE_M1_MASK, 0);
1614 max98090->master = false;
1615 break;
1616 case SND_SOC_DAIFMT_CBM_CFM:
1617 /* Set to master mode */
1618 if (max98090->tdm_slots == 4) {
1619 /* TDM */
1620 regval |= M98090_MAS_MASK |
1621 M98090_BSEL_64;
1622 } else if (max98090->tdm_slots == 3) {
1623 /* TDM */
1624 regval |= M98090_MAS_MASK |
1625 M98090_BSEL_48;
1626 } else {
1627 /* Few TDM slots, or No TDM */
1628 regval |= M98090_MAS_MASK |
1629 M98090_BSEL_32;
1630 }
1631 max98090->master = true;
1632 break;
1633 case SND_SOC_DAIFMT_CBS_CFM:
1634 case SND_SOC_DAIFMT_CBM_CFS:
1635 default:
1636 dev_err(codec->dev, "DAI clock mode unsupported");
1637 return -EINVAL;
1638 }
1639 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1640
1641 regval = 0;
1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1643 case SND_SOC_DAIFMT_I2S:
1644 regval |= M98090_DLY_MASK;
1645 break;
1646 case SND_SOC_DAIFMT_LEFT_J:
1647 break;
1648 case SND_SOC_DAIFMT_RIGHT_J:
1649 regval |= M98090_RJ_MASK;
1650 break;
1651 case SND_SOC_DAIFMT_DSP_A:
1652 /* Not supported mode */
1653 default:
1654 dev_err(codec->dev, "DAI format unsupported");
1655 return -EINVAL;
1656 }
1657
1658 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1659 case SND_SOC_DAIFMT_NB_NF:
1660 break;
1661 case SND_SOC_DAIFMT_NB_IF:
1662 regval |= M98090_WCI_MASK;
1663 break;
1664 case SND_SOC_DAIFMT_IB_NF:
1665 regval |= M98090_BCI_MASK;
1666 break;
1667 case SND_SOC_DAIFMT_IB_IF:
1668 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1669 break;
1670 default:
1671 dev_err(codec->dev, "DAI invert mode unsupported");
1672 return -EINVAL;
1673 }
1674
1675 /*
1676 * This accommodates an inverted logic in the MAX98090 chip
1677 * for Bit Clock Invert (BCI). The inverted logic is only
1678 * seen for the case of TDM mode. The remaining cases have
1679 * normal logic.
1680 */
1681 if (max98090->tdm_slots > 1)
1682 regval ^= M98090_BCI_MASK;
1683
1684 snd_soc_write(codec,
1685 M98090_REG_INTERFACE_FORMAT, regval);
1686 }
1687
1688 return 0;
1689 }
1690
1691 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1692 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1693 {
1694 struct snd_soc_codec *codec = codec_dai->codec;
1695 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1696 struct max98090_cdata *cdata;
1697 cdata = &max98090->dai[0];
1698
1699 if (slots < 0 || slots > 4)
1700 return -EINVAL;
1701
1702 max98090->tdm_slots = slots;
1703 max98090->tdm_width = slot_width;
1704
1705 if (max98090->tdm_slots > 1) {
1706 /* SLOTL SLOTR SLOTDLY */
1707 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1708 0 << M98090_TDM_SLOTL_SHIFT |
1709 1 << M98090_TDM_SLOTR_SHIFT |
1710 0 << M98090_TDM_SLOTDLY_SHIFT);
1711
1712 /* FSW TDM */
1713 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1714 M98090_TDM_MASK,
1715 M98090_TDM_MASK);
1716 }
1717
1718 /*
1719 * Normally advisable to set TDM first, but this permits either order
1720 */
1721 cdata->fmt = 0;
1722 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1723
1724 return 0;
1725 }
1726
1727 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1728 enum snd_soc_bias_level level)
1729 {
1730 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1731 int ret;
1732
1733 switch (level) {
1734 case SND_SOC_BIAS_ON:
1735 break;
1736
1737 case SND_SOC_BIAS_PREPARE:
1738 /*
1739 * SND_SOC_BIAS_PREPARE is called while preparing for a
1740 * transition to ON or away from ON. If current bias_level
1741 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1742 * away from ON. Disable the clock in that case, otherwise
1743 * enable it.
1744 */
1745 if (IS_ERR(max98090->mclk))
1746 break;
1747
1748 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
1749 clk_disable_unprepare(max98090->mclk);
1750 } else {
1751 ret = clk_prepare_enable(max98090->mclk);
1752 if (ret)
1753 return ret;
1754 }
1755 break;
1756
1757 case SND_SOC_BIAS_STANDBY:
1758 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1759 ret = regcache_sync(max98090->regmap);
1760 if (ret != 0) {
1761 dev_err(codec->dev,
1762 "Failed to sync cache: %d\n", ret);
1763 return ret;
1764 }
1765 }
1766 break;
1767
1768 case SND_SOC_BIAS_OFF:
1769 /* Set internal pull-up to lowest power mode */
1770 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1771 M98090_JDWK_MASK, M98090_JDWK_MASK);
1772 regcache_mark_dirty(max98090->regmap);
1773 break;
1774 }
1775 return 0;
1776 }
1777
1778 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1779
1780 static const int comp_lrclk_rates[] = {
1781 8000, 16000, 32000, 44100, 48000, 96000
1782 };
1783
1784 struct dmic_table {
1785 int pclk;
1786 struct {
1787 int freq;
1788 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1789 } settings[6]; /* One for each dmic divisor. */
1790 };
1791
1792 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1793 {
1794 .pclk = 11289600,
1795 .settings = {
1796 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1797 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1798 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1799 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1800 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1801 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1802 },
1803 },
1804 {
1805 .pclk = 12000000,
1806 .settings = {
1807 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1808 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1809 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1810 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1811 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1812 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1813 }
1814 },
1815 {
1816 .pclk = 12288000,
1817 .settings = {
1818 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1819 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1820 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1821 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1822 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1823 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1824 }
1825 },
1826 {
1827 .pclk = 13000000,
1828 .settings = {
1829 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1830 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1831 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1832 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1833 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1834 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1835 }
1836 },
1837 {
1838 .pclk = 19200000,
1839 .settings = {
1840 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1841 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1842 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1843 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1844 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1845 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1846 }
1847 },
1848 };
1849
1850 static int max98090_find_divisor(int target_freq, int pclk)
1851 {
1852 int current_diff = INT_MAX;
1853 int test_diff = INT_MAX;
1854 int divisor_index = 0;
1855 int i;
1856
1857 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1858 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1859 if (test_diff < current_diff) {
1860 current_diff = test_diff;
1861 divisor_index = i;
1862 }
1863 }
1864
1865 return divisor_index;
1866 }
1867
1868 static int max98090_find_closest_pclk(int pclk)
1869 {
1870 int m1;
1871 int m2;
1872 int i;
1873
1874 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1875 if (pclk == dmic_table[i].pclk)
1876 return i;
1877 if (pclk < dmic_table[i].pclk) {
1878 if (i == 0)
1879 return i;
1880 m1 = pclk - dmic_table[i-1].pclk;
1881 m2 = dmic_table[i].pclk - pclk;
1882 if (m1 < m2)
1883 return i - 1;
1884 else
1885 return i;
1886 }
1887 }
1888
1889 return -EINVAL;
1890 }
1891
1892 static int max98090_configure_dmic(struct max98090_priv *max98090,
1893 int target_dmic_clk, int pclk, int fs)
1894 {
1895 int micclk_index;
1896 int pclk_index;
1897 int dmic_freq;
1898 int dmic_comp;
1899 int i;
1900
1901 pclk_index = max98090_find_closest_pclk(pclk);
1902 if (pclk_index < 0)
1903 return pclk_index;
1904
1905 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1906
1907 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1908 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1909 break;
1910 }
1911
1912 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1913 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1914
1915 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1916 M98090_MICCLK_MASK,
1917 micclk_index << M98090_MICCLK_SHIFT);
1918
1919 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1920 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1921 dmic_comp << M98090_DMIC_COMP_SHIFT |
1922 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1923
1924 return 0;
1925 }
1926
1927 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1928 struct snd_pcm_hw_params *params,
1929 struct snd_soc_dai *dai)
1930 {
1931 struct snd_soc_codec *codec = dai->codec;
1932 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1933 struct max98090_cdata *cdata;
1934
1935 cdata = &max98090->dai[0];
1936 max98090->bclk = snd_soc_params_to_bclk(params);
1937 if (params_channels(params) == 1)
1938 max98090->bclk *= 2;
1939
1940 max98090->lrclk = params_rate(params);
1941
1942 switch (params_width(params)) {
1943 case 16:
1944 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1945 M98090_WS_MASK, 0);
1946 break;
1947 default:
1948 return -EINVAL;
1949 }
1950
1951 if (max98090->master)
1952 max98090_configure_bclk(codec);
1953
1954 cdata->rate = max98090->lrclk;
1955
1956 /* Update filter mode */
1957 if (max98090->lrclk < 24000)
1958 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1959 M98090_MODE_MASK, 0);
1960 else
1961 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1962 M98090_MODE_MASK, M98090_MODE_MASK);
1963
1964 /* Update sample rate mode */
1965 if (max98090->lrclk < 50000)
1966 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1967 M98090_DHF_MASK, 0);
1968 else
1969 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1970 M98090_DHF_MASK, M98090_DHF_MASK);
1971
1972 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1973 max98090->lrclk);
1974
1975 return 0;
1976 }
1977
1978 /*
1979 * PLL / Sysclk
1980 */
1981 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1982 int clk_id, unsigned int freq, int dir)
1983 {
1984 struct snd_soc_codec *codec = dai->codec;
1985 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1986
1987 /* Requested clock frequency is already setup */
1988 if (freq == max98090->sysclk)
1989 return 0;
1990
1991 if (!IS_ERR(max98090->mclk)) {
1992 freq = clk_round_rate(max98090->mclk, freq);
1993 clk_set_rate(max98090->mclk, freq);
1994 }
1995
1996 /* Setup clocks for slave mode, and using the PLL
1997 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1998 * 0x02 (when master clk is 20MHz to 40MHz)..
1999 * 0x03 (when master clk is 40MHz to 60MHz)..
2000 */
2001 if ((freq >= 10000000) && (freq <= 20000000)) {
2002 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2003 M98090_PSCLK_DIV1);
2004 max98090->pclk = freq;
2005 } else if ((freq > 20000000) && (freq <= 40000000)) {
2006 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2007 M98090_PSCLK_DIV2);
2008 max98090->pclk = freq >> 1;
2009 } else if ((freq > 40000000) && (freq <= 60000000)) {
2010 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2011 M98090_PSCLK_DIV4);
2012 max98090->pclk = freq >> 2;
2013 } else {
2014 dev_err(codec->dev, "Invalid master clock frequency\n");
2015 return -EINVAL;
2016 }
2017
2018 max98090->sysclk = freq;
2019
2020 return 0;
2021 }
2022
2023 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2024 {
2025 struct snd_soc_codec *codec = codec_dai->codec;
2026 int regval;
2027
2028 regval = mute ? M98090_DVM_MASK : 0;
2029 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
2030 M98090_DVM_MASK, regval);
2031
2032 return 0;
2033 }
2034
2035 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2036 struct snd_soc_dai *dai)
2037 {
2038 struct snd_soc_codec *codec = dai->codec;
2039 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2040
2041 switch (cmd) {
2042 case SNDRV_PCM_TRIGGER_START:
2043 case SNDRV_PCM_TRIGGER_RESUME:
2044 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2045 if (!max98090->master && dai->active == 1)
2046 queue_delayed_work(system_power_efficient_wq,
2047 &max98090->pll_det_enable_work,
2048 msecs_to_jiffies(10));
2049 break;
2050 case SNDRV_PCM_TRIGGER_STOP:
2051 case SNDRV_PCM_TRIGGER_SUSPEND:
2052 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2053 if (!max98090->master && dai->active == 1)
2054 schedule_work(&max98090->pll_det_disable_work);
2055 break;
2056 default:
2057 break;
2058 }
2059
2060 return 0;
2061 }
2062
2063 static void max98090_pll_det_enable_work(struct work_struct *work)
2064 {
2065 struct max98090_priv *max98090 =
2066 container_of(work, struct max98090_priv,
2067 pll_det_enable_work.work);
2068 struct snd_soc_codec *codec = max98090->codec;
2069 unsigned int status, mask;
2070
2071 /*
2072 * Clear status register in order to clear possibly already occurred
2073 * PLL unlock. If PLL hasn't still locked, the status will be set
2074 * again and PLL unlock interrupt will occur.
2075 * Note this will clear all status bits
2076 */
2077 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2078
2079 /*
2080 * Queue jack work in case jack state has just changed but handler
2081 * hasn't run yet
2082 */
2083 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2084 status &= mask;
2085 if (status & M98090_JDET_MASK)
2086 queue_delayed_work(system_power_efficient_wq,
2087 &max98090->jack_work,
2088 msecs_to_jiffies(100));
2089
2090 /* Enable PLL unlock interrupt */
2091 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2092 M98090_IULK_MASK,
2093 1 << M98090_IULK_SHIFT);
2094 }
2095
2096 static void max98090_pll_det_disable_work(struct work_struct *work)
2097 {
2098 struct max98090_priv *max98090 =
2099 container_of(work, struct max98090_priv, pll_det_disable_work);
2100 struct snd_soc_codec *codec = max98090->codec;
2101
2102 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2103
2104 /* Disable PLL unlock interrupt */
2105 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2106 M98090_IULK_MASK, 0);
2107 }
2108
2109 static void max98090_pll_work(struct work_struct *work)
2110 {
2111 struct max98090_priv *max98090 =
2112 container_of(work, struct max98090_priv, pll_work);
2113 struct snd_soc_codec *codec = max98090->codec;
2114
2115 if (!snd_soc_codec_is_active(codec))
2116 return;
2117
2118 dev_info(codec->dev, "PLL unlocked\n");
2119
2120 /* Toggle shutdown OFF then ON */
2121 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2122 M98090_SHDNN_MASK, 0);
2123 msleep(10);
2124 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2125 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2126
2127 /* Give PLL time to lock */
2128 msleep(10);
2129 }
2130
2131 static void max98090_jack_work(struct work_struct *work)
2132 {
2133 struct max98090_priv *max98090 = container_of(work,
2134 struct max98090_priv,
2135 jack_work.work);
2136 struct snd_soc_codec *codec = max98090->codec;
2137 int status = 0;
2138 int reg;
2139
2140 /* Read a second time */
2141 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2142
2143 /* Strong pull up allows mic detection */
2144 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2145 M98090_JDWK_MASK, 0);
2146
2147 msleep(50);
2148
2149 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2150
2151 /* Weak pull up allows only insertion detection */
2152 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2153 M98090_JDWK_MASK, M98090_JDWK_MASK);
2154 } else {
2155 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2156 }
2157
2158 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2159
2160 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2161 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2162 dev_dbg(codec->dev, "No Headset Detected\n");
2163
2164 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2165
2166 status |= 0;
2167
2168 break;
2169
2170 case 0:
2171 if (max98090->jack_state ==
2172 M98090_JACK_STATE_HEADSET) {
2173
2174 dev_dbg(codec->dev,
2175 "Headset Button Down Detected\n");
2176
2177 /*
2178 * max98090_headset_button_event(codec)
2179 * could be defined, then called here.
2180 */
2181
2182 status |= SND_JACK_HEADSET;
2183 status |= SND_JACK_BTN_0;
2184
2185 break;
2186 }
2187
2188 /* Line is reported as Headphone */
2189 /* Nokia Headset is reported as Headphone */
2190 /* Mono Headphone is reported as Headphone */
2191 dev_dbg(codec->dev, "Headphone Detected\n");
2192
2193 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2194
2195 status |= SND_JACK_HEADPHONE;
2196
2197 break;
2198
2199 case M98090_JKSNS_MASK:
2200 dev_dbg(codec->dev, "Headset Detected\n");
2201
2202 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2203
2204 status |= SND_JACK_HEADSET;
2205
2206 break;
2207
2208 default:
2209 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2210 break;
2211 }
2212
2213 snd_soc_jack_report(max98090->jack, status,
2214 SND_JACK_HEADSET | SND_JACK_BTN_0);
2215 }
2216
2217 static irqreturn_t max98090_interrupt(int irq, void *data)
2218 {
2219 struct max98090_priv *max98090 = data;
2220 struct snd_soc_codec *codec = max98090->codec;
2221 int ret;
2222 unsigned int mask;
2223 unsigned int active;
2224
2225 /* Treat interrupt before codec is initialized as spurious */
2226 if (codec == NULL)
2227 return IRQ_NONE;
2228
2229 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2230
2231 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2232
2233 if (ret != 0) {
2234 dev_err(codec->dev,
2235 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2236 ret);
2237 return IRQ_NONE;
2238 }
2239
2240 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2241
2242 if (ret != 0) {
2243 dev_err(codec->dev,
2244 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2245 ret);
2246 return IRQ_NONE;
2247 }
2248
2249 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2250 active, mask, active & mask);
2251
2252 active &= mask;
2253
2254 if (!active)
2255 return IRQ_NONE;
2256
2257 if (active & M98090_CLD_MASK)
2258 dev_err(codec->dev, "M98090_CLD_MASK\n");
2259
2260 if (active & M98090_SLD_MASK)
2261 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2262
2263 if (active & M98090_ULK_MASK) {
2264 dev_dbg(codec->dev, "M98090_ULK_MASK\n");
2265 schedule_work(&max98090->pll_work);
2266 }
2267
2268 if (active & M98090_JDET_MASK) {
2269 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2270
2271 pm_wakeup_event(codec->dev, 100);
2272
2273 queue_delayed_work(system_power_efficient_wq,
2274 &max98090->jack_work,
2275 msecs_to_jiffies(100));
2276 }
2277
2278 if (active & M98090_DRCACT_MASK)
2279 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2280
2281 if (active & M98090_DRCCLP_MASK)
2282 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2283
2284 return IRQ_HANDLED;
2285 }
2286
2287 /**
2288 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2289 *
2290 * @codec: MAX98090 codec
2291 * @jack: jack to report detection events on
2292 *
2293 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2294 * being used to bring out signals to the processor then only platform
2295 * data configuration is needed for MAX98090 and processor GPIOs should
2296 * be configured using snd_soc_jack_add_gpios() instead.
2297 *
2298 * If no jack is supplied detection will be disabled.
2299 */
2300 int max98090_mic_detect(struct snd_soc_codec *codec,
2301 struct snd_soc_jack *jack)
2302 {
2303 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2304
2305 dev_dbg(codec->dev, "max98090_mic_detect\n");
2306
2307 max98090->jack = jack;
2308 if (jack) {
2309 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2310 M98090_IJDET_MASK,
2311 1 << M98090_IJDET_SHIFT);
2312 } else {
2313 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2314 M98090_IJDET_MASK,
2315 0);
2316 }
2317
2318 /* Send an initial empty report */
2319 snd_soc_jack_report(max98090->jack, 0,
2320 SND_JACK_HEADSET | SND_JACK_BTN_0);
2321
2322 queue_delayed_work(system_power_efficient_wq,
2323 &max98090->jack_work,
2324 msecs_to_jiffies(100));
2325
2326 return 0;
2327 }
2328 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2329
2330 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2331 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2332
2333 static const struct snd_soc_dai_ops max98090_dai_ops = {
2334 .set_sysclk = max98090_dai_set_sysclk,
2335 .set_fmt = max98090_dai_set_fmt,
2336 .set_tdm_slot = max98090_set_tdm_slot,
2337 .hw_params = max98090_dai_hw_params,
2338 .digital_mute = max98090_dai_digital_mute,
2339 .trigger = max98090_dai_trigger,
2340 };
2341
2342 static struct snd_soc_dai_driver max98090_dai[] = {
2343 {
2344 .name = "HiFi",
2345 .playback = {
2346 .stream_name = "HiFi Playback",
2347 .channels_min = 2,
2348 .channels_max = 2,
2349 .rates = MAX98090_RATES,
2350 .formats = MAX98090_FORMATS,
2351 },
2352 .capture = {
2353 .stream_name = "HiFi Capture",
2354 .channels_min = 1,
2355 .channels_max = 2,
2356 .rates = MAX98090_RATES,
2357 .formats = MAX98090_FORMATS,
2358 },
2359 .ops = &max98090_dai_ops,
2360 }
2361 };
2362
2363 static int max98090_probe(struct snd_soc_codec *codec)
2364 {
2365 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2366 struct max98090_cdata *cdata;
2367 enum max98090_type devtype;
2368 int ret = 0;
2369 int err;
2370 unsigned int micbias;
2371
2372 dev_dbg(codec->dev, "max98090_probe\n");
2373
2374 max98090->mclk = devm_clk_get(codec->dev, "mclk");
2375 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2376 return -EPROBE_DEFER;
2377
2378 max98090->codec = codec;
2379
2380 /* Reset the codec, the DSP core, and disable all interrupts */
2381 max98090_reset(max98090);
2382
2383 /* Initialize private data */
2384
2385 max98090->sysclk = (unsigned)-1;
2386 max98090->pclk = (unsigned)-1;
2387 max98090->master = false;
2388
2389 cdata = &max98090->dai[0];
2390 cdata->rate = (unsigned)-1;
2391 cdata->fmt = (unsigned)-1;
2392
2393 max98090->lin_state = 0;
2394 max98090->pa1en = 0;
2395 max98090->pa2en = 0;
2396
2397 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2398 if (ret < 0) {
2399 dev_err(codec->dev, "Failed to read device revision: %d\n",
2400 ret);
2401 goto err_access;
2402 }
2403
2404 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2405 devtype = MAX98090;
2406 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2407 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2408 devtype = MAX98091;
2409 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2410 } else {
2411 devtype = MAX98090;
2412 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2413 }
2414
2415 if (max98090->devtype != devtype) {
2416 dev_warn(codec->dev, "Mismatch in DT specified CODEC type.\n");
2417 max98090->devtype = devtype;
2418 }
2419
2420 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2421
2422 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2423 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2424 max98090_pll_det_enable_work);
2425 INIT_WORK(&max98090->pll_det_disable_work,
2426 max98090_pll_det_disable_work);
2427 INIT_WORK(&max98090->pll_work, max98090_pll_work);
2428
2429 /* Enable jack detection */
2430 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2431 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2432
2433 /*
2434 * Clear any old interrupts.
2435 * An old interrupt ocurring prior to installing the ISR
2436 * can keep a new interrupt from generating a trigger.
2437 */
2438 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2439
2440 /* High Performance is default */
2441 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2442 M98090_DACHP_MASK,
2443 1 << M98090_DACHP_SHIFT);
2444 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2445 M98090_PERFMODE_MASK,
2446 0 << M98090_PERFMODE_SHIFT);
2447 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2448 M98090_ADCHP_MASK,
2449 1 << M98090_ADCHP_SHIFT);
2450
2451 /* Turn on VCM bandgap reference */
2452 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2453 M98090_VCM_MODE_MASK);
2454
2455 err = device_property_read_u32(codec->dev, "maxim,micbias", &micbias);
2456 if (err) {
2457 micbias = M98090_MBVSEL_2V8;
2458 dev_info(codec->dev, "use default 2.8v micbias\n");
2459 } else if (micbias < M98090_MBVSEL_2V2 || micbias > M98090_MBVSEL_2V8) {
2460 dev_err(codec->dev, "micbias out of range 0x%x\n", micbias);
2461 micbias = M98090_MBVSEL_2V8;
2462 }
2463
2464 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2465 M98090_MBVSEL_MASK, micbias);
2466
2467 max98090_add_widgets(codec);
2468
2469 err_access:
2470 return ret;
2471 }
2472
2473 static int max98090_remove(struct snd_soc_codec *codec)
2474 {
2475 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2476
2477 cancel_delayed_work_sync(&max98090->jack_work);
2478 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2479 cancel_work_sync(&max98090->pll_det_disable_work);
2480 cancel_work_sync(&max98090->pll_work);
2481 max98090->codec = NULL;
2482
2483 return 0;
2484 }
2485
2486 static void max98090_seq_notifier(struct snd_soc_dapm_context *dapm,
2487 enum snd_soc_dapm_type event, int subseq)
2488 {
2489 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
2490 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2491
2492 if (max98090->shdn_pending) {
2493 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2494 M98090_SHDNN_MASK, 0);
2495 msleep(40);
2496 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2497 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2498 max98090->shdn_pending = false;
2499 }
2500 }
2501
2502 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2503 .probe = max98090_probe,
2504 .remove = max98090_remove,
2505 .seq_notifier = max98090_seq_notifier,
2506 .set_bias_level = max98090_set_bias_level,
2507 };
2508
2509 static const struct regmap_config max98090_regmap = {
2510 .reg_bits = 8,
2511 .val_bits = 8,
2512
2513 .max_register = MAX98090_MAX_REGISTER,
2514 .reg_defaults = max98090_reg,
2515 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2516 .volatile_reg = max98090_volatile_register,
2517 .readable_reg = max98090_readable_register,
2518 .cache_type = REGCACHE_RBTREE,
2519 };
2520
2521 static int max98090_i2c_probe(struct i2c_client *i2c,
2522 const struct i2c_device_id *i2c_id)
2523 {
2524 struct max98090_priv *max98090;
2525 const struct acpi_device_id *acpi_id;
2526 kernel_ulong_t driver_data = 0;
2527 int ret;
2528
2529 pr_debug("max98090_i2c_probe\n");
2530
2531 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2532 GFP_KERNEL);
2533 if (max98090 == NULL)
2534 return -ENOMEM;
2535
2536 if (ACPI_HANDLE(&i2c->dev)) {
2537 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2538 &i2c->dev);
2539 if (!acpi_id) {
2540 dev_err(&i2c->dev, "No driver data\n");
2541 return -EINVAL;
2542 }
2543 driver_data = acpi_id->driver_data;
2544 } else if (i2c_id) {
2545 driver_data = i2c_id->driver_data;
2546 }
2547
2548 max98090->devtype = driver_data;
2549 i2c_set_clientdata(i2c, max98090);
2550 max98090->pdata = i2c->dev.platform_data;
2551
2552 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2553 &max98090->dmic_freq);
2554 if (ret < 0)
2555 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2556
2557 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2558 if (IS_ERR(max98090->regmap)) {
2559 ret = PTR_ERR(max98090->regmap);
2560 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2561 goto err_enable;
2562 }
2563
2564 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2565 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2566 "max98090_interrupt", max98090);
2567 if (ret < 0) {
2568 dev_err(&i2c->dev, "request_irq failed: %d\n",
2569 ret);
2570 return ret;
2571 }
2572
2573 ret = snd_soc_register_codec(&i2c->dev,
2574 &soc_codec_dev_max98090, max98090_dai,
2575 ARRAY_SIZE(max98090_dai));
2576 err_enable:
2577 return ret;
2578 }
2579
2580 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2581 {
2582 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2583
2584 /*
2585 * Enable volume smoothing, disable zero cross. This will cause
2586 * a quick 40ms ramp to mute on shutdown.
2587 */
2588 regmap_write(max98090->regmap,
2589 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2590 regmap_write(max98090->regmap,
2591 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2592 msleep(40);
2593 }
2594
2595 static int max98090_i2c_remove(struct i2c_client *client)
2596 {
2597 max98090_i2c_shutdown(client);
2598 snd_soc_unregister_codec(&client->dev);
2599 return 0;
2600 }
2601
2602 #ifdef CONFIG_PM
2603 static int max98090_runtime_resume(struct device *dev)
2604 {
2605 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2606
2607 regcache_cache_only(max98090->regmap, false);
2608
2609 max98090_reset(max98090);
2610
2611 regcache_sync(max98090->regmap);
2612
2613 return 0;
2614 }
2615
2616 static int max98090_runtime_suspend(struct device *dev)
2617 {
2618 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2619
2620 regcache_cache_only(max98090->regmap, true);
2621
2622 return 0;
2623 }
2624 #endif
2625
2626 #ifdef CONFIG_PM_SLEEP
2627 static int max98090_resume(struct device *dev)
2628 {
2629 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2630 unsigned int status;
2631
2632 regcache_mark_dirty(max98090->regmap);
2633
2634 max98090_reset(max98090);
2635
2636 /* clear IRQ status */
2637 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2638
2639 regcache_sync(max98090->regmap);
2640
2641 return 0;
2642 }
2643
2644 static int max98090_suspend(struct device *dev)
2645 {
2646 return 0;
2647 }
2648 #endif
2649
2650 static const struct dev_pm_ops max98090_pm = {
2651 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2652 max98090_runtime_resume, NULL)
2653 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2654 };
2655
2656 static const struct i2c_device_id max98090_i2c_id[] = {
2657 { "max98090", MAX98090 },
2658 { "max98091", MAX98091 },
2659 { }
2660 };
2661 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2662
2663 static const struct of_device_id max98090_of_match[] = {
2664 { .compatible = "maxim,max98090", },
2665 { .compatible = "maxim,max98091", },
2666 { }
2667 };
2668 MODULE_DEVICE_TABLE(of, max98090_of_match);
2669
2670 #ifdef CONFIG_ACPI
2671 static const struct acpi_device_id max98090_acpi_match[] = {
2672 { "193C9890", MAX98090 },
2673 { }
2674 };
2675 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2676 #endif
2677
2678 static struct i2c_driver max98090_i2c_driver = {
2679 .driver = {
2680 .name = "max98090",
2681 .pm = &max98090_pm,
2682 .of_match_table = of_match_ptr(max98090_of_match),
2683 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2684 },
2685 .probe = max98090_i2c_probe,
2686 .shutdown = max98090_i2c_shutdown,
2687 .remove = max98090_i2c_remove,
2688 .id_table = max98090_i2c_id,
2689 };
2690
2691 module_i2c_driver(max98090_i2c_driver);
2692
2693 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2694 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2695 MODULE_LICENSE("GPL");
Linux with added FPC-III support