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ftmac100: fix skb truesize underestimation
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c
bloba015c69068f68fc9d86a242fc019cd87e7beb7f3
1 /*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
16 #include <plat/cpu.h>
17 #include <plat/dma.h>
18 #include <plat/serial.h>
19 #include <plat/i2c.h>
20 #include <plat/gpio.h>
21 #include <plat/mcspi.h>
22 #include <plat/dmtimer.h>
23 #include <plat/l3_2xxx.h>
24 #include <plat/l4_2xxx.h>
25
26 #include "omap_hwmod_common_data.h"
27
28 #include "cm-regbits-24xx.h"
29 #include "prm-regbits-24xx.h"
30 #include "wd_timer.h"
31
32 /*
33 * OMAP2420 hardware module integration data
34 *
35 * ALl of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere.
39 */
40
41 static struct omap_hwmod omap2420_mpu_hwmod;
42 static struct omap_hwmod omap2420_iva_hwmod;
43 static struct omap_hwmod omap2420_l3_main_hwmod;
44 static struct omap_hwmod omap2420_l4_core_hwmod;
45 static struct omap_hwmod omap2420_dss_core_hwmod;
46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
48 static struct omap_hwmod omap2420_dss_venc_hwmod;
49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
50 static struct omap_hwmod omap2420_gpio1_hwmod;
51 static struct omap_hwmod omap2420_gpio2_hwmod;
52 static struct omap_hwmod omap2420_gpio3_hwmod;
53 static struct omap_hwmod omap2420_gpio4_hwmod;
54 static struct omap_hwmod omap2420_dma_system_hwmod;
55 static struct omap_hwmod omap2420_mcspi1_hwmod;
56 static struct omap_hwmod omap2420_mcspi2_hwmod;
57
58 /* L3 -> L4_CORE interface */
59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
60 .master = &omap2420_l3_main_hwmod,
61 .slave = &omap2420_l4_core_hwmod,
62 .user = OCP_USER_MPU | OCP_USER_SDMA,
63 };
64
65 /* MPU -> L3 interface */
66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
67 .master = &omap2420_mpu_hwmod,
68 .slave = &omap2420_l3_main_hwmod,
69 .user = OCP_USER_MPU,
70 };
71
72 /* Slave interfaces on the L3 interconnect */
73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
74 &omap2420_mpu__l3_main,
75 };
76
77 /* DSS -> l3 */
78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
79 .master = &omap2420_dss_core_hwmod,
80 .slave = &omap2420_l3_main_hwmod,
81 .fw = {
82 .omap2 = {
83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
84 .flags = OMAP_FIREWALL_L3,
85 }
86 },
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88 };
89
90 /* Master interfaces on the L3 interconnect */
91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
92 &omap2420_l3_main__l4_core,
93 };
94
95 /* L3 */
96 static struct omap_hwmod omap2420_l3_main_hwmod = {
97 .name = "l3_main",
98 .class = &l3_hwmod_class,
99 .masters = omap2420_l3_main_masters,
100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
101 .slaves = omap2420_l3_main_slaves,
102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
104 .flags = HWMOD_NO_IDLEST,
105 };
106
107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
108 static struct omap_hwmod omap2420_uart1_hwmod;
109 static struct omap_hwmod omap2420_uart2_hwmod;
110 static struct omap_hwmod omap2420_uart3_hwmod;
111 static struct omap_hwmod omap2420_i2c1_hwmod;
112 static struct omap_hwmod omap2420_i2c2_hwmod;
113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
115
116 /* l4 core -> mcspi1 interface */
117 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
118 .master = &omap2420_l4_core_hwmod,
119 .slave = &omap2420_mcspi1_hwmod,
120 .clk = "mcspi1_ick",
121 .addr = omap2_mcspi1_addr_space,
122 .user = OCP_USER_MPU | OCP_USER_SDMA,
123 };
124
125 /* l4 core -> mcspi2 interface */
126 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
127 .master = &omap2420_l4_core_hwmod,
128 .slave = &omap2420_mcspi2_hwmod,
129 .clk = "mcspi2_ick",
130 .addr = omap2_mcspi2_addr_space,
131 .user = OCP_USER_MPU | OCP_USER_SDMA,
132 };
133
134 /* L4_CORE -> L4_WKUP interface */
135 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
136 .master = &omap2420_l4_core_hwmod,
137 .slave = &omap2420_l4_wkup_hwmod,
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139 };
140
141 /* L4 CORE -> UART1 interface */
142 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
143 .master = &omap2420_l4_core_hwmod,
144 .slave = &omap2420_uart1_hwmod,
145 .clk = "uart1_ick",
146 .addr = omap2xxx_uart1_addr_space,
147 .user = OCP_USER_MPU | OCP_USER_SDMA,
148 };
149
150 /* L4 CORE -> UART2 interface */
151 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
152 .master = &omap2420_l4_core_hwmod,
153 .slave = &omap2420_uart2_hwmod,
154 .clk = "uart2_ick",
155 .addr = omap2xxx_uart2_addr_space,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157 };
158
159 /* L4 PER -> UART3 interface */
160 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
161 .master = &omap2420_l4_core_hwmod,
162 .slave = &omap2420_uart3_hwmod,
163 .clk = "uart3_ick",
164 .addr = omap2xxx_uart3_addr_space,
165 .user = OCP_USER_MPU | OCP_USER_SDMA,
166 };
167
168 /* L4 CORE -> I2C1 interface */
169 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
170 .master = &omap2420_l4_core_hwmod,
171 .slave = &omap2420_i2c1_hwmod,
172 .clk = "i2c1_ick",
173 .addr = omap2_i2c1_addr_space,
174 .user = OCP_USER_MPU | OCP_USER_SDMA,
175 };
176
177 /* L4 CORE -> I2C2 interface */
178 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
179 .master = &omap2420_l4_core_hwmod,
180 .slave = &omap2420_i2c2_hwmod,
181 .clk = "i2c2_ick",
182 .addr = omap2_i2c2_addr_space,
183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184 };
185
186 /* Slave interfaces on the L4_CORE interconnect */
187 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
188 &omap2420_l3_main__l4_core,
189 };
190
191 /* Master interfaces on the L4_CORE interconnect */
192 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
193 &omap2420_l4_core__l4_wkup,
194 &omap2_l4_core__uart1,
195 &omap2_l4_core__uart2,
196 &omap2_l4_core__uart3,
197 &omap2420_l4_core__i2c1,
198 &omap2420_l4_core__i2c2
199 };
200
201 /* L4 CORE */
202 static struct omap_hwmod omap2420_l4_core_hwmod = {
203 .name = "l4_core",
204 .class = &l4_hwmod_class,
205 .masters = omap2420_l4_core_masters,
206 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
207 .slaves = omap2420_l4_core_slaves,
208 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
209 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
210 .flags = HWMOD_NO_IDLEST,
211 };
212
213 /* Slave interfaces on the L4_WKUP interconnect */
214 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
215 &omap2420_l4_core__l4_wkup,
216 };
217
218 /* Master interfaces on the L4_WKUP interconnect */
219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
220 };
221
222 /* L4 WKUP */
223 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
224 .name = "l4_wkup",
225 .class = &l4_hwmod_class,
226 .masters = omap2420_l4_wkup_masters,
227 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
228 .slaves = omap2420_l4_wkup_slaves,
229 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
231 .flags = HWMOD_NO_IDLEST,
232 };
233
234 /* Master interfaces on the MPU device */
235 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
236 &omap2420_mpu__l3_main,
237 };
238
239 /* MPU */
240 static struct omap_hwmod omap2420_mpu_hwmod = {
241 .name = "mpu",
242 .class = &mpu_hwmod_class,
243 .main_clk = "mpu_ck",
244 .masters = omap2420_mpu_masters,
245 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
247 };
248
249 /*
250 * IVA1 interface data
251 */
252
253 /* IVA <- L3 interface */
254 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
255 .master = &omap2420_l3_main_hwmod,
256 .slave = &omap2420_iva_hwmod,
257 .clk = "iva1_ifck",
258 .user = OCP_USER_MPU | OCP_USER_SDMA,
259 };
260
261 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
262 &omap2420_l3__iva,
263 };
264
265 /*
266 * IVA2 (IVA2)
267 */
268
269 static struct omap_hwmod omap2420_iva_hwmod = {
270 .name = "iva",
271 .class = &iva_hwmod_class,
272 .masters = omap2420_iva_masters,
273 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
275 };
276
277 /* timer1 */
278 static struct omap_hwmod omap2420_timer1_hwmod;
279
280 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
281 {
282 .pa_start = 0x48028000,
283 .pa_end = 0x48028000 + SZ_1K - 1,
284 .flags = ADDR_TYPE_RT
285 },
286 { }
287 };
288
289 /* l4_wkup -> timer1 */
290 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
291 .master = &omap2420_l4_wkup_hwmod,
292 .slave = &omap2420_timer1_hwmod,
293 .clk = "gpt1_ick",
294 .addr = omap2420_timer1_addrs,
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296 };
297
298 /* timer1 slave port */
299 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
300 &omap2420_l4_wkup__timer1,
301 };
302
303 /* timer1 hwmod */
304 static struct omap_hwmod omap2420_timer1_hwmod = {
305 .name = "timer1",
306 .mpu_irqs = omap2_timer1_mpu_irqs,
307 .main_clk = "gpt1_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
312 .module_offs = WKUP_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
315 },
316 },
317 .slaves = omap2420_timer1_slaves,
318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
319 .class = &omap2xxx_timer_hwmod_class,
320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
321 };
322
323 /* timer2 */
324 static struct omap_hwmod omap2420_timer2_hwmod;
325
326 /* l4_core -> timer2 */
327 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
328 .master = &omap2420_l4_core_hwmod,
329 .slave = &omap2420_timer2_hwmod,
330 .clk = "gpt2_ick",
331 .addr = omap2xxx_timer2_addrs,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333 };
334
335 /* timer2 slave port */
336 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
337 &omap2420_l4_core__timer2,
338 };
339
340 /* timer2 hwmod */
341 static struct omap_hwmod omap2420_timer2_hwmod = {
342 .name = "timer2",
343 .mpu_irqs = omap2_timer2_mpu_irqs,
344 .main_clk = "gpt2_fck",
345 .prcm = {
346 .omap2 = {
347 .prcm_reg_id = 1,
348 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
349 .module_offs = CORE_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
352 },
353 },
354 .slaves = omap2420_timer2_slaves,
355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
356 .class = &omap2xxx_timer_hwmod_class,
357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
358 };
359
360 /* timer3 */
361 static struct omap_hwmod omap2420_timer3_hwmod;
362
363 /* l4_core -> timer3 */
364 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
365 .master = &omap2420_l4_core_hwmod,
366 .slave = &omap2420_timer3_hwmod,
367 .clk = "gpt3_ick",
368 .addr = omap2xxx_timer3_addrs,
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370 };
371
372 /* timer3 slave port */
373 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
374 &omap2420_l4_core__timer3,
375 };
376
377 /* timer3 hwmod */
378 static struct omap_hwmod omap2420_timer3_hwmod = {
379 .name = "timer3",
380 .mpu_irqs = omap2_timer3_mpu_irqs,
381 .main_clk = "gpt3_fck",
382 .prcm = {
383 .omap2 = {
384 .prcm_reg_id = 1,
385 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
386 .module_offs = CORE_MOD,
387 .idlest_reg_id = 1,
388 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
389 },
390 },
391 .slaves = omap2420_timer3_slaves,
392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
393 .class = &omap2xxx_timer_hwmod_class,
394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
395 };
396
397 /* timer4 */
398 static struct omap_hwmod omap2420_timer4_hwmod;
399
400 /* l4_core -> timer4 */
401 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
402 .master = &omap2420_l4_core_hwmod,
403 .slave = &omap2420_timer4_hwmod,
404 .clk = "gpt4_ick",
405 .addr = omap2xxx_timer4_addrs,
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407 };
408
409 /* timer4 slave port */
410 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
411 &omap2420_l4_core__timer4,
412 };
413
414 /* timer4 hwmod */
415 static struct omap_hwmod omap2420_timer4_hwmod = {
416 .name = "timer4",
417 .mpu_irqs = omap2_timer4_mpu_irqs,
418 .main_clk = "gpt4_fck",
419 .prcm = {
420 .omap2 = {
421 .prcm_reg_id = 1,
422 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
423 .module_offs = CORE_MOD,
424 .idlest_reg_id = 1,
425 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
426 },
427 },
428 .slaves = omap2420_timer4_slaves,
429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
430 .class = &omap2xxx_timer_hwmod_class,
431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
432 };
433
434 /* timer5 */
435 static struct omap_hwmod omap2420_timer5_hwmod;
436
437 /* l4_core -> timer5 */
438 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
439 .master = &omap2420_l4_core_hwmod,
440 .slave = &omap2420_timer5_hwmod,
441 .clk = "gpt5_ick",
442 .addr = omap2xxx_timer5_addrs,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
444 };
445
446 /* timer5 slave port */
447 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
448 &omap2420_l4_core__timer5,
449 };
450
451 /* timer5 hwmod */
452 static struct omap_hwmod omap2420_timer5_hwmod = {
453 .name = "timer5",
454 .mpu_irqs = omap2_timer5_mpu_irqs,
455 .main_clk = "gpt5_fck",
456 .prcm = {
457 .omap2 = {
458 .prcm_reg_id = 1,
459 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
460 .module_offs = CORE_MOD,
461 .idlest_reg_id = 1,
462 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
463 },
464 },
465 .slaves = omap2420_timer5_slaves,
466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
467 .class = &omap2xxx_timer_hwmod_class,
468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
469 };
470
471
472 /* timer6 */
473 static struct omap_hwmod omap2420_timer6_hwmod;
474
475 /* l4_core -> timer6 */
476 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
477 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer6_hwmod,
479 .clk = "gpt6_ick",
480 .addr = omap2xxx_timer6_addrs,
481 .user = OCP_USER_MPU | OCP_USER_SDMA,
482 };
483
484 /* timer6 slave port */
485 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
486 &omap2420_l4_core__timer6,
487 };
488
489 /* timer6 hwmod */
490 static struct omap_hwmod omap2420_timer6_hwmod = {
491 .name = "timer6",
492 .mpu_irqs = omap2_timer6_mpu_irqs,
493 .main_clk = "gpt6_fck",
494 .prcm = {
495 .omap2 = {
496 .prcm_reg_id = 1,
497 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
498 .module_offs = CORE_MOD,
499 .idlest_reg_id = 1,
500 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
501 },
502 },
503 .slaves = omap2420_timer6_slaves,
504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
505 .class = &omap2xxx_timer_hwmod_class,
506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
507 };
508
509 /* timer7 */
510 static struct omap_hwmod omap2420_timer7_hwmod;
511
512 /* l4_core -> timer7 */
513 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
514 .master = &omap2420_l4_core_hwmod,
515 .slave = &omap2420_timer7_hwmod,
516 .clk = "gpt7_ick",
517 .addr = omap2xxx_timer7_addrs,
518 .user = OCP_USER_MPU | OCP_USER_SDMA,
519 };
520
521 /* timer7 slave port */
522 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
523 &omap2420_l4_core__timer7,
524 };
525
526 /* timer7 hwmod */
527 static struct omap_hwmod omap2420_timer7_hwmod = {
528 .name = "timer7",
529 .mpu_irqs = omap2_timer7_mpu_irqs,
530 .main_clk = "gpt7_fck",
531 .prcm = {
532 .omap2 = {
533 .prcm_reg_id = 1,
534 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
535 .module_offs = CORE_MOD,
536 .idlest_reg_id = 1,
537 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
538 },
539 },
540 .slaves = omap2420_timer7_slaves,
541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
542 .class = &omap2xxx_timer_hwmod_class,
543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
544 };
545
546 /* timer8 */
547 static struct omap_hwmod omap2420_timer8_hwmod;
548
549 /* l4_core -> timer8 */
550 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
551 .master = &omap2420_l4_core_hwmod,
552 .slave = &omap2420_timer8_hwmod,
553 .clk = "gpt8_ick",
554 .addr = omap2xxx_timer8_addrs,
555 .user = OCP_USER_MPU | OCP_USER_SDMA,
556 };
557
558 /* timer8 slave port */
559 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
560 &omap2420_l4_core__timer8,
561 };
562
563 /* timer8 hwmod */
564 static struct omap_hwmod omap2420_timer8_hwmod = {
565 .name = "timer8",
566 .mpu_irqs = omap2_timer8_mpu_irqs,
567 .main_clk = "gpt8_fck",
568 .prcm = {
569 .omap2 = {
570 .prcm_reg_id = 1,
571 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
572 .module_offs = CORE_MOD,
573 .idlest_reg_id = 1,
574 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
575 },
576 },
577 .slaves = omap2420_timer8_slaves,
578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
579 .class = &omap2xxx_timer_hwmod_class,
580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
581 };
582
583 /* timer9 */
584 static struct omap_hwmod omap2420_timer9_hwmod;
585
586 /* l4_core -> timer9 */
587 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
588 .master = &omap2420_l4_core_hwmod,
589 .slave = &omap2420_timer9_hwmod,
590 .clk = "gpt9_ick",
591 .addr = omap2xxx_timer9_addrs,
592 .user = OCP_USER_MPU | OCP_USER_SDMA,
593 };
594
595 /* timer9 slave port */
596 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
597 &omap2420_l4_core__timer9,
598 };
599
600 /* timer9 hwmod */
601 static struct omap_hwmod omap2420_timer9_hwmod = {
602 .name = "timer9",
603 .mpu_irqs = omap2_timer9_mpu_irqs,
604 .main_clk = "gpt9_fck",
605 .prcm = {
606 .omap2 = {
607 .prcm_reg_id = 1,
608 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
609 .module_offs = CORE_MOD,
610 .idlest_reg_id = 1,
611 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
612 },
613 },
614 .slaves = omap2420_timer9_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
616 .class = &omap2xxx_timer_hwmod_class,
617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
618 };
619
620 /* timer10 */
621 static struct omap_hwmod omap2420_timer10_hwmod;
622
623 /* l4_core -> timer10 */
624 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
625 .master = &omap2420_l4_core_hwmod,
626 .slave = &omap2420_timer10_hwmod,
627 .clk = "gpt10_ick",
628 .addr = omap2_timer10_addrs,
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
630 };
631
632 /* timer10 slave port */
633 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
634 &omap2420_l4_core__timer10,
635 };
636
637 /* timer10 hwmod */
638 static struct omap_hwmod omap2420_timer10_hwmod = {
639 .name = "timer10",
640 .mpu_irqs = omap2_timer10_mpu_irqs,
641 .main_clk = "gpt10_fck",
642 .prcm = {
643 .omap2 = {
644 .prcm_reg_id = 1,
645 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
646 .module_offs = CORE_MOD,
647 .idlest_reg_id = 1,
648 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
649 },
650 },
651 .slaves = omap2420_timer10_slaves,
652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
653 .class = &omap2xxx_timer_hwmod_class,
654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
655 };
656
657 /* timer11 */
658 static struct omap_hwmod omap2420_timer11_hwmod;
659
660 /* l4_core -> timer11 */
661 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
662 .master = &omap2420_l4_core_hwmod,
663 .slave = &omap2420_timer11_hwmod,
664 .clk = "gpt11_ick",
665 .addr = omap2_timer11_addrs,
666 .user = OCP_USER_MPU | OCP_USER_SDMA,
667 };
668
669 /* timer11 slave port */
670 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
671 &omap2420_l4_core__timer11,
672 };
673
674 /* timer11 hwmod */
675 static struct omap_hwmod omap2420_timer11_hwmod = {
676 .name = "timer11",
677 .mpu_irqs = omap2_timer11_mpu_irqs,
678 .main_clk = "gpt11_fck",
679 .prcm = {
680 .omap2 = {
681 .prcm_reg_id = 1,
682 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
683 .module_offs = CORE_MOD,
684 .idlest_reg_id = 1,
685 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
686 },
687 },
688 .slaves = omap2420_timer11_slaves,
689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
690 .class = &omap2xxx_timer_hwmod_class,
691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
692 };
693
694 /* timer12 */
695 static struct omap_hwmod omap2420_timer12_hwmod;
696
697 /* l4_core -> timer12 */
698 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
699 .master = &omap2420_l4_core_hwmod,
700 .slave = &omap2420_timer12_hwmod,
701 .clk = "gpt12_ick",
702 .addr = omap2xxx_timer12_addrs,
703 .user = OCP_USER_MPU | OCP_USER_SDMA,
704 };
705
706 /* timer12 slave port */
707 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
708 &omap2420_l4_core__timer12,
709 };
710
711 /* timer12 hwmod */
712 static struct omap_hwmod omap2420_timer12_hwmod = {
713 .name = "timer12",
714 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
715 .main_clk = "gpt12_fck",
716 .prcm = {
717 .omap2 = {
718 .prcm_reg_id = 1,
719 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
720 .module_offs = CORE_MOD,
721 .idlest_reg_id = 1,
722 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
723 },
724 },
725 .slaves = omap2420_timer12_slaves,
726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
727 .class = &omap2xxx_timer_hwmod_class,
728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
729 };
730
731 /* l4_wkup -> wd_timer2 */
732 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
733 {
734 .pa_start = 0x48022000,
735 .pa_end = 0x4802207f,
736 .flags = ADDR_TYPE_RT
737 },
738 { }
739 };
740
741 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
742 .master = &omap2420_l4_wkup_hwmod,
743 .slave = &omap2420_wd_timer2_hwmod,
744 .clk = "mpu_wdt_ick",
745 .addr = omap2420_wd_timer2_addrs,
746 .user = OCP_USER_MPU | OCP_USER_SDMA,
747 };
748
749 /* wd_timer2 */
750 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
751 &omap2420_l4_wkup__wd_timer2,
752 };
753
754 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
755 .name = "wd_timer2",
756 .class = &omap2xxx_wd_timer_hwmod_class,
757 .main_clk = "mpu_wdt_fck",
758 .prcm = {
759 .omap2 = {
760 .prcm_reg_id = 1,
761 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
762 .module_offs = WKUP_MOD,
763 .idlest_reg_id = 1,
764 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
765 },
766 },
767 .slaves = omap2420_wd_timer2_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
770 };
771
772 /* UART1 */
773
774 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
775 &omap2_l4_core__uart1,
776 };
777
778 static struct omap_hwmod omap2420_uart1_hwmod = {
779 .name = "uart1",
780 .mpu_irqs = omap2_uart1_mpu_irqs,
781 .sdma_reqs = omap2_uart1_sdma_reqs,
782 .main_clk = "uart1_fck",
783 .prcm = {
784 .omap2 = {
785 .module_offs = CORE_MOD,
786 .prcm_reg_id = 1,
787 .module_bit = OMAP24XX_EN_UART1_SHIFT,
788 .idlest_reg_id = 1,
789 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
790 },
791 },
792 .slaves = omap2420_uart1_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
794 .class = &omap2_uart_class,
795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
796 };
797
798 /* UART2 */
799
800 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
801 &omap2_l4_core__uart2,
802 };
803
804 static struct omap_hwmod omap2420_uart2_hwmod = {
805 .name = "uart2",
806 .mpu_irqs = omap2_uart2_mpu_irqs,
807 .sdma_reqs = omap2_uart2_sdma_reqs,
808 .main_clk = "uart2_fck",
809 .prcm = {
810 .omap2 = {
811 .module_offs = CORE_MOD,
812 .prcm_reg_id = 1,
813 .module_bit = OMAP24XX_EN_UART2_SHIFT,
814 .idlest_reg_id = 1,
815 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
816 },
817 },
818 .slaves = omap2420_uart2_slaves,
819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
820 .class = &omap2_uart_class,
821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
822 };
823
824 /* UART3 */
825
826 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
827 &omap2_l4_core__uart3,
828 };
829
830 static struct omap_hwmod omap2420_uart3_hwmod = {
831 .name = "uart3",
832 .mpu_irqs = omap2_uart3_mpu_irqs,
833 .sdma_reqs = omap2_uart3_sdma_reqs,
834 .main_clk = "uart3_fck",
835 .prcm = {
836 .omap2 = {
837 .module_offs = CORE_MOD,
838 .prcm_reg_id = 2,
839 .module_bit = OMAP24XX_EN_UART3_SHIFT,
840 .idlest_reg_id = 2,
841 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
842 },
843 },
844 .slaves = omap2420_uart3_slaves,
845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
846 .class = &omap2_uart_class,
847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
848 };
849
850 /* dss */
851 /* dss master ports */
852 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
853 &omap2420_dss__l3,
854 };
855
856 /* l4_core -> dss */
857 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
858 .master = &omap2420_l4_core_hwmod,
859 .slave = &omap2420_dss_core_hwmod,
860 .clk = "dss_ick",
861 .addr = omap2_dss_addrs,
862 .fw = {
863 .omap2 = {
864 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
865 .flags = OMAP_FIREWALL_L4,
866 }
867 },
868 .user = OCP_USER_MPU | OCP_USER_SDMA,
869 };
870
871 /* dss slave ports */
872 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
873 &omap2420_l4_core__dss,
874 };
875
876 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
877 { .role = "tv_clk", .clk = "dss_54m_fck" },
878 { .role = "sys_clk", .clk = "dss2_fck" },
879 };
880
881 static struct omap_hwmod omap2420_dss_core_hwmod = {
882 .name = "dss_core",
883 .class = &omap2_dss_hwmod_class,
884 .main_clk = "dss1_fck", /* instead of dss_fck */
885 .sdma_reqs = omap2xxx_dss_sdma_chs,
886 .prcm = {
887 .omap2 = {
888 .prcm_reg_id = 1,
889 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
890 .module_offs = CORE_MOD,
891 .idlest_reg_id = 1,
892 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
893 },
894 },
895 .opt_clks = dss_opt_clks,
896 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
897 .slaves = omap2420_dss_slaves,
898 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
899 .masters = omap2420_dss_masters,
900 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
901 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
902 .flags = HWMOD_NO_IDLEST,
903 };
904
905 /* l4_core -> dss_dispc */
906 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
907 .master = &omap2420_l4_core_hwmod,
908 .slave = &omap2420_dss_dispc_hwmod,
909 .clk = "dss_ick",
910 .addr = omap2_dss_dispc_addrs,
911 .fw = {
912 .omap2 = {
913 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
914 .flags = OMAP_FIREWALL_L4,
915 }
916 },
917 .user = OCP_USER_MPU | OCP_USER_SDMA,
918 };
919
920 /* dss_dispc slave ports */
921 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
922 &omap2420_l4_core__dss_dispc,
923 };
924
925 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
926 .name = "dss_dispc",
927 .class = &omap2_dispc_hwmod_class,
928 .mpu_irqs = omap2_dispc_irqs,
929 .main_clk = "dss1_fck",
930 .prcm = {
931 .omap2 = {
932 .prcm_reg_id = 1,
933 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
934 .module_offs = CORE_MOD,
935 .idlest_reg_id = 1,
936 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
937 },
938 },
939 .slaves = omap2420_dss_dispc_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
941 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
942 .flags = HWMOD_NO_IDLEST,
943 };
944
945 /* l4_core -> dss_rfbi */
946 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
947 .master = &omap2420_l4_core_hwmod,
948 .slave = &omap2420_dss_rfbi_hwmod,
949 .clk = "dss_ick",
950 .addr = omap2_dss_rfbi_addrs,
951 .fw = {
952 .omap2 = {
953 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
954 .flags = OMAP_FIREWALL_L4,
955 }
956 },
957 .user = OCP_USER_MPU | OCP_USER_SDMA,
958 };
959
960 /* dss_rfbi slave ports */
961 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
962 &omap2420_l4_core__dss_rfbi,
963 };
964
965 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
966 .name = "dss_rfbi",
967 .class = &omap2_rfbi_hwmod_class,
968 .main_clk = "dss1_fck",
969 .prcm = {
970 .omap2 = {
971 .prcm_reg_id = 1,
972 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
973 .module_offs = CORE_MOD,
974 },
975 },
976 .slaves = omap2420_dss_rfbi_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
978 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
979 .flags = HWMOD_NO_IDLEST,
980 };
981
982 /* l4_core -> dss_venc */
983 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
984 .master = &omap2420_l4_core_hwmod,
985 .slave = &omap2420_dss_venc_hwmod,
986 .clk = "dss_54m_fck",
987 .addr = omap2_dss_venc_addrs,
988 .fw = {
989 .omap2 = {
990 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
991 .flags = OMAP_FIREWALL_L4,
992 }
993 },
994 .flags = OCPIF_SWSUP_IDLE,
995 .user = OCP_USER_MPU | OCP_USER_SDMA,
996 };
997
998 /* dss_venc slave ports */
999 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1000 &omap2420_l4_core__dss_venc,
1001 };
1002
1003 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1004 .name = "dss_venc",
1005 .class = &omap2_venc_hwmod_class,
1006 .main_clk = "dss1_fck",
1007 .prcm = {
1008 .omap2 = {
1009 .prcm_reg_id = 1,
1010 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1011 .module_offs = CORE_MOD,
1012 },
1013 },
1014 .slaves = omap2420_dss_venc_slaves,
1015 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
1016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1017 .flags = HWMOD_NO_IDLEST,
1018 };
1019
1020 /* I2C common */
1021 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1022 .rev_offs = 0x00,
1023 .sysc_offs = 0x20,
1024 .syss_offs = 0x10,
1025 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1026 .sysc_fields = &omap_hwmod_sysc_type1,
1027 };
1028
1029 static struct omap_hwmod_class i2c_class = {
1030 .name = "i2c",
1031 .sysc = &i2c_sysc,
1032 .rev = OMAP_I2C_IP_VERSION_1,
1033 .reset = &omap_i2c_reset,
1034 };
1035
1036 static struct omap_i2c_dev_attr i2c_dev_attr = {
1037 .flags = OMAP_I2C_FLAG_NO_FIFO |
1038 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1039 OMAP_I2C_FLAG_16BIT_DATA_REG |
1040 OMAP_I2C_FLAG_BUS_SHIFT_2,
1041 };
1042
1043 /* I2C1 */
1044
1045 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1046 &omap2420_l4_core__i2c1,
1047 };
1048
1049 static struct omap_hwmod omap2420_i2c1_hwmod = {
1050 .name = "i2c1",
1051 .mpu_irqs = omap2_i2c1_mpu_irqs,
1052 .sdma_reqs = omap2_i2c1_sdma_reqs,
1053 .main_clk = "i2c1_fck",
1054 .prcm = {
1055 .omap2 = {
1056 .module_offs = CORE_MOD,
1057 .prcm_reg_id = 1,
1058 .module_bit = OMAP2420_EN_I2C1_SHIFT,
1059 .idlest_reg_id = 1,
1060 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1061 },
1062 },
1063 .slaves = omap2420_i2c1_slaves,
1064 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
1065 .class = &i2c_class,
1066 .dev_attr = &i2c_dev_attr,
1067 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1068 .flags = HWMOD_16BIT_REG,
1069 };
1070
1071 /* I2C2 */
1072
1073 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1074 &omap2420_l4_core__i2c2,
1075 };
1076
1077 static struct omap_hwmod omap2420_i2c2_hwmod = {
1078 .name = "i2c2",
1079 .mpu_irqs = omap2_i2c2_mpu_irqs,
1080 .sdma_reqs = omap2_i2c2_sdma_reqs,
1081 .main_clk = "i2c2_fck",
1082 .prcm = {
1083 .omap2 = {
1084 .module_offs = CORE_MOD,
1085 .prcm_reg_id = 1,
1086 .module_bit = OMAP2420_EN_I2C2_SHIFT,
1087 .idlest_reg_id = 1,
1088 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1089 },
1090 },
1091 .slaves = omap2420_i2c2_slaves,
1092 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
1093 .class = &i2c_class,
1094 .dev_attr = &i2c_dev_attr,
1095 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1096 .flags = HWMOD_16BIT_REG,
1097 };
1098
1099 /* l4_wkup -> gpio1 */
1100 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1101 {
1102 .pa_start = 0x48018000,
1103 .pa_end = 0x480181ff,
1104 .flags = ADDR_TYPE_RT
1105 },
1106 { }
1107 };
1108
1109 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1110 .master = &omap2420_l4_wkup_hwmod,
1111 .slave = &omap2420_gpio1_hwmod,
1112 .clk = "gpios_ick",
1113 .addr = omap2420_gpio1_addr_space,
1114 .user = OCP_USER_MPU | OCP_USER_SDMA,
1115 };
1116
1117 /* l4_wkup -> gpio2 */
1118 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1119 {
1120 .pa_start = 0x4801a000,
1121 .pa_end = 0x4801a1ff,
1122 .flags = ADDR_TYPE_RT
1123 },
1124 { }
1125 };
1126
1127 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1128 .master = &omap2420_l4_wkup_hwmod,
1129 .slave = &omap2420_gpio2_hwmod,
1130 .clk = "gpios_ick",
1131 .addr = omap2420_gpio2_addr_space,
1132 .user = OCP_USER_MPU | OCP_USER_SDMA,
1133 };
1134
1135 /* l4_wkup -> gpio3 */
1136 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1137 {
1138 .pa_start = 0x4801c000,
1139 .pa_end = 0x4801c1ff,
1140 .flags = ADDR_TYPE_RT
1141 },
1142 { }
1143 };
1144
1145 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1146 .master = &omap2420_l4_wkup_hwmod,
1147 .slave = &omap2420_gpio3_hwmod,
1148 .clk = "gpios_ick",
1149 .addr = omap2420_gpio3_addr_space,
1150 .user = OCP_USER_MPU | OCP_USER_SDMA,
1151 };
1152
1153 /* l4_wkup -> gpio4 */
1154 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1155 {
1156 .pa_start = 0x4801e000,
1157 .pa_end = 0x4801e1ff,
1158 .flags = ADDR_TYPE_RT
1159 },
1160 { }
1161 };
1162
1163 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1164 .master = &omap2420_l4_wkup_hwmod,
1165 .slave = &omap2420_gpio4_hwmod,
1166 .clk = "gpios_ick",
1167 .addr = omap2420_gpio4_addr_space,
1168 .user = OCP_USER_MPU | OCP_USER_SDMA,
1169 };
1170
1171 /* gpio dev_attr */
1172 static struct omap_gpio_dev_attr gpio_dev_attr = {
1173 .bank_width = 32,
1174 .dbck_flag = false,
1175 };
1176
1177 /* gpio1 */
1178 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1179 &omap2420_l4_wkup__gpio1,
1180 };
1181
1182 static struct omap_hwmod omap2420_gpio1_hwmod = {
1183 .name = "gpio1",
1184 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1185 .mpu_irqs = omap2_gpio1_irqs,
1186 .main_clk = "gpios_fck",
1187 .prcm = {
1188 .omap2 = {
1189 .prcm_reg_id = 1,
1190 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1191 .module_offs = WKUP_MOD,
1192 .idlest_reg_id = 1,
1193 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1194 },
1195 },
1196 .slaves = omap2420_gpio1_slaves,
1197 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1198 .class = &omap2xxx_gpio_hwmod_class,
1199 .dev_attr = &gpio_dev_attr,
1200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1201 };
1202
1203 /* gpio2 */
1204 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1205 &omap2420_l4_wkup__gpio2,
1206 };
1207
1208 static struct omap_hwmod omap2420_gpio2_hwmod = {
1209 .name = "gpio2",
1210 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1211 .mpu_irqs = omap2_gpio2_irqs,
1212 .main_clk = "gpios_fck",
1213 .prcm = {
1214 .omap2 = {
1215 .prcm_reg_id = 1,
1216 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1217 .module_offs = WKUP_MOD,
1218 .idlest_reg_id = 1,
1219 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1220 },
1221 },
1222 .slaves = omap2420_gpio2_slaves,
1223 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1224 .class = &omap2xxx_gpio_hwmod_class,
1225 .dev_attr = &gpio_dev_attr,
1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1227 };
1228
1229 /* gpio3 */
1230 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1231 &omap2420_l4_wkup__gpio3,
1232 };
1233
1234 static struct omap_hwmod omap2420_gpio3_hwmod = {
1235 .name = "gpio3",
1236 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1237 .mpu_irqs = omap2_gpio3_irqs,
1238 .main_clk = "gpios_fck",
1239 .prcm = {
1240 .omap2 = {
1241 .prcm_reg_id = 1,
1242 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1243 .module_offs = WKUP_MOD,
1244 .idlest_reg_id = 1,
1245 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1246 },
1247 },
1248 .slaves = omap2420_gpio3_slaves,
1249 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1250 .class = &omap2xxx_gpio_hwmod_class,
1251 .dev_attr = &gpio_dev_attr,
1252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1253 };
1254
1255 /* gpio4 */
1256 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1257 &omap2420_l4_wkup__gpio4,
1258 };
1259
1260 static struct omap_hwmod omap2420_gpio4_hwmod = {
1261 .name = "gpio4",
1262 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1263 .mpu_irqs = omap2_gpio4_irqs,
1264 .main_clk = "gpios_fck",
1265 .prcm = {
1266 .omap2 = {
1267 .prcm_reg_id = 1,
1268 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1269 .module_offs = WKUP_MOD,
1270 .idlest_reg_id = 1,
1271 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1272 },
1273 },
1274 .slaves = omap2420_gpio4_slaves,
1275 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1276 .class = &omap2xxx_gpio_hwmod_class,
1277 .dev_attr = &gpio_dev_attr,
1278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1279 };
1280
1281 /* dma attributes */
1282 static struct omap_dma_dev_attr dma_dev_attr = {
1283 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1284 IS_CSSA_32 | IS_CDSA_32,
1285 .lch_count = 32,
1286 };
1287
1288 /* dma_system -> L3 */
1289 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1290 .master = &omap2420_dma_system_hwmod,
1291 .slave = &omap2420_l3_main_hwmod,
1292 .clk = "core_l3_ck",
1293 .user = OCP_USER_MPU | OCP_USER_SDMA,
1294 };
1295
1296 /* dma_system master ports */
1297 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1298 &omap2420_dma_system__l3,
1299 };
1300
1301 /* l4_core -> dma_system */
1302 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1303 .master = &omap2420_l4_core_hwmod,
1304 .slave = &omap2420_dma_system_hwmod,
1305 .clk = "sdma_ick",
1306 .addr = omap2_dma_system_addrs,
1307 .user = OCP_USER_MPU | OCP_USER_SDMA,
1308 };
1309
1310 /* dma_system slave ports */
1311 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1312 &omap2420_l4_core__dma_system,
1313 };
1314
1315 static struct omap_hwmod omap2420_dma_system_hwmod = {
1316 .name = "dma",
1317 .class = &omap2xxx_dma_hwmod_class,
1318 .mpu_irqs = omap2_dma_system_irqs,
1319 .main_clk = "core_l3_ck",
1320 .slaves = omap2420_dma_system_slaves,
1321 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
1322 .masters = omap2420_dma_system_masters,
1323 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
1324 .dev_attr = &dma_dev_attr,
1325 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1326 .flags = HWMOD_NO_IDLEST,
1327 };
1328
1329 /* mailbox */
1330 static struct omap_hwmod omap2420_mailbox_hwmod;
1331 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1332 { .name = "dsp", .irq = 26 },
1333 { .name = "iva", .irq = 34 },
1334 { .irq = -1 }
1335 };
1336
1337 /* l4_core -> mailbox */
1338 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1339 .master = &omap2420_l4_core_hwmod,
1340 .slave = &omap2420_mailbox_hwmod,
1341 .addr = omap2_mailbox_addrs,
1342 .user = OCP_USER_MPU | OCP_USER_SDMA,
1343 };
1344
1345 /* mailbox slave ports */
1346 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1347 &omap2420_l4_core__mailbox,
1348 };
1349
1350 static struct omap_hwmod omap2420_mailbox_hwmod = {
1351 .name = "mailbox",
1352 .class = &omap2xxx_mailbox_hwmod_class,
1353 .mpu_irqs = omap2420_mailbox_irqs,
1354 .main_clk = "mailboxes_ick",
1355 .prcm = {
1356 .omap2 = {
1357 .prcm_reg_id = 1,
1358 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1359 .module_offs = CORE_MOD,
1360 .idlest_reg_id = 1,
1361 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1362 },
1363 },
1364 .slaves = omap2420_mailbox_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1367 };
1368
1369 /* mcspi1 */
1370 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1371 &omap2420_l4_core__mcspi1,
1372 };
1373
1374 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1375 .num_chipselect = 4,
1376 };
1377
1378 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1379 .name = "mcspi1_hwmod",
1380 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1381 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1382 .main_clk = "mcspi1_fck",
1383 .prcm = {
1384 .omap2 = {
1385 .module_offs = CORE_MOD,
1386 .prcm_reg_id = 1,
1387 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1388 .idlest_reg_id = 1,
1389 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1390 },
1391 },
1392 .slaves = omap2420_mcspi1_slaves,
1393 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1394 .class = &omap2xxx_mcspi_class,
1395 .dev_attr = &omap_mcspi1_dev_attr,
1396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1397 };
1398
1399 /* mcspi2 */
1400 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1401 &omap2420_l4_core__mcspi2,
1402 };
1403
1404 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1405 .num_chipselect = 2,
1406 };
1407
1408 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1409 .name = "mcspi2_hwmod",
1410 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1411 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1412 .main_clk = "mcspi2_fck",
1413 .prcm = {
1414 .omap2 = {
1415 .module_offs = CORE_MOD,
1416 .prcm_reg_id = 1,
1417 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1418 .idlest_reg_id = 1,
1419 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1420 },
1421 },
1422 .slaves = omap2420_mcspi2_slaves,
1423 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1424 .class = &omap2xxx_mcspi_class,
1425 .dev_attr = &omap_mcspi2_dev_attr,
1426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1427 };
1428
1429 /*
1430 * 'mcbsp' class
1431 * multi channel buffered serial port controller
1432 */
1433
1434 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1435 .name = "mcbsp",
1436 };
1437
1438 /* mcbsp1 */
1439 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1440 { .name = "tx", .irq = 59 },
1441 { .name = "rx", .irq = 60 },
1442 { .irq = -1 }
1443 };
1444
1445 /* l4_core -> mcbsp1 */
1446 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1447 .master = &omap2420_l4_core_hwmod,
1448 .slave = &omap2420_mcbsp1_hwmod,
1449 .clk = "mcbsp1_ick",
1450 .addr = omap2_mcbsp1_addrs,
1451 .user = OCP_USER_MPU | OCP_USER_SDMA,
1452 };
1453
1454 /* mcbsp1 slave ports */
1455 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1456 &omap2420_l4_core__mcbsp1,
1457 };
1458
1459 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1460 .name = "mcbsp1",
1461 .class = &omap2420_mcbsp_hwmod_class,
1462 .mpu_irqs = omap2420_mcbsp1_irqs,
1463 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1464 .main_clk = "mcbsp1_fck",
1465 .prcm = {
1466 .omap2 = {
1467 .prcm_reg_id = 1,
1468 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1469 .module_offs = CORE_MOD,
1470 .idlest_reg_id = 1,
1471 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1472 },
1473 },
1474 .slaves = omap2420_mcbsp1_slaves,
1475 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1476 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1477 };
1478
1479 /* mcbsp2 */
1480 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1481 { .name = "tx", .irq = 62 },
1482 { .name = "rx", .irq = 63 },
1483 { .irq = -1 }
1484 };
1485
1486 /* l4_core -> mcbsp2 */
1487 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1488 .master = &omap2420_l4_core_hwmod,
1489 .slave = &omap2420_mcbsp2_hwmod,
1490 .clk = "mcbsp2_ick",
1491 .addr = omap2xxx_mcbsp2_addrs,
1492 .user = OCP_USER_MPU | OCP_USER_SDMA,
1493 };
1494
1495 /* mcbsp2 slave ports */
1496 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1497 &omap2420_l4_core__mcbsp2,
1498 };
1499
1500 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1501 .name = "mcbsp2",
1502 .class = &omap2420_mcbsp_hwmod_class,
1503 .mpu_irqs = omap2420_mcbsp2_irqs,
1504 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1505 .main_clk = "mcbsp2_fck",
1506 .prcm = {
1507 .omap2 = {
1508 .prcm_reg_id = 1,
1509 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1510 .module_offs = CORE_MOD,
1511 .idlest_reg_id = 1,
1512 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1513 },
1514 },
1515 .slaves = omap2420_mcbsp2_slaves,
1516 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1518 };
1519
1520 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1521 &omap2420_l3_main_hwmod,
1522 &omap2420_l4_core_hwmod,
1523 &omap2420_l4_wkup_hwmod,
1524 &omap2420_mpu_hwmod,
1525 &omap2420_iva_hwmod,
1526
1527 &omap2420_timer1_hwmod,
1528 &omap2420_timer2_hwmod,
1529 &omap2420_timer3_hwmod,
1530 &omap2420_timer4_hwmod,
1531 &omap2420_timer5_hwmod,
1532 &omap2420_timer6_hwmod,
1533 &omap2420_timer7_hwmod,
1534 &omap2420_timer8_hwmod,
1535 &omap2420_timer9_hwmod,
1536 &omap2420_timer10_hwmod,
1537 &omap2420_timer11_hwmod,
1538 &omap2420_timer12_hwmod,
1539
1540 &omap2420_wd_timer2_hwmod,
1541 &omap2420_uart1_hwmod,
1542 &omap2420_uart2_hwmod,
1543 &omap2420_uart3_hwmod,
1544 /* dss class */
1545 &omap2420_dss_core_hwmod,
1546 &omap2420_dss_dispc_hwmod,
1547 &omap2420_dss_rfbi_hwmod,
1548 &omap2420_dss_venc_hwmod,
1549 /* i2c class */
1550 &omap2420_i2c1_hwmod,
1551 &omap2420_i2c2_hwmod,
1552
1553 /* gpio class */
1554 &omap2420_gpio1_hwmod,
1555 &omap2420_gpio2_hwmod,
1556 &omap2420_gpio3_hwmod,
1557 &omap2420_gpio4_hwmod,
1558
1559 /* dma_system class*/
1560 &omap2420_dma_system_hwmod,
1561
1562 /* mailbox class */
1563 &omap2420_mailbox_hwmod,
1564
1565 /* mcbsp class */
1566 &omap2420_mcbsp1_hwmod,
1567 &omap2420_mcbsp2_hwmod,
1568
1569 /* mcspi class */
1570 &omap2420_mcspi1_hwmod,
1571 &omap2420_mcspi2_hwmod,
1572 NULL,
1573 };
1574
1575 int __init omap2420_hwmod_init(void)
1576 {
1577 return omap_hwmod_register(omap2420_hwmods);
1578 }
Linux with added FPC-III support