drivers/spi/spi-mpc52xx-psc.c

   1 /*
   2  * MPC52xx PSC in SPI mode driver.
   3  *
   4  * Maintainer: Dragos Carp
   5  *
   6  * Copyright (C) 2006 TOPTICA Photonics AG.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/workqueue.h>
  21 #include <linux/completion.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/slab.h>
  27
  28 #include <asm/mpc52xx.h>
  29 #include <asm/mpc52xx_psc.h>
  30
  31 #define MCLK 20000000 /* PSC port MClk in hz */
  32
  33 struct mpc52xx_psc_spi {
  34         /* fsl_spi_platform data */
  35         void (*cs_control)(struct spi_device *spi, bool on);
  36         u32 sysclk;
  37
  38         /* driver internal data */
  39         struct mpc52xx_psc __iomem *psc;
  40         struct mpc52xx_psc_fifo __iomem *fifo;
  41         unsigned int irq;
  42         u8 bits_per_word;
  43         u8 busy;
  44
  45         struct work_struct work;
  46
  47         struct list_head queue;
  48         spinlock_t lock;
  49
  50         struct completion done;
  51 };
  52
  53 /* controller state */
  54 struct mpc52xx_psc_spi_cs {
  55         int bits_per_word;
  56         int speed_hz;
  57 };
  58
  59 /* set clock freq, clock ramp, bits per work
  60  * if t is NULL then reset the values to the default values
  61  */
  62 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  63                 struct spi_transfer *t)
  64 {
  65         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  66
  67         cs->speed_hz = (t && t->speed_hz)
  68                         ? t->speed_hz : spi->max_speed_hz;
  69         cs->bits_per_word = (t && t->bits_per_word)
  70                         ? t->bits_per_word : spi->bits_per_word;
  71         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  72         return 0;
  73 }
  74
  75 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  76 {
  77         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  78         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  79         struct mpc52xx_psc __iomem *psc = mps->psc;
  80         u32 sicr;
  81         u16 ccr;
  82
  83         sicr = in_be32(&psc->sicr);
  84
  85         /* Set clock phase and polarity */
  86         if (spi->mode & SPI_CPHA)
  87                 sicr |= 0x00001000;
  88         else
  89                 sicr &= ~0x00001000;
  90         if (spi->mode & SPI_CPOL)
  91                 sicr |= 0x00002000;
  92         else
  93                 sicr &= ~0x00002000;
  94
  95         if (spi->mode & SPI_LSB_FIRST)
  96                 sicr |= 0x10000000;
  97         else
  98                 sicr &= ~0x10000000;
  99         out_be32(&psc->sicr, sicr);
 100
 101         /* Set clock frequency and bits per word
 102          * Because psc->ccr is defined as 16bit register instead of 32bit
 103          * just set the lower byte of BitClkDiv
 104          */
 105         ccr = in_be16((u16 __iomem *)&psc->ccr);
 106         ccr &= 0xFF00;
 107         if (cs->speed_hz)
 108                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
 109         else /* by default SPI Clk 1MHz */
 110                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
 111         out_be16((u16 __iomem *)&psc->ccr, ccr);
 112         mps->bits_per_word = cs->bits_per_word;
 113
 114         if (mps->cs_control)
 115                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 116 }
 117
 118 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
 119 {
 120         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 121
 122         if (mps->cs_control)
 123                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 124 }
 125
 126 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
 127 /* wake up when 80% fifo full */
 128 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
 129
 130 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
 131                                                 struct spi_transfer *t)
 132 {
 133         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 134         struct mpc52xx_psc __iomem *psc = mps->psc;
 135         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 136         unsigned rb = 0;        /* number of bytes receieved */
 137         unsigned sb = 0;        /* number of bytes sent */
 138         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
 139         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
 140         unsigned rfalarm;
 141         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
 142         unsigned recv_at_once;
 143         int last_block = 0;
 144
 145         if (!t->tx_buf && !t->rx_buf && t->len)
 146                 return -EINVAL;
 147
 148         /* enable transmiter/receiver */
 149         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 150         while (rb < t->len) {
 151                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
 152                         rfalarm = MPC52xx_PSC_RFALARM;
 153                         last_block = 0;
 154                 } else {
 155                         send_at_once = t->len - sb;
 156                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
 157                         last_block = 1;
 158                 }
 159
 160                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
 161                 for (; send_at_once; sb++, send_at_once--) {
 162                         /* set EOF flag before the last word is sent */
 163                         if (send_at_once == 1 && last_block)
 164                                 out_8(&psc->ircr2, 0x01);
 165
 166                         if (tx_buf)
 167                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
 168                         else
 169                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
 170                 }
 171
 172
 173                 /* enable interrupts and wait for wake up
 174                  * if just one byte is expected the Rx FIFO genererates no
 175                  * FFULL interrupt, so activate the RxRDY interrupt
 176                  */
 177                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 178                 if (t->len - rb == 1) {
 179                         out_8(&psc->mode, 0);
 180                 } else {
 181                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 182                         out_be16(&fifo->rfalarm, rfalarm);
 183                 }
 184                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
 185                 wait_for_completion(&mps->done);
 186                 recv_at_once = in_be16(&fifo->rfnum);
 187                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
 188
 189                 send_at_once = recv_at_once;
 190                 if (rx_buf) {
 191                         for (; recv_at_once; rb++, recv_at_once--)
 192                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
 193                 } else {
 194                         for (; recv_at_once; rb++, recv_at_once--)
 195                                 in_8(&psc->mpc52xx_psc_buffer_8);
 196                 }
 197         }
 198         /* disable transmiter/receiver */
 199         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 200
 201         return 0;
 202 }
 203
 204 static void mpc52xx_psc_spi_work(struct work_struct *work)
 205 {
 206         struct mpc52xx_psc_spi *mps =
 207                 container_of(work, struct mpc52xx_psc_spi, work);
 208
 209         spin_lock_irq(&mps->lock);
 210         mps->busy = 1;
 211         while (!list_empty(&mps->queue)) {
 212                 struct spi_message *m;
 213                 struct spi_device *spi;
 214                 struct spi_transfer *t = NULL;
 215                 unsigned cs_change;
 216                 int status;
 217
 218                 m = container_of(mps->queue.next, struct spi_message, queue);
 219                 list_del_init(&m->queue);
 220                 spin_unlock_irq(&mps->lock);
 221
 222                 spi = m->spi;
 223                 cs_change = 1;
 224                 status = 0;
 225                 list_for_each_entry (t, &m->transfers, transfer_list) {
 226                         if (t->bits_per_word || t->speed_hz) {
 227                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
 228                                 if (status < 0)
 229                                         break;
 230                         }
 231
 232                         if (cs_change)
 233                                 mpc52xx_psc_spi_activate_cs(spi);
 234                         cs_change = t->cs_change;
 235
 236                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
 237                         if (status)
 238                                 break;
 239                         m->actual_length += t->len;
 240
 241                         if (t->delay_usecs)
 242                                 udelay(t->delay_usecs);
 243
 244                         if (cs_change)
 245                                 mpc52xx_psc_spi_deactivate_cs(spi);
 246                 }
 247
 248                 m->status = status;
 249                 if (m->complete)
 250                         m->complete(m->context);
 251
 252                 if (status || !cs_change)
 253                         mpc52xx_psc_spi_deactivate_cs(spi);
 254
 255                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
 256
 257                 spin_lock_irq(&mps->lock);
 258         }
 259         mps->busy = 0;
 260         spin_unlock_irq(&mps->lock);
 261 }
 262
 263 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
 264 {
 265         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 266         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
 267         unsigned long flags;
 268
 269         if (spi->bits_per_word%8)
 270                 return -EINVAL;
 271
 272         if (!cs) {
 273                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 274                 if (!cs)
 275                         return -ENOMEM;
 276                 spi->controller_state = cs;
 277         }
 278
 279         cs->bits_per_word = spi->bits_per_word;
 280         cs->speed_hz = spi->max_speed_hz;
 281
 282         spin_lock_irqsave(&mps->lock, flags);
 283         if (!mps->busy)
 284                 mpc52xx_psc_spi_deactivate_cs(spi);
 285         spin_unlock_irqrestore(&mps->lock, flags);
 286
 287         return 0;
 288 }
 289
 290 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
 291                 struct spi_message *m)
 292 {
 293         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 294         unsigned long flags;
 295
 296         m->actual_length = 0;
 297         m->status = -EINPROGRESS;
 298
 299         spin_lock_irqsave(&mps->lock, flags);
 300         list_add_tail(&m->queue, &mps->queue);
 301         schedule_work(&mps->work);
 302         spin_unlock_irqrestore(&mps->lock, flags);
 303
 304         return 0;
 305 }
 306
 307 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
 308 {
 309         kfree(spi->controller_state);
 310 }
 311
 312 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 313 {
 314         struct mpc52xx_psc __iomem *psc = mps->psc;
 315         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 316         u32 mclken_div;
 317         int ret;
 318
 319         /* default sysclk is 512MHz */
 320         mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
 321         ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
 322         if (ret)
 323                 return ret;
 324
 325         /* Reset the PSC into a known state */
 326         out_8(&psc->command, MPC52xx_PSC_RST_RX);
 327         out_8(&psc->command, MPC52xx_PSC_RST_TX);
 328         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 329
 330         /* Disable interrupts, interrupts are based on alarm level */
 331         out_be16(&psc->mpc52xx_psc_imr, 0);
 332         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 333         out_8(&fifo->rfcntl, 0);
 334         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 335
 336         /* Configure 8bit codec mode as a SPI master and use EOF flags */
 337         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 338         out_be32(&psc->sicr, 0x0180C800);
 339         out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
 340
 341         /* Set 2ms DTL delay */
 342         out_8(&psc->ctur, 0x00);
 343         out_8(&psc->ctlr, 0x84);
 344
 345         mps->bits_per_word = 8;
 346
 347         return 0;
 348 }
 349
 350 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
 351 {
 352         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
 353         struct mpc52xx_psc __iomem *psc = mps->psc;
 354
 355         /* disable interrupt and wake up the work queue */
 356         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
 357                 out_be16(&psc->mpc52xx_psc_imr, 0);
 358                 complete(&mps->done);
 359                 return IRQ_HANDLED;
 360         }
 361         return IRQ_NONE;
 362 }
 363
 364 /* bus_num is used only for the case dev->platform_data == NULL */
 365 static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 366                                 u32 size, unsigned int irq, s16 bus_num)
 367 {
 368         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 369         struct mpc52xx_psc_spi *mps;
 370         struct spi_master *master;
 371         int ret;
 372
 373         master = spi_alloc_master(dev, sizeof *mps);
 374         if (master == NULL)
 375                 return -ENOMEM;
 376
 377         dev_set_drvdata(dev, master);
 378         mps = spi_master_get_devdata(master);
 379
 380         /* the spi->mode bits understood by this driver: */
 381         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 382
 383         mps->irq = irq;
 384         if (pdata == NULL) {
 385                 dev_warn(dev,
 386                          "probe called without platform data, no cs_control function will be called\n");
 387                 mps->cs_control = NULL;
 388                 mps->sysclk = 0;
 389                 master->bus_num = bus_num;
 390                 master->num_chipselect = 255;
 391         } else {
 392                 mps->cs_control = pdata->cs_control;
 393                 mps->sysclk = pdata->sysclk;
 394                 master->bus_num = pdata->bus_num;
 395                 master->num_chipselect = pdata->max_chipselect;
 396         }
 397         master->setup = mpc52xx_psc_spi_setup;
 398         master->transfer = mpc52xx_psc_spi_transfer;
 399         master->cleanup = mpc52xx_psc_spi_cleanup;
 400         master->dev.of_node = dev->of_node;
 401
 402         mps->psc = ioremap(regaddr, size);
 403         if (!mps->psc) {
 404                 dev_err(dev, "could not ioremap I/O port range\n");
 405                 ret = -EFAULT;
 406                 goto free_master;
 407         }
 408         /* On the 5200, fifo regs are immediately ajacent to the psc regs */
 409         mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
 410
 411         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
 412                                 mps);
 413         if (ret)
 414                 goto free_master;
 415
 416         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
 417         if (ret < 0) {
 418                 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
 419                 goto free_irq;
 420         }
 421
 422         spin_lock_init(&mps->lock);
 423         init_completion(&mps->done);
 424         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
 425         INIT_LIST_HEAD(&mps->queue);
 426
 427         ret = spi_register_master(master);
 428         if (ret < 0)
 429                 goto free_irq;
 430
 431         return ret;
 432
 433 free_irq:
 434         free_irq(mps->irq, mps);
 435 free_master:
 436         if (mps->psc)
 437                 iounmap(mps->psc);
 438         spi_master_put(master);
 439
 440         return ret;
 441 }
 442
 443 static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
 444 {
 445         const u32 *regaddr_p;
 446         u64 regaddr64, size64;
 447         s16 id = -1;
 448
 449         regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
 450         if (!regaddr_p) {
 451                 dev_err(&op->dev, "Invalid PSC address\n");
 452                 return -EINVAL;
 453         }
 454         regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
 455
 456         /* get PSC id (1..6, used by port_config) */
 457         if (op->dev.platform_data == NULL) {
 458                 const u32 *psc_nump;
 459
 460                 psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
 461                 if (!psc_nump || *psc_nump > 5) {
 462                         dev_err(&op->dev, "Invalid cell-index property\n");
 463                         return -EINVAL;
 464                 }
 465                 id = *psc_nump + 1;
 466         }
 467
 468         return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
 469                                 irq_of_parse_and_map(op->dev.of_node, 0), id);
 470 }
 471
 472 static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
 473 {
 474         struct spi_master *master = spi_master_get(platform_get_drvdata(op));
 475         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
 476
 477         flush_work(&mps->work);
 478         spi_unregister_master(master);
 479         free_irq(mps->irq, mps);
 480         if (mps->psc)
 481                 iounmap(mps->psc);
 482         spi_master_put(master);
 483
 484         return 0;
 485 }
 486
 487 static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
 488         { .compatible = "fsl,mpc5200-psc-spi", },
 489         { .compatible = "mpc5200-psc-spi", }, /* old */
 490         {}
 491 };
 492
 493 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
 494
 495 static struct platform_driver mpc52xx_psc_spi_of_driver = {
 496         .probe = mpc52xx_psc_spi_of_probe,
 497         .remove = mpc52xx_psc_spi_of_remove,
 498         .driver = {
 499                 .name = "mpc52xx-psc-spi",
 500                 .of_match_table = mpc52xx_psc_spi_of_match,
 501         },
 502 };
 503 module_platform_driver(mpc52xx_psc_spi_of_driver);
 504
 505 MODULE_AUTHOR("Dragos Carp");
 506 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
 507 MODULE_LICENSE("GPL");