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dmaengine: imx-sdma: Let the core do the device node validation
[linux/fpc-iii.git] / drivers / scsi / megaraid / megaraid_sas_fusion.h
blob1481bf0294900155c931f4d33d3fe176886cd2c2
1 /*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
4 * Copyright (c) 2009-2013 LSI Corporation
5 * Copyright (c) 2013-2016 Avago Technologies
6 * Copyright (c) 2016-2018 Broadcom Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 * FILE: megaraid_sas_fusion.h
22 *
23 * Authors: Broadcom Inc.
24 * Manoj Jose
25 * Sumant Patro
26 * Kashyap Desai <kashyap.desai@broadcom.com>
27 * Sumit Saxena <sumit.saxena@broadcom.com>
28 *
29 * Send feedback to: megaraidlinux.pdl@broadcom.com
30 */
31
32 #ifndef _MEGARAID_SAS_FUSION_H_
33 #define _MEGARAID_SAS_FUSION_H_
34
35 /* Fusion defines */
36 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
38 #define MEGASAS_MAX_CHAIN_SHIFT 5
39 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
40 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
41 #define MEGASAS_256K_IO 128
42 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
43 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
44 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
45 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
46 #define MEGASAS_LOAD_BALANCE_FLAG 0x1
47 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
48 #define HOST_DIAG_WRITE_ENABLE 0x80
49 #define HOST_DIAG_RESET_ADAPTER 0x4
50 #define MEGASAS_FUSION_MAX_RESET_TRIES 3
51 #define MAX_MSIX_QUEUES_FUSION 128
52 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
53 #define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
54
55 /* Invader defines */
56 #define MPI2_TYPE_CUDA 0x2
57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
62 #define MR_RL_WRITE_THROUGH_MODE 0x00
63 #define MR_RL_WRITE_BACK_MODE 0x01
64
65 /* T10 PI defines */
66 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
67 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
68 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
69 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
70 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
71 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
72 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
73
74 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
75 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
76
77 /*
78 * Raid context flags
79 */
80
81 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
82 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
83 enum MR_RAID_FLAGS_IO_SUB_TYPE {
84 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
85 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
86 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
87 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
88 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
89 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
90 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
91 };
92
93 /*
94 * Request descriptor types
95 */
96 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
97 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
98 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
99 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
100
101 #define MEGASAS_FP_CMD_LEN 16
102 #define MEGASAS_FUSION_IN_RESET 0
103 #define THRESHOLD_REPLY_COUNT 50
104 #define RAID_1_PEER_CMDS 2
105 #define JBOD_MAPS_COUNT 2
106 #define MEGASAS_REDUCE_QD_COUNT 64
107 #define IOC_INIT_FRAME_SIZE 4096
108
109 /*
110 * Raid Context structure which describes MegaRAID specific IO Parameters
111 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
112 */
113
114 struct RAID_CONTEXT {
115 #if defined(__BIG_ENDIAN_BITFIELD)
116 u8 nseg:4;
117 u8 type:4;
118 #else
119 u8 type:4;
120 u8 nseg:4;
121 #endif
122 u8 resvd0;
123 __le16 timeout_value;
124 u8 reg_lock_flags;
125 u8 resvd1;
126 __le16 virtual_disk_tgt_id;
127 __le64 reg_lock_row_lba;
128 __le32 reg_lock_length;
129 __le16 next_lmid;
130 u8 ex_status;
131 u8 status;
132 u8 raid_flags;
133 u8 num_sge;
134 __le16 config_seq_num;
135 u8 span_arm;
136 u8 priority;
137 u8 num_sge_ext;
138 u8 resvd2;
139 };
140
141 /*
142 * Raid Context structure which describes ventura MegaRAID specific
143 * IO Paramenters ,This resides at offset 0x60 where the SGL normally
144 * starts in MPT IO Frames
145 */
146 struct RAID_CONTEXT_G35 {
147 #define RAID_CONTEXT_NSEG_MASK 0x00F0
148 #define RAID_CONTEXT_NSEG_SHIFT 4
149 #define RAID_CONTEXT_TYPE_MASK 0x000F
150 #define RAID_CONTEXT_TYPE_SHIFT 0
151 u16 nseg_type;
152 u16 timeout_value; /* 0x02 -0x03 */
153 u16 routing_flags; // 0x04 -0x05 routing flags
154 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */
155 u64 reg_lock_row_lba; /* 0x08 - 0x0F */
156 u32 reg_lock_length; /* 0x10 - 0x13 */
157 union {
158 u16 next_lmid; /* 0x14 - 0x15 */
159 u16 peer_smid; /* used for the raid 1/10 fp writes */
160 } smid;
161 u8 ex_status; /* 0x16 : OUT */
162 u8 status; /* 0x17 status */
163 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4],
164 * resvd[3:1], preferredCpu[0]
165 */
166 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */
167 u16 config_seq_num; /* 0x1A -0x1B */
168 union {
169 /*
170 * Bit format:
171 * ---------------------------------
172 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
173 * ---------------------------------
174 * Byte0 | numSGE[7]- numSGE[0] |
175 * ---------------------------------
176 * Byte1 |SD | resvd | numSGE 8-11 |
177 * --------------------------------
178 */
179 #define NUM_SGE_MASK_LOWER 0xFF
180 #define NUM_SGE_MASK_UPPER 0x0F
181 #define NUM_SGE_SHIFT_UPPER 8
182 #define STREAM_DETECT_SHIFT 7
183 #define STREAM_DETECT_MASK 0x80
184 struct {
185 #if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
186 u16 stream_detected:1;
187 u16 reserved:3;
188 u16 num_sge:12;
189 #else
190 u16 num_sge:12;
191 u16 reserved:3;
192 u16 stream_detected:1;
193 #endif
194 } bits;
195 u8 bytes[2];
196 } u;
197 u8 resvd2[2]; /* 0x1E-0x1F */
198 };
199
200 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
201 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
202 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
203 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
204 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
205 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
206 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
207 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
208 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
209 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
210 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
211
212 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
213 u16 sge_count)
214 {
215 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
216 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
217 & NUM_SGE_MASK_UPPER);
218 }
219
220 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
221 {
222 u16 sge_count;
223
224 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
225 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
226 return sge_count;
227 }
228
229 #define SET_STREAM_DETECTED(rctx_g35) \
230 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
231
232 #define CLEAR_STREAM_DETECTED(rctx_g35) \
233 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
234
235 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
236 {
237 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
238 }
239
240 union RAID_CONTEXT_UNION {
241 struct RAID_CONTEXT raid_context;
242 struct RAID_CONTEXT_G35 raid_context_g35;
243 };
244
245 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
246 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
247
248 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
249 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
250
251 /* number of bits per index in U32 TrackStream */
252 #define BITS_PER_INDEX_STREAM 4
253 #define INVALID_STREAM_NUM 16
254 #define MR_STREAM_BITMAP 0x76543210
255 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
256 #define ZERO_LAST_STREAM 0x0fffffff
257 #define MAX_STREAMS_TRACKED 8
258
259 /*
260 * define region lock types
261 */
262 enum REGION_TYPE {
263 REGION_TYPE_UNUSED = 0,
264 REGION_TYPE_SHARED_READ = 1,
265 REGION_TYPE_SHARED_WRITE = 2,
266 REGION_TYPE_EXCLUSIVE = 3,
267 };
268
269 /* MPI2 defines */
270 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
271 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
272 #define MPI2_VERSION_MAJOR (0x02)
273 #define MPI2_VERSION_MINOR (0x00)
274 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
275 #define MPI2_VERSION_MAJOR_SHIFT (8)
276 #define MPI2_VERSION_MINOR_MASK (0x00FF)
277 #define MPI2_VERSION_MINOR_SHIFT (0)
278 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
279 MPI2_VERSION_MINOR)
280 #define MPI2_HEADER_VERSION_UNIT (0x10)
281 #define MPI2_HEADER_VERSION_DEV (0x00)
282 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
283 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
284 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
285 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
286 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
287 MPI2_HEADER_VERSION_DEV)
288 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
289 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
293 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
294 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
295 /* EEDP escape mode */
296 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
297 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
298 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
299 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
300 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
301 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
302 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
303 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
304 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
305 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
306 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
307 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
308 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
309 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
310 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
311 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
312 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
313 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
314 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
315 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
316 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
317
318 struct MPI25_IEEE_SGE_CHAIN64 {
319 __le64 Address;
320 __le32 Length;
321 __le16 Reserved1;
322 u8 NextChainOffset;
323 u8 Flags;
324 };
325
326 struct MPI2_SGE_SIMPLE_UNION {
327 __le32 FlagsLength;
328 union {
329 __le32 Address32;
330 __le64 Address64;
331 } u;
332 };
333
334 struct MPI2_SCSI_IO_CDB_EEDP32 {
335 u8 CDB[20]; /* 0x00 */
336 __be32 PrimaryReferenceTag; /* 0x14 */
337 __be16 PrimaryApplicationTag; /* 0x18 */
338 __be16 PrimaryApplicationTagMask; /* 0x1A */
339 __le32 TransferLength; /* 0x1C */
340 };
341
342 struct MPI2_SGE_CHAIN_UNION {
343 __le16 Length;
344 u8 NextChainOffset;
345 u8 Flags;
346 union {
347 __le32 Address32;
348 __le64 Address64;
349 } u;
350 };
351
352 struct MPI2_IEEE_SGE_SIMPLE32 {
353 __le32 Address;
354 __le32 FlagsLength;
355 };
356
357 struct MPI2_IEEE_SGE_CHAIN32 {
358 __le32 Address;
359 __le32 FlagsLength;
360 };
361
362 struct MPI2_IEEE_SGE_SIMPLE64 {
363 __le64 Address;
364 __le32 Length;
365 __le16 Reserved1;
366 u8 Reserved2;
367 u8 Flags;
368 };
369
370 struct MPI2_IEEE_SGE_CHAIN64 {
371 __le64 Address;
372 __le32 Length;
373 __le16 Reserved1;
374 u8 Reserved2;
375 u8 Flags;
376 };
377
378 union MPI2_IEEE_SGE_SIMPLE_UNION {
379 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
380 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
381 };
382
383 union MPI2_IEEE_SGE_CHAIN_UNION {
384 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
385 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
386 };
387
388 union MPI2_SGE_IO_UNION {
389 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
390 struct MPI2_SGE_CHAIN_UNION MpiChain;
391 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
392 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
393 };
394
395 union MPI2_SCSI_IO_CDB_UNION {
396 u8 CDB32[32];
397 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
398 struct MPI2_SGE_SIMPLE_UNION SGE;
399 };
400
401 /****************************************************************************
402 * SCSI Task Management messages
403 ****************************************************************************/
404
405 /*SCSI Task Management Request Message */
406 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
407 u16 DevHandle; /*0x00 */
408 u8 ChainOffset; /*0x02 */
409 u8 Function; /*0x03 */
410 u8 Reserved1; /*0x04 */
411 u8 TaskType; /*0x05 */
412 u8 Reserved2; /*0x06 */
413 u8 MsgFlags; /*0x07 */
414 u8 VP_ID; /*0x08 */
415 u8 VF_ID; /*0x09 */
416 u16 Reserved3; /*0x0A */
417 u8 LUN[8]; /*0x0C */
418 u32 Reserved4[7]; /*0x14 */
419 u16 TaskMID; /*0x30 */
420 u16 Reserved5; /*0x32 */
421 };
422
423
424 /*SCSI Task Management Reply Message */
425 struct MPI2_SCSI_TASK_MANAGE_REPLY {
426 u16 DevHandle; /*0x00 */
427 u8 MsgLength; /*0x02 */
428 u8 Function; /*0x03 */
429 u8 ResponseCode; /*0x04 */
430 u8 TaskType; /*0x05 */
431 u8 Reserved1; /*0x06 */
432 u8 MsgFlags; /*0x07 */
433 u8 VP_ID; /*0x08 */
434 u8 VF_ID; /*0x09 */
435 u16 Reserved2; /*0x0A */
436 u16 Reserved3; /*0x0C */
437 u16 IOCStatus; /*0x0E */
438 u32 IOCLogInfo; /*0x10 */
439 u32 TerminationCount; /*0x14 */
440 u32 ResponseInfo; /*0x18 */
441 };
442
443 struct MR_TM_REQUEST {
444 char request[128];
445 };
446
447 struct MR_TM_REPLY {
448 char reply[128];
449 };
450
451 /* SCSI Task Management Request Message */
452 struct MR_TASK_MANAGE_REQUEST {
453 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
454 struct MR_TM_REQUEST TmRequest;
455 union {
456 struct {
457 #if defined(__BIG_ENDIAN_BITFIELD)
458 u32 reserved1:30;
459 u32 isTMForPD:1;
460 u32 isTMForLD:1;
461 #else
462 u32 isTMForLD:1;
463 u32 isTMForPD:1;
464 u32 reserved1:30;
465 #endif
466 u32 reserved2;
467 } tmReqFlags;
468 struct MR_TM_REPLY TMReply;
469 };
470 };
471
472 /* TaskType values */
473
474 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
475 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
476 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
477 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
478 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
479 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
480 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
481 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
482 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
483
484 /* ResponseCode values */
485
486 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
487 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
488 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
489 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
490 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
491 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
492 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
493 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
494
495 /*
496 * RAID SCSI IO Request Message
497 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
498 */
499 struct MPI2_RAID_SCSI_IO_REQUEST {
500 __le16 DevHandle; /* 0x00 */
501 u8 ChainOffset; /* 0x02 */
502 u8 Function; /* 0x03 */
503 __le16 Reserved1; /* 0x04 */
504 u8 Reserved2; /* 0x06 */
505 u8 MsgFlags; /* 0x07 */
506 u8 VP_ID; /* 0x08 */
507 u8 VF_ID; /* 0x09 */
508 __le16 Reserved3; /* 0x0A */
509 __le32 SenseBufferLowAddress; /* 0x0C */
510 __le16 SGLFlags; /* 0x10 */
511 u8 SenseBufferLength; /* 0x12 */
512 u8 Reserved4; /* 0x13 */
513 u8 SGLOffset0; /* 0x14 */
514 u8 SGLOffset1; /* 0x15 */
515 u8 SGLOffset2; /* 0x16 */
516 u8 SGLOffset3; /* 0x17 */
517 __le32 SkipCount; /* 0x18 */
518 __le32 DataLength; /* 0x1C */
519 __le32 BidirectionalDataLength; /* 0x20 */
520 __le16 IoFlags; /* 0x24 */
521 __le16 EEDPFlags; /* 0x26 */
522 __le32 EEDPBlockSize; /* 0x28 */
523 __le32 SecondaryReferenceTag; /* 0x2C */
524 __le16 SecondaryApplicationTag; /* 0x30 */
525 __le16 ApplicationTagTranslationMask; /* 0x32 */
526 u8 LUN[8]; /* 0x34 */
527 __le32 Control; /* 0x3C */
528 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
529 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */
530 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
531 };
532
533 /*
534 * MPT RAID MFA IO Descriptor.
535 */
536 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
537 u32 RequestFlags:8;
538 u32 MessageAddress1:24;
539 u32 MessageAddress2;
540 };
541
542 /* Default Request Descriptor */
543 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
544 u8 RequestFlags; /* 0x00 */
545 u8 MSIxIndex; /* 0x01 */
546 __le16 SMID; /* 0x02 */
547 __le16 LMID; /* 0x04 */
548 __le16 DescriptorTypeDependent; /* 0x06 */
549 };
550
551 /* High Priority Request Descriptor */
552 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
553 u8 RequestFlags; /* 0x00 */
554 u8 MSIxIndex; /* 0x01 */
555 __le16 SMID; /* 0x02 */
556 __le16 LMID; /* 0x04 */
557 __le16 Reserved1; /* 0x06 */
558 };
559
560 /* SCSI IO Request Descriptor */
561 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
562 u8 RequestFlags; /* 0x00 */
563 u8 MSIxIndex; /* 0x01 */
564 __le16 SMID; /* 0x02 */
565 __le16 LMID; /* 0x04 */
566 __le16 DevHandle; /* 0x06 */
567 };
568
569 /* SCSI Target Request Descriptor */
570 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
571 u8 RequestFlags; /* 0x00 */
572 u8 MSIxIndex; /* 0x01 */
573 __le16 SMID; /* 0x02 */
574 __le16 LMID; /* 0x04 */
575 __le16 IoIndex; /* 0x06 */
576 };
577
578 /* RAID Accelerator Request Descriptor */
579 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
580 u8 RequestFlags; /* 0x00 */
581 u8 MSIxIndex; /* 0x01 */
582 __le16 SMID; /* 0x02 */
583 __le16 LMID; /* 0x04 */
584 __le16 Reserved; /* 0x06 */
585 };
586
587 /* union of Request Descriptors */
588 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
589 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
590 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
591 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
592 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
593 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
594 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
595 union {
596 struct {
597 __le32 low;
598 __le32 high;
599 } u;
600 __le64 Words;
601 };
602 };
603
604 /* Default Reply Descriptor */
605 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
606 u8 ReplyFlags; /* 0x00 */
607 u8 MSIxIndex; /* 0x01 */
608 __le16 DescriptorTypeDependent1; /* 0x02 */
609 __le32 DescriptorTypeDependent2; /* 0x04 */
610 };
611
612 /* Address Reply Descriptor */
613 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
614 u8 ReplyFlags; /* 0x00 */
615 u8 MSIxIndex; /* 0x01 */
616 __le16 SMID; /* 0x02 */
617 __le32 ReplyFrameAddress; /* 0x04 */
618 };
619
620 /* SCSI IO Success Reply Descriptor */
621 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
622 u8 ReplyFlags; /* 0x00 */
623 u8 MSIxIndex; /* 0x01 */
624 __le16 SMID; /* 0x02 */
625 __le16 TaskTag; /* 0x04 */
626 __le16 Reserved1; /* 0x06 */
627 };
628
629 /* TargetAssist Success Reply Descriptor */
630 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
631 u8 ReplyFlags; /* 0x00 */
632 u8 MSIxIndex; /* 0x01 */
633 __le16 SMID; /* 0x02 */
634 u8 SequenceNumber; /* 0x04 */
635 u8 Reserved1; /* 0x05 */
636 __le16 IoIndex; /* 0x06 */
637 };
638
639 /* Target Command Buffer Reply Descriptor */
640 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
641 u8 ReplyFlags; /* 0x00 */
642 u8 MSIxIndex; /* 0x01 */
643 u8 VP_ID; /* 0x02 */
644 u8 Flags; /* 0x03 */
645 __le16 InitiatorDevHandle; /* 0x04 */
646 __le16 IoIndex; /* 0x06 */
647 };
648
649 /* RAID Accelerator Success Reply Descriptor */
650 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
651 u8 ReplyFlags; /* 0x00 */
652 u8 MSIxIndex; /* 0x01 */
653 __le16 SMID; /* 0x02 */
654 __le32 Reserved; /* 0x04 */
655 };
656
657 /* union of Reply Descriptors */
658 union MPI2_REPLY_DESCRIPTORS_UNION {
659 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
660 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
661 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
662 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
663 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
664 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
665 RAIDAcceleratorSuccess;
666 __le64 Words;
667 };
668
669 /* IOCInit Request message */
670 struct MPI2_IOC_INIT_REQUEST {
671 u8 WhoInit; /* 0x00 */
672 u8 Reserved1; /* 0x01 */
673 u8 ChainOffset; /* 0x02 */
674 u8 Function; /* 0x03 */
675 __le16 Reserved2; /* 0x04 */
676 u8 Reserved3; /* 0x06 */
677 u8 MsgFlags; /* 0x07 */
678 u8 VP_ID; /* 0x08 */
679 u8 VF_ID; /* 0x09 */
680 __le16 Reserved4; /* 0x0A */
681 __le16 MsgVersion; /* 0x0C */
682 __le16 HeaderVersion; /* 0x0E */
683 u32 Reserved5; /* 0x10 */
684 __le16 Reserved6; /* 0x14 */
685 u8 HostPageSize; /* 0x16 */
686 u8 HostMSIxVectors; /* 0x17 */
687 __le16 Reserved8; /* 0x18 */
688 __le16 SystemRequestFrameSize; /* 0x1A */
689 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */
690 __le16 ReplyFreeQueueDepth; /* 0x1E */
691 __le32 SenseBufferAddressHigh; /* 0x20 */
692 __le32 SystemReplyAddressHigh; /* 0x24 */
693 __le64 SystemRequestFrameBaseAddress; /* 0x28 */
694 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */
695 __le64 ReplyFreeQueueAddress; /* 0x38 */
696 __le64 TimeStamp; /* 0x40 */
697 };
698
699 /* mrpriv defines */
700 #define MR_PD_INVALID 0xFFFF
701 #define MR_DEVHANDLE_INVALID 0xFFFF
702 #define MAX_SPAN_DEPTH 8
703 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
704 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
705 #define MAX_ROW_SIZE 32
706 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
707 #define MAX_LOGICAL_DRIVES 64
708 #define MAX_LOGICAL_DRIVES_EXT 256
709 #define MAX_LOGICAL_DRIVES_DYN 512
710 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
711 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
712 #define MAX_ARRAYS 128
713 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
714 #define MAX_ARRAYS_EXT 256
715 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
716 #define MAX_API_ARRAYS_DYN 512
717 #define MAX_PHYSICAL_DEVICES 256
718 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
719 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
720 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
721 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
722 #define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
723 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
724 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
725 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
726 #define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES 0x01200100
727 #define MR_DCMD_CTRL_DEVICE_LIST_GET 0x01190600
728
729 struct MR_DEV_HANDLE_INFO {
730 __le16 curDevHdl;
731 u8 validHandles;
732 u8 interfaceType;
733 __le16 devHandle[2];
734 };
735
736 struct MR_ARRAY_INFO {
737 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
738 };
739
740 struct MR_QUAD_ELEMENT {
741 __le64 logStart;
742 __le64 logEnd;
743 __le64 offsetInSpan;
744 __le32 diff;
745 __le32 reserved1;
746 };
747
748 struct MR_SPAN_INFO {
749 __le32 noElements;
750 __le32 reserved1;
751 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
752 };
753
754 struct MR_LD_SPAN {
755 __le64 startBlk;
756 __le64 numBlks;
757 __le16 arrayRef;
758 u8 spanRowSize;
759 u8 spanRowDataSize;
760 u8 reserved[4];
761 };
762
763 struct MR_SPAN_BLOCK_INFO {
764 __le64 num_rows;
765 struct MR_LD_SPAN span;
766 struct MR_SPAN_INFO block_span_info;
767 };
768
769 #define MR_RAID_CTX_CPUSEL_0 0
770 #define MR_RAID_CTX_CPUSEL_1 1
771 #define MR_RAID_CTX_CPUSEL_2 2
772 #define MR_RAID_CTX_CPUSEL_3 3
773 #define MR_RAID_CTX_CPUSEL_FCFS 0xF
774
775 struct MR_CPU_AFFINITY_MASK {
776 union {
777 struct {
778 #ifndef MFI_BIG_ENDIAN
779 u8 hw_path:1;
780 u8 cpu0:1;
781 u8 cpu1:1;
782 u8 cpu2:1;
783 u8 cpu3:1;
784 u8 reserved:3;
785 #else
786 u8 reserved:3;
787 u8 cpu3:1;
788 u8 cpu2:1;
789 u8 cpu1:1;
790 u8 cpu0:1;
791 u8 hw_path:1;
792 #endif
793 };
794 u8 core_mask;
795 };
796 };
797
798 struct MR_IO_AFFINITY {
799 union {
800 struct {
801 struct MR_CPU_AFFINITY_MASK pdRead;
802 struct MR_CPU_AFFINITY_MASK pdWrite;
803 struct MR_CPU_AFFINITY_MASK ldRead;
804 struct MR_CPU_AFFINITY_MASK ldWrite;
805 };
806 u32 word;
807 };
808 u8 maxCores; /* Total cores + HW Path in ROC */
809 u8 reserved[3];
810 };
811
812 struct MR_LD_RAID {
813 struct {
814 #if defined(__BIG_ENDIAN_BITFIELD)
815 u32 reserved4:2;
816 u32 fp_cache_bypass_capable:1;
817 u32 fp_rmw_capable:1;
818 u32 disable_coalescing:1;
819 u32 fpBypassRegionLock:1;
820 u32 tmCapable:1;
821 u32 fpNonRWCapable:1;
822 u32 fpReadAcrossStripe:1;
823 u32 fpWriteAcrossStripe:1;
824 u32 fpReadCapable:1;
825 u32 fpWriteCapable:1;
826 u32 encryptionType:8;
827 u32 pdPiMode:4;
828 u32 ldPiMode:4;
829 u32 reserved5:2;
830 u32 ra_capable:1;
831 u32 fpCapable:1;
832 #else
833 u32 fpCapable:1;
834 u32 ra_capable:1;
835 u32 reserved5:2;
836 u32 ldPiMode:4;
837 u32 pdPiMode:4;
838 u32 encryptionType:8;
839 u32 fpWriteCapable:1;
840 u32 fpReadCapable:1;
841 u32 fpWriteAcrossStripe:1;
842 u32 fpReadAcrossStripe:1;
843 u32 fpNonRWCapable:1;
844 u32 tmCapable:1;
845 u32 fpBypassRegionLock:1;
846 u32 disable_coalescing:1;
847 u32 fp_rmw_capable:1;
848 u32 fp_cache_bypass_capable:1;
849 u32 reserved4:2;
850 #endif
851 } capability;
852 __le32 reserved6;
853 __le64 size;
854 u8 spanDepth;
855 u8 level;
856 u8 stripeShift;
857 u8 rowSize;
858 u8 rowDataSize;
859 u8 writeMode;
860 u8 PRL;
861 u8 SRL;
862 __le16 targetId;
863 u8 ldState;
864 u8 regTypeReqOnWrite;
865 u8 modFactor;
866 u8 regTypeReqOnRead;
867 __le16 seqNum;
868
869 struct {
870 u32 ldSyncRequired:1;
871 u32 reserved:31;
872 } flags;
873
874 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
875 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
876 /* Ox2D This LD accept priority boost of this type */
877 u8 ld_accept_priority_type;
878 u8 reserved2[2]; /* 0x2E - 0x2F */
879 /* 0x30 - 0x33, Logical block size for the LD */
880 u32 logical_block_length;
881 struct {
882 #ifndef MFI_BIG_ENDIAN
883 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
884 u32 ld_pi_exp:4;
885 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
886 * BLOCK EXPONENT from READ CAPACITY 16
887 */
888 u32 ld_logical_block_exp:4;
889 u32 reserved1:24; /* 0x34 */
890 #else
891 u32 reserved1:24; /* 0x34 */
892 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
893 * BLOCK EXPONENT from READ CAPACITY 16
894 */
895 u32 ld_logical_block_exp:4;
896 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
897 u32 ld_pi_exp:4;
898 #endif
899 }; /* 0x34 - 0x37 */
900 /* 0x38 - 0x3f, This will determine which
901 * core will process LD IO and PD IO.
902 */
903 struct MR_IO_AFFINITY cpuAffinity;
904 /* Bit definiations are specified by MR_IO_AFFINITY */
905 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */
906 };
907
908 struct MR_LD_SPAN_MAP {
909 struct MR_LD_RAID ldRaid;
910 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
911 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
912 };
913
914 struct MR_FW_RAID_MAP {
915 __le32 totalSize;
916 union {
917 struct {
918 __le32 maxLd;
919 __le32 maxSpanDepth;
920 __le32 maxRowSize;
921 __le32 maxPdCount;
922 __le32 maxArrays;
923 } validationInfo;
924 __le32 version[5];
925 };
926
927 __le32 ldCount;
928 __le32 Reserved1;
929 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
930 MAX_RAIDMAP_VIEWS];
931 u8 fpPdIoTimeoutSec;
932 u8 reserved2[7];
933 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
934 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
935 struct MR_LD_SPAN_MAP ldSpanMap[1];
936 };
937
938 struct IO_REQUEST_INFO {
939 u64 ldStartBlock;
940 u32 numBlocks;
941 u16 ldTgtId;
942 u8 isRead;
943 __le16 devHandle;
944 u8 pd_interface;
945 u64 pdBlock;
946 u8 fpOkForIo;
947 u8 IoforUnevenSpan;
948 u8 start_span;
949 u8 do_fp_rlbypass;
950 u64 start_row;
951 u8 span_arm; /* span[7:5], arm[4:0] */
952 u8 pd_after_lb;
953 u16 r1_alt_dev_handle; /* raid 1/10 only */
954 bool ra_capable;
955 };
956
957 struct MR_LD_TARGET_SYNC {
958 u8 targetId;
959 u8 reserved;
960 __le16 seqNum;
961 };
962
963 /*
964 * RAID Map descriptor Types.
965 * Each element should uniquely idetify one data structure in the RAID map
966 */
967 enum MR_RAID_MAP_DESC_TYPE {
968 /* MR_DEV_HANDLE_INFO data */
969 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
970 /* target to Ld num Index map */
971 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
972 /* MR_ARRAY_INFO data */
973 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
974 /* MR_LD_SPAN_MAP data */
975 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
976 RAID_MAP_DESC_TYPE_COUNT,
977 };
978
979 /*
980 * This table defines the offset, size and num elements of each descriptor
981 * type in the RAID Map buffer
982 */
983 struct MR_RAID_MAP_DESC_TABLE {
984 /* Raid map descriptor type */
985 u32 raid_map_desc_type;
986 /* Offset into the RAID map buffer where
987 * descriptor data is saved
988 */
989 u32 raid_map_desc_offset;
990 /* total size of the
991 * descriptor buffer
992 */
993 u32 raid_map_desc_buffer_size;
994 /* Number of elements contained in the
995 * descriptor buffer
996 */
997 u32 raid_map_desc_elements;
998 };
999
1000 /*
1001 * Dynamic Raid Map Structure.
1002 */
1003 struct MR_FW_RAID_MAP_DYNAMIC {
1004 u32 raid_map_size; /* total size of RAID Map structure */
1005 u32 desc_table_offset;/* Offset of desc table into RAID map*/
1006 u32 desc_table_size; /* Total Size of desc table */
1007 /* Total Number of elements in the desc table */
1008 u32 desc_table_num_elements;
1009 u64 reserved1;
1010 u32 reserved2[3]; /*future use */
1011 /* timeout value used by driver in FP IOs */
1012 u8 fp_pd_io_timeout_sec;
1013 u8 reserved3[3];
1014 /* when this seqNum increments, driver needs to
1015 * release RMW buffers asap
1016 */
1017 u32 rmw_fp_seq_num;
1018 u16 ld_count; /* count of lds. */
1019 u16 ar_count; /* count of arrays */
1020 u16 span_count; /* count of spans */
1021 u16 reserved4[3];
1022 /*
1023 * The below structure of pointers is only to be used by the driver.
1024 * This is added in the ,API to reduce the amount of code changes
1025 * needed in the driver to support dynamic RAID map Firmware should
1026 * not update these pointers while preparing the raid map
1027 */
1028 union {
1029 struct {
1030 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1031 u16 *ld_tgt_id_to_ld;
1032 struct MR_ARRAY_INFO *ar_map_info;
1033 struct MR_LD_SPAN_MAP *ld_span_map;
1034 };
1035 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1036 };
1037 /*
1038 * RAID Map descriptor table defines the layout of data in the RAID Map.
1039 * The size of the descriptor table itself could change.
1040 */
1041 /* Variable Size descriptor Table. */
1042 struct MR_RAID_MAP_DESC_TABLE
1043 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1044 /* Variable Size buffer containing all data */
1045 u32 raid_map_desc_data[1];
1046 }; /* Dynamicaly sized RAID MAp structure */
1047
1048 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1049 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1050 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1051 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1052 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1053 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1054 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1055
1056 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1057 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1058 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1059 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1060
1061 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1062 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1063 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1064 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1065
1066 #define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15
1067 #define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60
1068
1069 struct megasas_register_set;
1070 struct megasas_instance;
1071
1072 union desc_word {
1073 u64 word;
1074 struct {
1075 u32 low;
1076 u32 high;
1077 } u;
1078 };
1079
1080 struct megasas_cmd_fusion {
1081 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1082 dma_addr_t io_request_phys_addr;
1083
1084 union MPI2_SGE_IO_UNION *sg_frame;
1085 dma_addr_t sg_frame_phys_addr;
1086
1087 u8 *sense;
1088 dma_addr_t sense_phys_addr;
1089
1090 struct list_head list;
1091 struct scsi_cmnd *scmd;
1092 struct megasas_instance *instance;
1093
1094 u8 retry_for_fw_reset;
1095 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1096
1097 /*
1098 * Context for a MFI frame.
1099 * Used to get the mfi cmd from list when a MFI cmd is completed
1100 */
1101 u32 sync_cmd_idx;
1102 u32 index;
1103 u8 pd_r1_lb;
1104 struct completion done;
1105 u8 pd_interface;
1106 u16 r1_alt_dev_handle; /* raid 1/10 only*/
1107 bool cmd_completed; /* raid 1/10 fp writes status holder */
1108
1109 };
1110
1111 struct LD_LOAD_BALANCE_INFO {
1112 u8 loadBalanceFlag;
1113 u8 reserved1;
1114 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1115 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
1116 };
1117
1118 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1119 typedef struct _LD_SPAN_SET {
1120 u64 log_start_lba;
1121 u64 log_end_lba;
1122 u64 span_row_start;
1123 u64 span_row_end;
1124 u64 data_strip_start;
1125 u64 data_strip_end;
1126 u64 data_row_start;
1127 u64 data_row_end;
1128 u8 strip_offset[MAX_SPAN_DEPTH];
1129 u32 span_row_data_width;
1130 u32 diff;
1131 u32 reserved[2];
1132 } LD_SPAN_SET, *PLD_SPAN_SET;
1133
1134 typedef struct LOG_BLOCK_SPAN_INFO {
1135 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1136 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1137
1138 struct MR_FW_RAID_MAP_ALL {
1139 struct MR_FW_RAID_MAP raidMap;
1140 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1141 } __attribute__ ((packed));
1142
1143 struct MR_DRV_RAID_MAP {
1144 /* total size of this structure, including this field.
1145 * This feild will be manupulated by driver for ext raid map,
1146 * else pick the value from firmware raid map.
1147 */
1148 __le32 totalSize;
1149
1150 union {
1151 struct {
1152 __le32 maxLd;
1153 __le32 maxSpanDepth;
1154 __le32 maxRowSize;
1155 __le32 maxPdCount;
1156 __le32 maxArrays;
1157 } validationInfo;
1158 __le32 version[5];
1159 };
1160
1161 /* timeout value used by driver in FP IOs*/
1162 u8 fpPdIoTimeoutSec;
1163 u8 reserved2[7];
1164
1165 __le16 ldCount;
1166 __le16 arCount;
1167 __le16 spanCount;
1168 __le16 reserve3;
1169
1170 struct MR_DEV_HANDLE_INFO
1171 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1172 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1173 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1174 struct MR_LD_SPAN_MAP ldSpanMap[1];
1175
1176 };
1177
1178 /* Driver raid map size is same as raid map ext
1179 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1180 * And it is mainly for code re-use purpose.
1181 */
1182 struct MR_DRV_RAID_MAP_ALL {
1183
1184 struct MR_DRV_RAID_MAP raidMap;
1185 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1186 } __packed;
1187
1188
1189
1190 struct MR_FW_RAID_MAP_EXT {
1191 /* Not usred in new map */
1192 u32 reserved;
1193
1194 union {
1195 struct {
1196 u32 maxLd;
1197 u32 maxSpanDepth;
1198 u32 maxRowSize;
1199 u32 maxPdCount;
1200 u32 maxArrays;
1201 } validationInfo;
1202 u32 version[5];
1203 };
1204
1205 u8 fpPdIoTimeoutSec;
1206 u8 reserved2[7];
1207
1208 __le16 ldCount;
1209 __le16 arCount;
1210 __le16 spanCount;
1211 __le16 reserve3;
1212
1213 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1214 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1215 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1216 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1217 };
1218
1219 /*
1220 * * define MR_PD_CFG_SEQ structure for system PDs
1221 * */
1222 struct MR_PD_CFG_SEQ {
1223 u16 seqNum;
1224 u16 devHandle;
1225 struct {
1226 #if defined(__BIG_ENDIAN_BITFIELD)
1227 u8 reserved:7;
1228 u8 tmCapable:1;
1229 #else
1230 u8 tmCapable:1;
1231 u8 reserved:7;
1232 #endif
1233 } capability;
1234 u8 reserved;
1235 u16 pd_target_id;
1236 } __packed;
1237
1238 struct MR_PD_CFG_SEQ_NUM_SYNC {
1239 __le32 size;
1240 __le32 count;
1241 struct MR_PD_CFG_SEQ seq[1];
1242 } __packed;
1243
1244 /* stream detection */
1245 struct STREAM_DETECT {
1246 u64 next_seq_lba; /* next LBA to match sequential access */
1247 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1248 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1249 u32 count_cmds_in_stream; /* count of host commands in this stream */
1250 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1251 u8 is_read; /* SCSI OpCode for this stream */
1252 u8 group_depth; /* total number of host commands in group */
1253 /* TRUE if cannot add any more commands to this group */
1254 bool group_flush;
1255 u8 reserved[7]; /* pad to 64-bit alignment */
1256 };
1257
1258 struct LD_STREAM_DETECT {
1259 bool write_back; /* TRUE if WB, FALSE if WT */
1260 bool fp_write_enabled;
1261 bool members_ssds;
1262 bool fp_cache_bypass_capable;
1263 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1264 /* this is the array of stream detect structures (one per stream) */
1265 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1266 };
1267
1268 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1269 u64 RDPQBaseAddress;
1270 u32 Reserved1;
1271 u32 Reserved2;
1272 };
1273
1274 struct rdpq_alloc_detail {
1275 struct dma_pool *dma_pool_ptr;
1276 dma_addr_t pool_entry_phys;
1277 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1278 };
1279
1280 struct fusion_context {
1281 struct megasas_cmd_fusion **cmd_list;
1282 dma_addr_t req_frames_desc_phys;
1283 u8 *req_frames_desc;
1284
1285 struct dma_pool *io_request_frames_pool;
1286 dma_addr_t io_request_frames_phys;
1287 u8 *io_request_frames;
1288
1289 struct dma_pool *sg_dma_pool;
1290 struct dma_pool *sense_dma_pool;
1291
1292 u8 *sense;
1293 dma_addr_t sense_phys_addr;
1294
1295 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1296 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1297 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
1298 struct dma_pool *reply_frames_desc_pool;
1299 struct dma_pool *reply_frames_desc_pool_align;
1300
1301 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1302
1303 u32 reply_q_depth;
1304 u32 request_alloc_sz;
1305 u32 reply_alloc_sz;
1306 u32 io_frames_alloc_sz;
1307
1308 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1309 dma_addr_t rdpq_phys;
1310 u16 max_sge_in_main_msg;
1311 u16 max_sge_in_chain;
1312
1313 u8 chain_offset_io_request;
1314 u8 chain_offset_mfi_pthru;
1315
1316 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1317 dma_addr_t ld_map_phys[2];
1318
1319 /*Non dma-able memory. Driver local copy.*/
1320 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1321
1322 u32 max_map_sz;
1323 u32 current_map_sz;
1324 u32 old_map_sz;
1325 u32 new_map_sz;
1326 u32 drv_map_sz;
1327 u32 drv_map_pages;
1328 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1329 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1330 u8 fast_path_io;
1331 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1332 u32 load_balance_info_pages;
1333 LD_SPAN_INFO *log_to_span;
1334 u32 log_to_span_pages;
1335 struct LD_STREAM_DETECT **stream_detect_by_ld;
1336 dma_addr_t ioc_init_request_phys;
1337 struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1338 struct megasas_cmd *ioc_init_cmd;
1339
1340 };
1341
1342 union desc_value {
1343 __le64 word;
1344 struct {
1345 __le32 low;
1346 __le32 high;
1347 } u;
1348 };
1349
1350 enum CMD_RET_VALUES {
1351 REFIRE_CMD = 1,
1352 COMPLETE_CMD = 2,
1353 RETURN_CMD = 3,
1354 };
1355
1356 struct MR_SNAPDUMP_PROPERTIES {
1357 u8 offload_num;
1358 u8 max_num_supported;
1359 u8 cur_num_supported;
1360 u8 trigger_min_num_sec_before_ocr;
1361 u8 reserved[12];
1362 };
1363
1364 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1365 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1366 u8 megasas_get_map_info(struct megasas_instance *instance);
1367 int megasas_sync_map_info(struct megasas_instance *instance);
1368 void megasas_release_fusion(struct megasas_instance *instance);
1369 void megasas_reset_reply_desc(struct megasas_instance *instance);
1370 int megasas_check_mpio_paths(struct megasas_instance *instance,
1371 struct scsi_cmnd *scmd);
1372 void megasas_fusion_ocr_wq(struct work_struct *work);
1373
1374 #endif /* _MEGARAID_SAS_FUSION_H_ */
Linux with added FPC-III support