drivers/ata/ahci_qoriq.c

   1 /*
   2  * Freescale QorIQ AHCI SATA platform driver
   3  *
   4  * Copyright 2015 Freescale, Inc.
   5  *   Tang Yuantian <Yuantian.Tang@freescale.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pm.h>
  16 #include <linux/ahci_platform.h>
  17 #include <linux/device.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/libata.h>
  23 #include "ahci.h"
  24
  25 #define DRV_NAME "ahci-qoriq"
  26
  27 /* port register definition */
  28 #define PORT_PHY1       0xA8
  29 #define PORT_PHY2       0xAC
  30 #define PORT_PHY3       0xB0
  31 #define PORT_PHY4       0xB4
  32 #define PORT_PHY5       0xB8
  33 #define PORT_AXICC      0xBC
  34 #define PORT_TRANS      0xC8
  35
  36 /* port register default value */
  37 #define AHCI_PORT_PHY_1_CFG     0xa003fffe
  38 #define AHCI_PORT_TRANS_CFG     0x08000029
  39 #define AHCI_PORT_AXICC_CFG     0x3fffffff
  40
  41 /* for ls1021a */
  42 #define LS1021A_PORT_PHY2       0x28183414
  43 #define LS1021A_PORT_PHY3       0x0e080e06
  44 #define LS1021A_PORT_PHY4       0x064a080b
  45 #define LS1021A_PORT_PHY5       0x2aa86470
  46 #define LS1021A_AXICC_ADDR      0xC0
  47
  48 #define SATA_ECC_DISABLE        0x00020000
  49 #define ECC_DIS_ARMV8_CH2       0x80000000
  50 #define ECC_DIS_LS1088A         0x40000000
  51
  52 enum ahci_qoriq_type {
  53         AHCI_LS1021A,
  54         AHCI_LS1043A,
  55         AHCI_LS2080A,
  56         AHCI_LS1046A,
  57         AHCI_LS1088A,
  58         AHCI_LS2088A,
  59 };
  60
  61 struct ahci_qoriq_priv {
  62         struct ccsr_ahci *reg_base;
  63         enum ahci_qoriq_type type;
  64         void __iomem *ecc_addr;
  65         bool is_dmacoherent;
  66 };
  67
  68 static const struct of_device_id ahci_qoriq_of_match[] = {
  69         { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  70         { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  71         { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  72         { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
  73         { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
  74         { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
  75         {},
  76 };
  77 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  78
  79 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  80                           unsigned long deadline)
  81 {
  82         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  83         void __iomem *port_mmio = ahci_port_base(link->ap);
  84         u32 px_cmd, px_is, px_val;
  85         struct ata_port *ap = link->ap;
  86         struct ahci_port_priv *pp = ap->private_data;
  87         struct ahci_host_priv *hpriv = ap->host->private_data;
  88         struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  89         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  90         struct ata_taskfile tf;
  91         bool online;
  92         int rc;
  93         bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  94
  95         DPRINTK("ENTER\n");
  96
  97         ahci_stop_engine(ap);
  98
  99         /*
 100          * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
 101          * A-009042: The device detection initialization sequence
 102          * mistakenly resets some registers.
 103          *
 104          * Workaround for this is:
 105          * The software should read and store PxCMD and PxIS values
 106          * before issuing the device detection initialization sequence.
 107          * After the sequence is complete, software should restore the
 108          * PxCMD and PxIS with the stored values.
 109          */
 110         if (ls1021a_workaround) {
 111                 px_cmd = readl(port_mmio + PORT_CMD);
 112                 px_is = readl(port_mmio + PORT_IRQ_STAT);
 113         }
 114
 115         /* clear D2H reception area to properly wait for D2H FIS */
 116         ata_tf_init(link->device, &tf);
 117         tf.command = ATA_BUSY;
 118         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 119
 120         rc = sata_link_hardreset(link, timing, deadline, &online,
 121                                  ahci_check_ready);
 122
 123         /* restore the PxCMD and PxIS on ls1021 */
 124         if (ls1021a_workaround) {
 125                 px_val = readl(port_mmio + PORT_CMD);
 126                 if (px_val != px_cmd)
 127                         writel(px_cmd, port_mmio + PORT_CMD);
 128
 129                 px_val = readl(port_mmio + PORT_IRQ_STAT);
 130                 if (px_val != px_is)
 131                         writel(px_is, port_mmio + PORT_IRQ_STAT);
 132         }
 133
 134         hpriv->start_engine(ap);
 135
 136         if (online)
 137                 *class = ahci_dev_classify(ap);
 138
 139         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 140         return rc;
 141 }
 142
 143 static struct ata_port_operations ahci_qoriq_ops = {
 144         .inherits       = &ahci_ops,
 145         .hardreset      = ahci_qoriq_hardreset,
 146 };
 147
 148 static const struct ata_port_info ahci_qoriq_port_info = {
 149         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 150         .pio_mask       = ATA_PIO4,
 151         .udma_mask      = ATA_UDMA6,
 152         .port_ops       = &ahci_qoriq_ops,
 153 };
 154
 155 static struct scsi_host_template ahci_qoriq_sht = {
 156         AHCI_SHT(DRV_NAME),
 157 };
 158
 159 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 160 {
 161         struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
 162         void __iomem *reg_base = hpriv->mmio;
 163
 164         switch (qpriv->type) {
 165         case AHCI_LS1021A:
 166                 if (!qpriv->ecc_addr)
 167                         return -EINVAL;
 168                 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
 169                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 170                 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
 171                 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
 172                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
 173                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
 174                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 175                 if (qpriv->is_dmacoherent)
 176                         writel(AHCI_PORT_AXICC_CFG,
 177                                         reg_base + LS1021A_AXICC_ADDR);
 178                 break;
 179
 180         case AHCI_LS1043A:
 181                 if (!qpriv->ecc_addr)
 182                         return -EINVAL;
 183                 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
 184                                 qpriv->ecc_addr);
 185                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 186                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 187                 if (qpriv->is_dmacoherent)
 188                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 189                 break;
 190
 191         case AHCI_LS2080A:
 192                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 193                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 194                 if (qpriv->is_dmacoherent)
 195                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 196                 break;
 197
 198         case AHCI_LS1046A:
 199                 if (!qpriv->ecc_addr)
 200                         return -EINVAL;
 201                 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
 202                                 qpriv->ecc_addr);
 203                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 204                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 205                 if (qpriv->is_dmacoherent)
 206                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 207                 break;
 208
 209         case AHCI_LS1088A:
 210                 if (!qpriv->ecc_addr)
 211                         return -EINVAL;
 212                 writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
 213                        qpriv->ecc_addr);
 214                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 215                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 216                 if (qpriv->is_dmacoherent)
 217                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 218                 break;
 219
 220         case AHCI_LS2088A:
 221                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 222                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 223                 if (qpriv->is_dmacoherent)
 224                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 225                 break;
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int ahci_qoriq_probe(struct platform_device *pdev)
 232 {
 233         struct device_node *np = pdev->dev.of_node;
 234         struct device *dev = &pdev->dev;
 235         struct ahci_host_priv *hpriv;
 236         struct ahci_qoriq_priv *qoriq_priv;
 237         const struct of_device_id *of_id;
 238         struct resource *res;
 239         int rc;
 240
 241         hpriv = ahci_platform_get_resources(pdev);
 242         if (IS_ERR(hpriv))
 243                 return PTR_ERR(hpriv);
 244
 245         of_id = of_match_node(ahci_qoriq_of_match, np);
 246         if (!of_id)
 247                 return -ENODEV;
 248
 249         qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
 250         if (!qoriq_priv)
 251                 return -ENOMEM;
 252
 253         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
 254
 255         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 256                         "sata-ecc");
 257         if (res) {
 258                 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
 259                 if (IS_ERR(qoriq_priv->ecc_addr))
 260                         return PTR_ERR(qoriq_priv->ecc_addr);
 261         }
 262         qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
 263
 264         rc = ahci_platform_enable_resources(hpriv);
 265         if (rc)
 266                 return rc;
 267
 268         hpriv->plat_data = qoriq_priv;
 269         rc = ahci_qoriq_phy_init(hpriv);
 270         if (rc)
 271                 goto disable_resources;
 272
 273         rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
 274                                      &ahci_qoriq_sht);
 275         if (rc)
 276                 goto disable_resources;
 277
 278         return 0;
 279
 280 disable_resources:
 281         ahci_platform_disable_resources(hpriv);
 282
 283         return rc;
 284 }
 285
 286 #ifdef CONFIG_PM_SLEEP
 287 static int ahci_qoriq_resume(struct device *dev)
 288 {
 289         struct ata_host *host = dev_get_drvdata(dev);
 290         struct ahci_host_priv *hpriv = host->private_data;
 291         int rc;
 292
 293         rc = ahci_platform_enable_resources(hpriv);
 294         if (rc)
 295                 return rc;
 296
 297         rc = ahci_qoriq_phy_init(hpriv);
 298         if (rc)
 299                 goto disable_resources;
 300
 301         rc = ahci_platform_resume_host(dev);
 302         if (rc)
 303                 goto disable_resources;
 304
 305         /* We resumed so update PM runtime state */
 306         pm_runtime_disable(dev);
 307         pm_runtime_set_active(dev);
 308         pm_runtime_enable(dev);
 309
 310         return 0;
 311
 312 disable_resources:
 313         ahci_platform_disable_resources(hpriv);
 314
 315         return rc;
 316 }
 317 #endif
 318
 319 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
 320                          ahci_qoriq_resume);
 321
 322 static struct platform_driver ahci_qoriq_driver = {
 323         .probe = ahci_qoriq_probe,
 324         .remove = ata_platform_remove_one,
 325         .driver = {
 326                 .name = DRV_NAME,
 327                 .of_match_table = ahci_qoriq_of_match,
 328                 .pm = &ahci_qoriq_pm_ops,
 329         },
 330 };
 331 module_platform_driver(ahci_qoriq_driver);
 332
 333 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
 334 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
 335 MODULE_LICENSE("GPL");