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iwmc3200wifi: Implement cfg80211 PMKSA API
[linux/fpc-iii.git] / drivers / video / mx3fb.c
blob054ef29be4795dd75900b9b48e66db9494fbb725
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/fb.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29
30 #include <mach/hardware.h>
31 #include <mach/ipu.h>
32 #include <mach/mx3fb.h>
33
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36
37 #define MX3FB_NAME "mx3_sdc_fb"
38
39 #define MX3FB_REG_OFFSET 0xB4
40
41 /* SDC Registers */
42 #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
43 #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
44 #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
45 #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
46 #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
47 #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
48 #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
49 #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
50 #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
51 #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
53
54 /* Register bits */
55 #define SDC_COM_TFT_COLOR 0x00000001UL
56 #define SDC_COM_FG_EN 0x00000010UL
57 #define SDC_COM_GWSEL 0x00000020UL
58 #define SDC_COM_GLB_A 0x00000040UL
59 #define SDC_COM_KEY_COLOR_G 0x00000080UL
60 #define SDC_COM_BG_EN 0x00000200UL
61 #define SDC_COM_SHARP 0x00001000UL
62
63 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
64
65 /* Display Interface registers */
66 #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
67 #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
68 #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
70 #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
71 #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
74 #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
77 #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
80 #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
81 #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
87 #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
90 #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
93 #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
99 #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
102 #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
103 #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
105
106 /* DI_DISP_SIG_POL bits */
107 #define DI_D3_VSYNC_POL_SHIFT 28
108 #define DI_D3_HSYNC_POL_SHIFT 27
109 #define DI_D3_DRDY_SHARP_POL_SHIFT 26
110 #define DI_D3_CLK_POL_SHIFT 25
111 #define DI_D3_DATA_POL_SHIFT 24
112
113 /* DI_DISP_IF_CONF bits */
114 #define DI_D3_CLK_IDLE_SHIFT 26
115 #define DI_D3_CLK_SEL_SHIFT 25
116 #define DI_D3_DATAMSK_SHIFT 24
117
118 enum ipu_panel {
119 IPU_PANEL_SHARP_TFT,
120 IPU_PANEL_TFT,
121 };
122
123 struct ipu_di_signal_cfg {
124 unsigned datamask_en:1;
125 unsigned clksel_en:1;
126 unsigned clkidle_en:1;
127 unsigned data_pol:1; /* true = inverted */
128 unsigned clk_pol:1; /* true = rising edge */
129 unsigned enable_pol:1;
130 unsigned Hsync_pol:1; /* true = active high */
131 unsigned Vsync_pol:1;
132 };
133
134 static const struct fb_videomode mx3fb_modedb[] = {
135 {
136 /* 240x320 @ 60 Hz */
137 .name = "Sharp-QVGA",
138 .refresh = 60,
139 .xres = 240,
140 .yres = 320,
141 .pixclock = 185925,
142 .left_margin = 9,
143 .right_margin = 16,
144 .upper_margin = 7,
145 .lower_margin = 9,
146 .hsync_len = 1,
147 .vsync_len = 1,
148 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
149 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
150 FB_SYNC_CLK_IDLE_EN,
151 .vmode = FB_VMODE_NONINTERLACED,
152 .flag = 0,
153 }, {
154 /* 240x33 @ 60 Hz */
155 .name = "Sharp-CLI",
156 .refresh = 60,
157 .xres = 240,
158 .yres = 33,
159 .pixclock = 185925,
160 .left_margin = 9,
161 .right_margin = 16,
162 .upper_margin = 7,
163 .lower_margin = 9 + 287,
164 .hsync_len = 1,
165 .vsync_len = 1,
166 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
167 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
168 FB_SYNC_CLK_IDLE_EN,
169 .vmode = FB_VMODE_NONINTERLACED,
170 .flag = 0,
171 }, {
172 /* 640x480 @ 60 Hz */
173 .name = "NEC-VGA",
174 .refresh = 60,
175 .xres = 640,
176 .yres = 480,
177 .pixclock = 38255,
178 .left_margin = 144,
179 .right_margin = 0,
180 .upper_margin = 34,
181 .lower_margin = 40,
182 .hsync_len = 1,
183 .vsync_len = 1,
184 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
185 .vmode = FB_VMODE_NONINTERLACED,
186 .flag = 0,
187 }, {
188 /* NTSC TV output */
189 .name = "TV-NTSC",
190 .refresh = 60,
191 .xres = 640,
192 .yres = 480,
193 .pixclock = 37538,
194 .left_margin = 38,
195 .right_margin = 858 - 640 - 38 - 3,
196 .upper_margin = 36,
197 .lower_margin = 518 - 480 - 36 - 1,
198 .hsync_len = 3,
199 .vsync_len = 1,
200 .sync = 0,
201 .vmode = FB_VMODE_NONINTERLACED,
202 .flag = 0,
203 }, {
204 /* PAL TV output */
205 .name = "TV-PAL",
206 .refresh = 50,
207 .xres = 640,
208 .yres = 480,
209 .pixclock = 37538,
210 .left_margin = 38,
211 .right_margin = 960 - 640 - 38 - 32,
212 .upper_margin = 32,
213 .lower_margin = 555 - 480 - 32 - 3,
214 .hsync_len = 32,
215 .vsync_len = 3,
216 .sync = 0,
217 .vmode = FB_VMODE_NONINTERLACED,
218 .flag = 0,
219 }, {
220 /* TV output VGA mode, 640x480 @ 65 Hz */
221 .name = "TV-VGA",
222 .refresh = 60,
223 .xres = 640,
224 .yres = 480,
225 .pixclock = 40574,
226 .left_margin = 35,
227 .right_margin = 45,
228 .upper_margin = 9,
229 .lower_margin = 1,
230 .hsync_len = 46,
231 .vsync_len = 5,
232 .sync = 0,
233 .vmode = FB_VMODE_NONINTERLACED,
234 .flag = 0,
235 },
236 };
237
238 struct mx3fb_data {
239 struct fb_info *fbi;
240 int backlight_level;
241 void __iomem *reg_base;
242 spinlock_t lock;
243 struct device *dev;
244
245 uint32_t h_start_width;
246 uint32_t v_start_width;
247 };
248
249 struct dma_chan_request {
250 struct mx3fb_data *mx3fb;
251 enum ipu_channel id;
252 };
253
254 /* MX3 specific framebuffer information. */
255 struct mx3fb_info {
256 int blank;
257 enum ipu_channel ipu_ch;
258 uint32_t cur_ipu_buf;
259
260 u32 pseudo_palette[16];
261
262 struct completion flip_cmpl;
263 struct mutex mutex; /* Protects fb-ops */
264 struct mx3fb_data *mx3fb;
265 struct idmac_channel *idmac_channel;
266 struct dma_async_tx_descriptor *txd;
267 dma_cookie_t cookie;
268 struct scatterlist sg[2];
269
270 u32 sync; /* preserve var->sync flags */
271 };
272
273 static void mx3fb_dma_done(void *);
274
275 /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
276 static const char *fb_mode;
277 static unsigned long default_bpp = 16;
278
279 static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
280 {
281 return __raw_readl(mx3fb->reg_base + reg);
282 }
283
284 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
285 {
286 __raw_writel(value, mx3fb->reg_base + reg);
287 }
288
289 static const uint32_t di_mappings[] = {
290 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
291 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
292 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
293 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
294 };
295
296 static void sdc_fb_init(struct mx3fb_info *fbi)
297 {
298 struct mx3fb_data *mx3fb = fbi->mx3fb;
299 uint32_t reg;
300
301 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
302
303 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
304 }
305
306 /* Returns enabled flag before uninit */
307 static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
308 {
309 struct mx3fb_data *mx3fb = fbi->mx3fb;
310 uint32_t reg;
311
312 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
313
314 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
315
316 return reg & SDC_COM_BG_EN;
317 }
318
319 static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
320 {
321 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
322 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
323 struct dma_chan *dma_chan = &ichan->dma_chan;
324 unsigned long flags;
325 dma_cookie_t cookie;
326
327 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
328 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
329
330 /* This enables the channel */
331 if (mx3_fbi->cookie < 0) {
332 mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
333 &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
334 if (!mx3_fbi->txd) {
335 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
336 dma_chan->chan_id);
337 return;
338 }
339
340 mx3_fbi->txd->callback_param = mx3_fbi->txd;
341 mx3_fbi->txd->callback = mx3fb_dma_done;
342
343 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
344 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
345 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
346 } else {
347 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
348 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
349 dma_chan->chan_id);
350 return;
351 }
352
353 /* Just re-activate the same buffer */
354 dma_async_issue_pending(dma_chan);
355 cookie = mx3_fbi->cookie;
356 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
357 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
358 }
359
360 if (cookie >= 0) {
361 spin_lock_irqsave(&mx3fb->lock, flags);
362 sdc_fb_init(mx3_fbi);
363 mx3_fbi->cookie = cookie;
364 spin_unlock_irqrestore(&mx3fb->lock, flags);
365 }
366
367 /*
368 * Attention! Without this msleep the channel keeps generating
369 * interrupts. Next sdc_set_brightness() is going to be called
370 * from mx3fb_blank().
371 */
372 msleep(2);
373 }
374
375 static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
376 {
377 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
378 uint32_t enabled;
379 unsigned long flags;
380
381 spin_lock_irqsave(&mx3fb->lock, flags);
382
383 enabled = sdc_fb_uninit(mx3_fbi);
384
385 spin_unlock_irqrestore(&mx3fb->lock, flags);
386
387 mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan);
388 mx3_fbi->txd = NULL;
389 mx3_fbi->cookie = -EINVAL;
390 }
391
392 /**
393 * sdc_set_window_pos() - set window position of the respective plane.
394 * @mx3fb: mx3fb context.
395 * @channel: IPU DMAC channel ID.
396 * @x_pos: X coordinate relative to the top left corner to place window at.
397 * @y_pos: Y coordinate relative to the top left corner to place window at.
398 * @return: 0 on success or negative error code on failure.
399 */
400 static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
401 int16_t x_pos, int16_t y_pos)
402 {
403 if (channel != IDMAC_SDC_0)
404 return -EINVAL;
405
406 x_pos += mx3fb->h_start_width;
407 y_pos += mx3fb->v_start_width;
408
409 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
410 return 0;
411 }
412
413 /**
414 * sdc_init_panel() - initialize a synchronous LCD panel.
415 * @mx3fb: mx3fb context.
416 * @panel: panel type.
417 * @pixel_clk: desired pixel clock frequency in Hz.
418 * @width: width of panel in pixels.
419 * @height: height of panel in pixels.
420 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
421 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
422 * and the start of valid data.
423 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
424 * @h_end_width: number of pixel clocks between the end of valid data
425 * and the HSYNC signal for next line.
426 * @v_start_width: number of lines between the VSYNC signal pulse and the
427 * start of valid data.
428 * @v_sync_width: width of the VSYNC signal in units of lines
429 * @v_end_width: number of lines between the end of valid data and the
430 * VSYNC signal for next frame.
431 * @sig: bitfield of signal polarities for LCD interface.
432 * @return: 0 on success or negative error code on failure.
433 */
434 static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
435 uint32_t pixel_clk,
436 uint16_t width, uint16_t height,
437 enum pixel_fmt pixel_fmt,
438 uint16_t h_start_width, uint16_t h_sync_width,
439 uint16_t h_end_width, uint16_t v_start_width,
440 uint16_t v_sync_width, uint16_t v_end_width,
441 struct ipu_di_signal_cfg sig)
442 {
443 unsigned long lock_flags;
444 uint32_t reg;
445 uint32_t old_conf;
446 uint32_t div;
447 struct clk *ipu_clk;
448
449 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
450
451 if (v_sync_width == 0 || h_sync_width == 0)
452 return -EINVAL;
453
454 /* Init panel size and blanking periods */
455 reg = ((uint32_t) (h_sync_width - 1) << 26) |
456 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
457 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
458
459 #ifdef DEBUG
460 printk(KERN_CONT " hor_conf %x,", reg);
461 #endif
462
463 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
464 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
465 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
466
467 #ifdef DEBUG
468 printk(KERN_CONT " ver_conf %x\n", reg);
469 #endif
470
471 mx3fb->h_start_width = h_start_width;
472 mx3fb->v_start_width = v_start_width;
473
474 switch (panel) {
475 case IPU_PANEL_SHARP_TFT:
476 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
477 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
478 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
479 break;
480 case IPU_PANEL_TFT:
481 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
482 break;
483 default:
484 return -EINVAL;
485 }
486
487 /* Init clocking */
488
489 /*
490 * Calculate divider: fractional part is 4 bits so simply multiple by
491 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
492 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
493 */
494 ipu_clk = clk_get(mx3fb->dev, NULL);
495 if (!IS_ERR(ipu_clk)) {
496 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
497 clk_put(ipu_clk);
498 } else {
499 div = 0;
500 }
501
502 if (div < 0x40) { /* Divider less than 4 */
503 dev_dbg(mx3fb->dev,
504 "InitPanel() - Pixel clock divider less than 4\n");
505 div = 0x40;
506 }
507
508 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
509 pixel_clk, div >> 4, (div & 7) * 125);
510
511 spin_lock_irqsave(&mx3fb->lock, lock_flags);
512
513 /*
514 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
515 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
516 * debug. DISP3_IF_CLK_UP_WR is 0
517 */
518 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
519
520 /* DI settings */
521 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
522 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
523 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
524 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
525 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
526
527 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
528 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
529 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
530 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
531 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
532 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
533 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
534
535 switch (pixel_fmt) {
536 case IPU_PIX_FMT_RGB24:
537 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
538 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
539 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
540 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
541 ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
542 break;
543 case IPU_PIX_FMT_RGB666:
544 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
545 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
546 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
547 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
548 ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
549 break;
550 case IPU_PIX_FMT_BGR666:
551 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
552 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
553 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
554 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
555 ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
556 break;
557 default:
558 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
559 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
560 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
561 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
562 ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
563 break;
564 }
565
566 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
567
568 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
569 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
570 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
571 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
572 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
573 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
574
575 return 0;
576 }
577
578 /**
579 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
580 * @mx3fb: mx3fb context.
581 * @channel: IPU DMAC channel ID.
582 * @enable: boolean to enable or disable color keyl.
583 * @color_key: 24-bit RGB color to use as transparent color key.
584 * @return: 0 on success or negative error code on failure.
585 */
586 static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
587 bool enable, uint32_t color_key)
588 {
589 uint32_t reg, sdc_conf;
590 unsigned long lock_flags;
591
592 spin_lock_irqsave(&mx3fb->lock, lock_flags);
593
594 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
595 if (channel == IDMAC_SDC_0)
596 sdc_conf &= ~SDC_COM_GWSEL;
597 else
598 sdc_conf |= SDC_COM_GWSEL;
599
600 if (enable) {
601 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
602 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
603 SDC_GW_CTRL);
604
605 sdc_conf |= SDC_COM_KEY_COLOR_G;
606 } else {
607 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
608 }
609 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
610
611 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
612
613 return 0;
614 }
615
616 /**
617 * sdc_set_global_alpha() - set global alpha blending modes.
618 * @mx3fb: mx3fb context.
619 * @enable: boolean to enable or disable global alpha blending. If disabled,
620 * per pixel blending is used.
621 * @alpha: global alpha value.
622 * @return: 0 on success or negative error code on failure.
623 */
624 static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
625 {
626 uint32_t reg;
627 unsigned long lock_flags;
628
629 spin_lock_irqsave(&mx3fb->lock, lock_flags);
630
631 if (enable) {
632 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
633 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
634
635 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
636 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
637 } else {
638 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
639 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
640 }
641
642 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
643
644 return 0;
645 }
646
647 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
648 {
649 /* This might be board-specific */
650 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
651 return;
652 }
653
654 static uint32_t bpp_to_pixfmt(int bpp)
655 {
656 uint32_t pixfmt = 0;
657 switch (bpp) {
658 case 24:
659 pixfmt = IPU_PIX_FMT_BGR24;
660 break;
661 case 32:
662 pixfmt = IPU_PIX_FMT_BGR32;
663 break;
664 case 16:
665 pixfmt = IPU_PIX_FMT_RGB565;
666 break;
667 }
668 return pixfmt;
669 }
670
671 static int mx3fb_blank(int blank, struct fb_info *fbi);
672 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
673 bool lock);
674 static int mx3fb_unmap_video_memory(struct fb_info *fbi);
675
676 /**
677 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
678 * @info: framebuffer information pointer
679 * @return: 0 on success or negative error code on failure.
680 */
681 static int mx3fb_set_fix(struct fb_info *fbi)
682 {
683 struct fb_fix_screeninfo *fix = &fbi->fix;
684 struct fb_var_screeninfo *var = &fbi->var;
685
686 strncpy(fix->id, "DISP3 BG", 8);
687
688 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
689
690 fix->type = FB_TYPE_PACKED_PIXELS;
691 fix->accel = FB_ACCEL_NONE;
692 fix->visual = FB_VISUAL_TRUECOLOR;
693 fix->xpanstep = 1;
694 fix->ypanstep = 1;
695
696 return 0;
697 }
698
699 static void mx3fb_dma_done(void *arg)
700 {
701 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
702 struct dma_chan *chan = tx_desc->txd.chan;
703 struct idmac_channel *ichannel = to_idmac_chan(chan);
704 struct mx3fb_data *mx3fb = ichannel->client;
705 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
706
707 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
708
709 /* We only need one interrupt, it will be re-enabled as needed */
710 disable_irq_nosync(ichannel->eof_irq);
711
712 complete(&mx3_fbi->flip_cmpl);
713 }
714
715 static int __set_par(struct fb_info *fbi, bool lock)
716 {
717 u32 mem_len;
718 struct ipu_di_signal_cfg sig_cfg;
719 enum ipu_panel mode = IPU_PANEL_TFT;
720 struct mx3fb_info *mx3_fbi = fbi->par;
721 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
722 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
723 struct idmac_video_param *video = &ichan->params.video;
724 struct scatterlist *sg = mx3_fbi->sg;
725
726 /* Total cleanup */
727 if (mx3_fbi->txd)
728 sdc_disable_channel(mx3_fbi);
729
730 mx3fb_set_fix(fbi);
731
732 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
733 if (mem_len > fbi->fix.smem_len) {
734 if (fbi->fix.smem_start)
735 mx3fb_unmap_video_memory(fbi);
736
737 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
738 return -ENOMEM;
739 }
740
741 sg_init_table(&sg[0], 1);
742 sg_init_table(&sg[1], 1);
743
744 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
745 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
746 fbi->fix.smem_len,
747 offset_in_page(fbi->screen_base));
748
749 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
750 memset(&sig_cfg, 0, sizeof(sig_cfg));
751 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
752 sig_cfg.Hsync_pol = true;
753 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
754 sig_cfg.Vsync_pol = true;
755 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
756 sig_cfg.clk_pol = true;
757 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
758 sig_cfg.data_pol = true;
759 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
760 sig_cfg.enable_pol = true;
761 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
762 sig_cfg.clkidle_en = true;
763 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
764 sig_cfg.clksel_en = true;
765 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
766 mode = IPU_PANEL_SHARP_TFT;
767
768 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
769 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
770
771 if (sdc_init_panel(mx3fb, mode,
772 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
773 fbi->var.xres, fbi->var.yres,
774 (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
775 IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
776 fbi->var.left_margin,
777 fbi->var.hsync_len,
778 fbi->var.right_margin +
779 fbi->var.hsync_len,
780 fbi->var.upper_margin,
781 fbi->var.vsync_len,
782 fbi->var.lower_margin +
783 fbi->var.vsync_len, sig_cfg) != 0) {
784 dev_err(fbi->device,
785 "mx3fb: Error initializing panel.\n");
786 return -EINVAL;
787 }
788 }
789
790 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
791
792 mx3_fbi->cur_ipu_buf = 0;
793
794 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
795 video->out_width = fbi->var.xres;
796 video->out_height = fbi->var.yres;
797 video->out_stride = fbi->var.xres_virtual;
798
799 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
800 sdc_enable_channel(mx3_fbi);
801
802 return 0;
803 }
804
805 /**
806 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
807 * @fbi: framebuffer information pointer.
808 * @return: 0 on success or negative error code on failure.
809 */
810 static int mx3fb_set_par(struct fb_info *fbi)
811 {
812 struct mx3fb_info *mx3_fbi = fbi->par;
813 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
814 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
815 int ret;
816
817 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
818
819 mutex_lock(&mx3_fbi->mutex);
820
821 ret = __set_par(fbi, true);
822
823 mutex_unlock(&mx3_fbi->mutex);
824
825 return ret;
826 }
827
828 /**
829 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
830 * @var: framebuffer variable parameters
831 * @fbi: framebuffer information pointer
832 */
833 static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
834 {
835 struct mx3fb_info *mx3_fbi = fbi->par;
836 u32 vtotal;
837 u32 htotal;
838
839 dev_dbg(fbi->device, "%s\n", __func__);
840
841 if (var->xres_virtual < var->xres)
842 var->xres_virtual = var->xres;
843 if (var->yres_virtual < var->yres)
844 var->yres_virtual = var->yres;
845
846 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
847 (var->bits_per_pixel != 16))
848 var->bits_per_pixel = default_bpp;
849
850 switch (var->bits_per_pixel) {
851 case 16:
852 var->red.length = 5;
853 var->red.offset = 11;
854 var->red.msb_right = 0;
855
856 var->green.length = 6;
857 var->green.offset = 5;
858 var->green.msb_right = 0;
859
860 var->blue.length = 5;
861 var->blue.offset = 0;
862 var->blue.msb_right = 0;
863
864 var->transp.length = 0;
865 var->transp.offset = 0;
866 var->transp.msb_right = 0;
867 break;
868 case 24:
869 var->red.length = 8;
870 var->red.offset = 16;
871 var->red.msb_right = 0;
872
873 var->green.length = 8;
874 var->green.offset = 8;
875 var->green.msb_right = 0;
876
877 var->blue.length = 8;
878 var->blue.offset = 0;
879 var->blue.msb_right = 0;
880
881 var->transp.length = 0;
882 var->transp.offset = 0;
883 var->transp.msb_right = 0;
884 break;
885 case 32:
886 var->red.length = 8;
887 var->red.offset = 16;
888 var->red.msb_right = 0;
889
890 var->green.length = 8;
891 var->green.offset = 8;
892 var->green.msb_right = 0;
893
894 var->blue.length = 8;
895 var->blue.offset = 0;
896 var->blue.msb_right = 0;
897
898 var->transp.length = 8;
899 var->transp.offset = 24;
900 var->transp.msb_right = 0;
901 break;
902 }
903
904 if (var->pixclock < 1000) {
905 htotal = var->xres + var->right_margin + var->hsync_len +
906 var->left_margin;
907 vtotal = var->yres + var->lower_margin + var->vsync_len +
908 var->upper_margin;
909 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
910 var->pixclock = KHZ2PICOS(var->pixclock);
911 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
912 var->pixclock);
913 }
914
915 var->height = -1;
916 var->width = -1;
917 var->grayscale = 0;
918
919 /* Preserve sync flags */
920 var->sync |= mx3_fbi->sync;
921 mx3_fbi->sync |= var->sync;
922
923 return 0;
924 }
925
926 static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
927 {
928 chan &= 0xffff;
929 chan >>= 16 - bf->length;
930 return chan << bf->offset;
931 }
932
933 static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
934 unsigned int green, unsigned int blue,
935 unsigned int trans, struct fb_info *fbi)
936 {
937 struct mx3fb_info *mx3_fbi = fbi->par;
938 u32 val;
939 int ret = 1;
940
941 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
942
943 mutex_lock(&mx3_fbi->mutex);
944 /*
945 * If greyscale is true, then we convert the RGB value
946 * to greyscale no matter what visual we are using.
947 */
948 if (fbi->var.grayscale)
949 red = green = blue = (19595 * red + 38470 * green +
950 7471 * blue) >> 16;
951 switch (fbi->fix.visual) {
952 case FB_VISUAL_TRUECOLOR:
953 /*
954 * 16-bit True Colour. We encode the RGB value
955 * according to the RGB bitfield information.
956 */
957 if (regno < 16) {
958 u32 *pal = fbi->pseudo_palette;
959
960 val = chan_to_field(red, &fbi->var.red);
961 val |= chan_to_field(green, &fbi->var.green);
962 val |= chan_to_field(blue, &fbi->var.blue);
963
964 pal[regno] = val;
965
966 ret = 0;
967 }
968 break;
969
970 case FB_VISUAL_STATIC_PSEUDOCOLOR:
971 case FB_VISUAL_PSEUDOCOLOR:
972 break;
973 }
974 mutex_unlock(&mx3_fbi->mutex);
975
976 return ret;
977 }
978
979 static void __blank(int blank, struct fb_info *fbi)
980 {
981 struct mx3fb_info *mx3_fbi = fbi->par;
982 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
983
984 mx3_fbi->blank = blank;
985
986 switch (blank) {
987 case FB_BLANK_POWERDOWN:
988 case FB_BLANK_VSYNC_SUSPEND:
989 case FB_BLANK_HSYNC_SUSPEND:
990 case FB_BLANK_NORMAL:
991 sdc_set_brightness(mx3fb, 0);
992 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
993 /* Give LCD time to update - enough for 50 and 60 Hz */
994 msleep(25);
995 sdc_disable_channel(mx3_fbi);
996 break;
997 case FB_BLANK_UNBLANK:
998 sdc_enable_channel(mx3_fbi);
999 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1000 break;
1001 }
1002 }
1003
1004 /**
1005 * mx3fb_blank() - blank the display.
1006 */
1007 static int mx3fb_blank(int blank, struct fb_info *fbi)
1008 {
1009 struct mx3fb_info *mx3_fbi = fbi->par;
1010
1011 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1012 blank, fbi->screen_base, fbi->fix.smem_len);
1013
1014 if (mx3_fbi->blank == blank)
1015 return 0;
1016
1017 mutex_lock(&mx3_fbi->mutex);
1018 __blank(blank, fbi);
1019 mutex_unlock(&mx3_fbi->mutex);
1020
1021 return 0;
1022 }
1023
1024 /**
1025 * mx3fb_pan_display() - pan or wrap the display
1026 * @var: variable screen buffer information.
1027 * @info: framebuffer information pointer.
1028 *
1029 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1030 */
1031 static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1032 struct fb_info *fbi)
1033 {
1034 struct mx3fb_info *mx3_fbi = fbi->par;
1035 u32 y_bottom;
1036 unsigned long base;
1037 off_t offset;
1038 dma_cookie_t cookie;
1039 struct scatterlist *sg = mx3_fbi->sg;
1040 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1041 struct dma_async_tx_descriptor *txd;
1042 int ret;
1043
1044 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1045 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1046
1047 if (var->xoffset > 0) {
1048 dev_dbg(fbi->device, "x panning not supported\n");
1049 return -EINVAL;
1050 }
1051
1052 if (fbi->var.xoffset == var->xoffset &&
1053 fbi->var.yoffset == var->yoffset)
1054 return 0; /* No change, do nothing */
1055
1056 y_bottom = var->yoffset;
1057
1058 if (!(var->vmode & FB_VMODE_YWRAP))
1059 y_bottom += var->yres;
1060
1061 if (y_bottom > fbi->var.yres_virtual)
1062 return -EINVAL;
1063
1064 mutex_lock(&mx3_fbi->mutex);
1065
1066 offset = (var->yoffset * var->xres_virtual + var->xoffset) *
1067 (var->bits_per_pixel / 8);
1068 base = fbi->fix.smem_start + offset;
1069
1070 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1071 mx3_fbi->cur_ipu_buf, base);
1072
1073 /*
1074 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1075 * which we will need for the next device_prep_slave_sg(). The
1076 * IRQ-handler will disable the IRQ again.
1077 */
1078 init_completion(&mx3_fbi->flip_cmpl);
1079 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1080
1081 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1082 if (ret <= 0) {
1083 mutex_unlock(&mx3_fbi->mutex);
1084 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1085 "user interrupt" : "timeout");
1086 disable_irq(mx3_fbi->idmac_channel->eof_irq);
1087 return ret ? : -ETIMEDOUT;
1088 }
1089
1090 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1091
1092 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1093 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1094 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1095 offset_in_page(fbi->screen_base + offset));
1096
1097 if (mx3_fbi->txd)
1098 async_tx_ack(mx3_fbi->txd);
1099
1100 txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1101 mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
1102 if (!txd) {
1103 dev_err(fbi->device,
1104 "Error preparing a DMA transaction descriptor.\n");
1105 mutex_unlock(&mx3_fbi->mutex);
1106 return -EIO;
1107 }
1108
1109 txd->callback_param = txd;
1110 txd->callback = mx3fb_dma_done;
1111
1112 /*
1113 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1114 * should switch to another buffer
1115 */
1116 cookie = txd->tx_submit(txd);
1117 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1118 if (cookie < 0) {
1119 dev_err(fbi->device,
1120 "Error updating SDC buf %d to address=0x%08lX\n",
1121 mx3_fbi->cur_ipu_buf, base);
1122 mutex_unlock(&mx3_fbi->mutex);
1123 return -EIO;
1124 }
1125
1126 mx3_fbi->txd = txd;
1127
1128 fbi->var.xoffset = var->xoffset;
1129 fbi->var.yoffset = var->yoffset;
1130
1131 if (var->vmode & FB_VMODE_YWRAP)
1132 fbi->var.vmode |= FB_VMODE_YWRAP;
1133 else
1134 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1135
1136 mutex_unlock(&mx3_fbi->mutex);
1137
1138 dev_dbg(fbi->device, "Update complete\n");
1139
1140 return 0;
1141 }
1142
1143 /*
1144 * This structure contains the pointers to the control functions that are
1145 * invoked by the core framebuffer driver to perform operations like
1146 * blitting, rectangle filling, copy regions and cursor definition.
1147 */
1148 static struct fb_ops mx3fb_ops = {
1149 .owner = THIS_MODULE,
1150 .fb_set_par = mx3fb_set_par,
1151 .fb_check_var = mx3fb_check_var,
1152 .fb_setcolreg = mx3fb_setcolreg,
1153 .fb_pan_display = mx3fb_pan_display,
1154 .fb_fillrect = cfb_fillrect,
1155 .fb_copyarea = cfb_copyarea,
1156 .fb_imageblit = cfb_imageblit,
1157 .fb_blank = mx3fb_blank,
1158 };
1159
1160 #ifdef CONFIG_PM
1161 /*
1162 * Power management hooks. Note that we won't be called from IRQ context,
1163 * unlike the blank functions above, so we may sleep.
1164 */
1165
1166 /*
1167 * Suspends the framebuffer and blanks the screen. Power management support
1168 */
1169 static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1170 {
1171 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1172 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1173
1174 acquire_console_sem();
1175 fb_set_suspend(mx3fb->fbi, 1);
1176 release_console_sem();
1177
1178 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1179 sdc_disable_channel(mx3_fbi);
1180 sdc_set_brightness(mx3fb, 0);
1181
1182 }
1183 return 0;
1184 }
1185
1186 /*
1187 * Resumes the framebuffer and unblanks the screen. Power management support
1188 */
1189 static int mx3fb_resume(struct platform_device *pdev)
1190 {
1191 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1192 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1193
1194 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1195 sdc_enable_channel(mx3_fbi);
1196 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1197 }
1198
1199 acquire_console_sem();
1200 fb_set_suspend(mx3fb->fbi, 0);
1201 release_console_sem();
1202
1203 return 0;
1204 }
1205 #else
1206 #define mx3fb_suspend NULL
1207 #define mx3fb_resume NULL
1208 #endif
1209
1210 /*
1211 * Main framebuffer functions
1212 */
1213
1214 /**
1215 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1216 * @fbi: framebuffer information pointer
1217 * @mem_len: length of mapped memory
1218 * @lock: do not lock during initialisation
1219 * @return: Error code indicating success or failure
1220 *
1221 * This buffer is remapped into a non-cached, non-buffered, memory region to
1222 * allow palette and pixel writes to occur without flushing the cache. Once this
1223 * area is remapped, all virtual memory access to the video memory should occur
1224 * at the new region.
1225 */
1226 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1227 bool lock)
1228 {
1229 int retval = 0;
1230 dma_addr_t addr;
1231
1232 fbi->screen_base = dma_alloc_writecombine(fbi->device,
1233 mem_len,
1234 &addr, GFP_DMA);
1235
1236 if (!fbi->screen_base) {
1237 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1238 mem_len);
1239 retval = -EBUSY;
1240 goto err0;
1241 }
1242
1243 if (lock)
1244 mutex_lock(&fbi->mm_lock);
1245 fbi->fix.smem_start = addr;
1246 fbi->fix.smem_len = mem_len;
1247 if (lock)
1248 mutex_unlock(&fbi->mm_lock);
1249
1250 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1251 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1252
1253 fbi->screen_size = fbi->fix.smem_len;
1254
1255 /* Clear the screen */
1256 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1257
1258 return 0;
1259
1260 err0:
1261 fbi->fix.smem_len = 0;
1262 fbi->fix.smem_start = 0;
1263 fbi->screen_base = NULL;
1264 return retval;
1265 }
1266
1267 /**
1268 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1269 * @fbi: framebuffer information pointer
1270 * @return: error code indicating success or failure
1271 */
1272 static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1273 {
1274 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1275 fbi->screen_base, fbi->fix.smem_start);
1276
1277 fbi->screen_base = 0;
1278 mutex_lock(&fbi->mm_lock);
1279 fbi->fix.smem_start = 0;
1280 fbi->fix.smem_len = 0;
1281 mutex_unlock(&fbi->mm_lock);
1282 return 0;
1283 }
1284
1285 /**
1286 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1287 * @return: initialized framebuffer structure.
1288 */
1289 static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1290 {
1291 struct fb_info *fbi;
1292 struct mx3fb_info *mx3fbi;
1293 int ret;
1294
1295 /* Allocate sufficient memory for the fb structure */
1296 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1297 if (!fbi)
1298 return NULL;
1299
1300 mx3fbi = fbi->par;
1301 mx3fbi->cookie = -EINVAL;
1302 mx3fbi->cur_ipu_buf = 0;
1303
1304 fbi->var.activate = FB_ACTIVATE_NOW;
1305
1306 fbi->fbops = ops;
1307 fbi->flags = FBINFO_FLAG_DEFAULT;
1308 fbi->pseudo_palette = mx3fbi->pseudo_palette;
1309
1310 mutex_init(&mx3fbi->mutex);
1311
1312 /* Allocate colormap */
1313 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1314 if (ret < 0) {
1315 framebuffer_release(fbi);
1316 return NULL;
1317 }
1318
1319 return fbi;
1320 }
1321
1322 static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1323 {
1324 struct device *dev = mx3fb->dev;
1325 struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1326 const char *name = mx3fb_pdata->name;
1327 unsigned int irq;
1328 struct fb_info *fbi;
1329 struct mx3fb_info *mx3fbi;
1330 const struct fb_videomode *mode;
1331 int ret, num_modes;
1332
1333 ichan->client = mx3fb;
1334 irq = ichan->eof_irq;
1335
1336 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1337 return -EINVAL;
1338
1339 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1340 if (!fbi)
1341 return -ENOMEM;
1342
1343 if (!fb_mode)
1344 fb_mode = name;
1345
1346 if (!fb_mode) {
1347 ret = -EINVAL;
1348 goto emode;
1349 }
1350
1351 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1352 mode = mx3fb_pdata->mode;
1353 num_modes = mx3fb_pdata->num_modes;
1354 } else {
1355 mode = mx3fb_modedb;
1356 num_modes = ARRAY_SIZE(mx3fb_modedb);
1357 }
1358
1359 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1360 num_modes, NULL, default_bpp)) {
1361 ret = -EBUSY;
1362 goto emode;
1363 }
1364
1365 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1366
1367 /* Default Y virtual size is 2x panel size */
1368 fbi->var.yres_virtual = fbi->var.yres * 2;
1369
1370 mx3fb->fbi = fbi;
1371
1372 /* set Display Interface clock period */
1373 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1374 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1375
1376 sdc_set_brightness(mx3fb, 255);
1377 sdc_set_global_alpha(mx3fb, true, 0xFF);
1378 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1379
1380 mx3fbi = fbi->par;
1381 mx3fbi->idmac_channel = ichan;
1382 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1383 mx3fbi->mx3fb = mx3fb;
1384 mx3fbi->blank = FB_BLANK_NORMAL;
1385
1386 init_completion(&mx3fbi->flip_cmpl);
1387 disable_irq(ichan->eof_irq);
1388 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1389 ret = __set_par(fbi, false);
1390 if (ret < 0)
1391 goto esetpar;
1392
1393 __blank(FB_BLANK_UNBLANK, fbi);
1394
1395 dev_info(dev, "registered, using mode %s\n", fb_mode);
1396
1397 ret = register_framebuffer(fbi);
1398 if (ret < 0)
1399 goto erfb;
1400
1401 return 0;
1402
1403 erfb:
1404 esetpar:
1405 emode:
1406 fb_dealloc_cmap(&fbi->cmap);
1407 framebuffer_release(fbi);
1408
1409 return ret;
1410 }
1411
1412 static bool chan_filter(struct dma_chan *chan, void *arg)
1413 {
1414 struct dma_chan_request *rq = arg;
1415 struct device *dev;
1416 struct mx3fb_platform_data *mx3fb_pdata;
1417
1418 if (!rq)
1419 return false;
1420
1421 dev = rq->mx3fb->dev;
1422 mx3fb_pdata = dev->platform_data;
1423
1424 return rq->id == chan->chan_id &&
1425 mx3fb_pdata->dma_dev == chan->device->dev;
1426 }
1427
1428 static void release_fbi(struct fb_info *fbi)
1429 {
1430 mx3fb_unmap_video_memory(fbi);
1431
1432 fb_dealloc_cmap(&fbi->cmap);
1433
1434 unregister_framebuffer(fbi);
1435 framebuffer_release(fbi);
1436 }
1437
1438 static int mx3fb_probe(struct platform_device *pdev)
1439 {
1440 struct device *dev = &pdev->dev;
1441 int ret;
1442 struct resource *sdc_reg;
1443 struct mx3fb_data *mx3fb;
1444 dma_cap_mask_t mask;
1445 struct dma_chan *chan;
1446 struct dma_chan_request rq;
1447
1448 /*
1449 * Display Interface (DI) and Synchronous Display Controller (SDC)
1450 * registers
1451 */
1452 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1453 if (!sdc_reg)
1454 return -EINVAL;
1455
1456 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1457 if (!mx3fb)
1458 return -ENOMEM;
1459
1460 spin_lock_init(&mx3fb->lock);
1461
1462 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1463 if (!mx3fb->reg_base) {
1464 ret = -ENOMEM;
1465 goto eremap;
1466 }
1467
1468 pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end,
1469 mx3fb->reg_base);
1470
1471 /* IDMAC interface */
1472 dmaengine_get();
1473
1474 mx3fb->dev = dev;
1475 platform_set_drvdata(pdev, mx3fb);
1476
1477 rq.mx3fb = mx3fb;
1478
1479 dma_cap_zero(mask);
1480 dma_cap_set(DMA_SLAVE, mask);
1481 dma_cap_set(DMA_PRIVATE, mask);
1482 rq.id = IDMAC_SDC_0;
1483 chan = dma_request_channel(mask, chan_filter, &rq);
1484 if (!chan) {
1485 ret = -EBUSY;
1486 goto ersdc0;
1487 }
1488
1489 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1490 if (ret < 0)
1491 goto eisdc0;
1492
1493 mx3fb->backlight_level = 255;
1494
1495 return 0;
1496
1497 eisdc0:
1498 dma_release_channel(chan);
1499 ersdc0:
1500 dmaengine_put();
1501 iounmap(mx3fb->reg_base);
1502 eremap:
1503 kfree(mx3fb);
1504 dev_err(dev, "mx3fb: failed to register fb\n");
1505 return ret;
1506 }
1507
1508 static int mx3fb_remove(struct platform_device *dev)
1509 {
1510 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1511 struct fb_info *fbi = mx3fb->fbi;
1512 struct mx3fb_info *mx3_fbi = fbi->par;
1513 struct dma_chan *chan;
1514
1515 chan = &mx3_fbi->idmac_channel->dma_chan;
1516 release_fbi(fbi);
1517
1518 dma_release_channel(chan);
1519 dmaengine_put();
1520
1521 iounmap(mx3fb->reg_base);
1522 kfree(mx3fb);
1523 return 0;
1524 }
1525
1526 static struct platform_driver mx3fb_driver = {
1527 .driver = {
1528 .name = MX3FB_NAME,
1529 },
1530 .probe = mx3fb_probe,
1531 .remove = mx3fb_remove,
1532 .suspend = mx3fb_suspend,
1533 .resume = mx3fb_resume,
1534 };
1535
1536 /*
1537 * Parse user specified options (`video=mx3fb:')
1538 * example:
1539 * video=mx3fb:bpp=16
1540 */
1541 static int __init mx3fb_setup(void)
1542 {
1543 #ifndef MODULE
1544 char *opt, *options = NULL;
1545
1546 if (fb_get_options("mx3fb", &options))
1547 return -ENODEV;
1548
1549 if (!options || !*options)
1550 return 0;
1551
1552 while ((opt = strsep(&options, ",")) != NULL) {
1553 if (!*opt)
1554 continue;
1555 if (!strncmp(opt, "bpp=", 4))
1556 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1557 else
1558 fb_mode = opt;
1559 }
1560 #endif
1561
1562 return 0;
1563 }
1564
1565 static int __init mx3fb_init(void)
1566 {
1567 int ret = mx3fb_setup();
1568
1569 if (ret < 0)
1570 return ret;
1571
1572 ret = platform_driver_register(&mx3fb_driver);
1573 return ret;
1574 }
1575
1576 static void __exit mx3fb_exit(void)
1577 {
1578 platform_driver_unregister(&mx3fb_driver);
1579 }
1580
1581 module_init(mx3fb_init);
1582 module_exit(mx3fb_exit);
1583
1584 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1585 MODULE_DESCRIPTION("MX3 framebuffer driver");
1586 MODULE_ALIAS("platform:" MX3FB_NAME);
1587 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support