ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / ctxgf104.c
blobc5a8d55e2cac0f47d509673e9cdcdfbf3eb88d7b
1 /*
2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
24 #include "ctxgf100.h"
26 /*******************************************************************************
27 * PGRAPH context register lists
28 ******************************************************************************/
30 const struct gf100_gr_init
31 gf104_grctx_init_tex_0[] = {
32 { 0x419a00, 1, 0x04, 0x000001f0 },
33 { 0x419a04, 1, 0x04, 0x00000001 },
34 { 0x419a08, 1, 0x04, 0x00000023 },
35 { 0x419a0c, 1, 0x04, 0x00020000 },
36 { 0x419a10, 1, 0x04, 0x00000000 },
37 { 0x419a14, 1, 0x04, 0x00000200 },
38 { 0x419a1c, 1, 0x04, 0x00000000 },
39 { 0x419a20, 1, 0x04, 0x00000800 },
40 { 0x419ac4, 1, 0x04, 0x0007f440 },
44 const struct gf100_gr_init
45 gf104_grctx_init_l1c_0[] = {
46 { 0x419cb0, 1, 0x04, 0x00020048 },
47 { 0x419ce8, 1, 0x04, 0x00000000 },
48 { 0x419cf4, 1, 0x04, 0x00000183 },
52 const struct gf100_gr_init
53 gf104_grctx_init_sm_0[] = {
54 { 0x419e04, 3, 0x04, 0x00000000 },
55 { 0x419e10, 1, 0x04, 0x00000002 },
56 { 0x419e44, 1, 0x04, 0x001beff2 },
57 { 0x419e48, 1, 0x04, 0x00000000 },
58 { 0x419e4c, 1, 0x04, 0x0000000f },
59 { 0x419e50, 17, 0x04, 0x00000000 },
60 { 0x419e98, 1, 0x04, 0x00000000 },
61 { 0x419ee0, 1, 0x04, 0x00011110 },
62 { 0x419f30, 11, 0x04, 0x00000000 },
66 static const struct gf100_gr_pack
67 gf104_grctx_pack_tpc[] = {
68 { gf100_grctx_init_pe_0 },
69 { gf104_grctx_init_tex_0 },
70 { gf100_grctx_init_wwdx_0 },
71 { gf100_grctx_init_mpc_0 },
72 { gf104_grctx_init_l1c_0 },
73 { gf100_grctx_init_tpccs_0 },
74 { gf104_grctx_init_sm_0 },
78 /*******************************************************************************
79 * PGRAPH context implementation
80 ******************************************************************************/
82 struct nvkm_oclass *
83 gf104_grctx_oclass = &(struct gf100_grctx_oclass) {
84 .base.handle = NV_ENGCTX(GR, 0xc3),
85 .base.ofuncs = &(struct nvkm_ofuncs) {
86 .ctor = gf100_gr_context_ctor,
87 .dtor = gf100_gr_context_dtor,
88 .init = _nvkm_gr_context_init,
89 .fini = _nvkm_gr_context_fini,
90 .rd32 = _nvkm_gr_context_rd32,
91 .wr32 = _nvkm_gr_context_wr32,
93 .main = gf100_grctx_generate_main,
94 .unkn = gf100_grctx_generate_unkn,
95 .hub = gf100_grctx_pack_hub,
96 .gpc = gf100_grctx_pack_gpc,
97 .zcull = gf100_grctx_pack_zcull,
98 .tpc = gf104_grctx_pack_tpc,
99 .icmd = gf100_grctx_pack_icmd,
100 .mthd = gf100_grctx_pack_mthd,
101 .bundle = gf100_grctx_generate_bundle,
102 .bundle_size = 0x1800,
103 .pagepool = gf100_grctx_generate_pagepool,
104 .pagepool_size = 0x8000,
105 .attrib = gf100_grctx_generate_attrib,
106 .attrib_nr_max = 0x324,
107 .attrib_nr = 0x218,
108 }.base;