ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / ctxgk110b.c
blobb11c26794fde814cb2af6c098d807cde53c41e46
1 /*
2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
24 #include "ctxgf100.h"
26 /*******************************************************************************
27 * PGRAPH context register lists
28 ******************************************************************************/
30 static const struct gf100_gr_init
31 gk110b_grctx_init_sm_0[] = {
32 { 0x419e04, 1, 0x04, 0x00000000 },
33 { 0x419e08, 1, 0x04, 0x0000001d },
34 { 0x419e0c, 1, 0x04, 0x00000000 },
35 { 0x419e10, 1, 0x04, 0x00001c02 },
36 { 0x419e44, 1, 0x04, 0x0013eff2 },
37 { 0x419e48, 1, 0x04, 0x00000000 },
38 { 0x419e4c, 1, 0x04, 0x0000007f },
39 { 0x419e50, 2, 0x04, 0x00000000 },
40 { 0x419e58, 1, 0x04, 0x00000001 },
41 { 0x419e5c, 3, 0x04, 0x00000000 },
42 { 0x419e68, 1, 0x04, 0x00000002 },
43 { 0x419e6c, 12, 0x04, 0x00000000 },
44 { 0x419eac, 1, 0x04, 0x00001f8f },
45 { 0x419eb0, 1, 0x04, 0x0db00d2f },
46 { 0x419eb8, 1, 0x04, 0x00000000 },
47 { 0x419ec8, 1, 0x04, 0x0001304f },
48 { 0x419f30, 4, 0x04, 0x00000000 },
49 { 0x419f40, 1, 0x04, 0x00000018 },
50 { 0x419f44, 3, 0x04, 0x00000000 },
51 { 0x419f58, 1, 0x04, 0x00000000 },
52 { 0x419f70, 1, 0x04, 0x00006300 },
53 { 0x419f78, 1, 0x04, 0x000000eb },
54 { 0x419f7c, 1, 0x04, 0x00000404 },
58 static const struct gf100_gr_pack
59 gk110b_grctx_pack_tpc[] = {
60 { gf117_grctx_init_pe_0 },
61 { gk110_grctx_init_tex_0 },
62 { gk110_grctx_init_mpc_0 },
63 { gk110_grctx_init_l1c_0 },
64 { gk110b_grctx_init_sm_0 },
68 /*******************************************************************************
69 * PGRAPH context implementation
70 ******************************************************************************/
72 struct nvkm_oclass *
73 gk110b_grctx_oclass = &(struct gf100_grctx_oclass) {
74 .base.handle = NV_ENGCTX(GR, 0xf1),
75 .base.ofuncs = &(struct nvkm_ofuncs) {
76 .ctor = gf100_gr_context_ctor,
77 .dtor = gf100_gr_context_dtor,
78 .init = _nvkm_gr_context_init,
79 .fini = _nvkm_gr_context_fini,
80 .rd32 = _nvkm_gr_context_rd32,
81 .wr32 = _nvkm_gr_context_wr32,
83 .main = gk104_grctx_generate_main,
84 .unkn = gk104_grctx_generate_unkn,
85 .hub = gk110_grctx_pack_hub,
86 .gpc = gk110_grctx_pack_gpc,
87 .zcull = gf100_grctx_pack_zcull,
88 .tpc = gk110b_grctx_pack_tpc,
89 .ppc = gk110_grctx_pack_ppc,
90 .icmd = gk110_grctx_pack_icmd,
91 .mthd = gk110_grctx_pack_mthd,
92 .bundle = gk104_grctx_generate_bundle,
93 .bundle_size = 0x3000,
94 .bundle_min_gpm_fifo_depth = 0x180,
95 .bundle_token_limit = 0x600,
96 .pagepool = gk104_grctx_generate_pagepool,
97 .pagepool_size = 0x8000,
98 .attrib = gf117_grctx_generate_attrib,
99 .attrib_nr_max = 0x324,
100 .attrib_nr = 0x218,
101 .alpha_nr_max = 0x7ff,
102 .alpha_nr = 0x648,
103 }.base;