drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #define gf110_pmu_code gk104_pmu_code
  25 #define gf110_pmu_data gk104_pmu_data
  26 #include "priv.h"
  27 #include "fuc/gf110.fuc4.h"
  28
  29 static void
  30 gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
  31 {
  32         nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
  33         nv_rd32(pmu, 0x000200);
  34         nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
  35         msleep(50);
  36
  37         nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
  38         nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
  39         nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
  40
  41         nv_mask(pmu, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
  42         msleep(50);
  43
  44         nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
  45         nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
  46         nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
  47
  48         nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
  49         nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
  50         nv_rd32(pmu, 0x000200);
  51 }
  52
  53 struct nvkm_oclass *
  54 gk104_pmu_oclass = &(struct nvkm_pmu_impl) {
  55         .base.handle = NV_SUBDEV(PMU, 0xe4),
  56         .base.ofuncs = &(struct nvkm_ofuncs) {
  57                 .ctor = _nvkm_pmu_ctor,
  58                 .dtor = _nvkm_pmu_dtor,
  59                 .init = _nvkm_pmu_init,
  60                 .fini = _nvkm_pmu_fini,
  61         },
  62         .code.data = gk104_pmu_code,
  63         .code.size = sizeof(gk104_pmu_code),
  64         .data.data = gk104_pmu_data,
  65         .data.size = sizeof(gk104_pmu_data),
  66         .pgob = gk104_pmu_pgob,
  67 }.base;