arch/alpha/include/asm/core_apecs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ALPHA_APECS__H__
   3 #define __ALPHA_APECS__H__
   4
   5 #include <linux/types.h>
   6 #include <asm/compiler.h>
   7
   8 /*
   9  * APECS is the internal name for the 2107x chipset which provides
  10  * memory controller and PCI access for the 21064 chip based systems.
  11  *
  12  * This file is based on:
  13  *
  14  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  15  * Data Sheet
  16  *
  17  * EC-N0648-72
  18  *
  19  *
  20  * david.rusling@reo.mts.dec.com Initial Version.
  21  *
  22  */
  23
  24 /*
  25    An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
  26    that get passed through the PCI<->ISA bridge chip. So we've gotta use
  27    both windows to max out the physical memory we can DMA to. Sigh...
  28
  29    If we try a window at 0 for 1GB as a work-around, we run into conflicts
  30    with ISA/PCI bus memory which can't be relocated, like VGA aperture and
  31    BIOS ROMs. So we must put the windows high enough to avoid these areas.
  32
  33    We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
  34    and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.
  35    Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
  36    be used for that range (via virt_to_bus()).
  37
  38    Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,
  39    to keep virt_to_bus() from returning an address in the first window, for
  40    a data area that goes beyond the 64Mb first DMA window.  Sigh...
  41    The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but
  42    we can't just use that here, because of header file looping... :-(
  43
  44    Window 1 will be used for all DMA from the ISA bus; yes, that does
  45    limit what memory an ISA floppy or sound card or Ethernet can touch, but
  46    it's also a known limitation on other platforms as well. We use the
  47    same technique that is used on INTEL platforms with similar limitation:
  48    set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
  49    We trust that any ISA bus device drivers will *always* ask for DMAable
  50    memory explicitly via kmalloc()/get_free_pages() flags arguments.
  51
  52    Note that most PCI bus devices' drivers do *not* explicitly ask for
  53    DMAable memory; they count on being able to DMA to any memory they
  54    get from kmalloc()/get_free_pages(). They will also use window 1 for
  55    any physical memory accesses below 64Mb; the rest will be handled by
  56    window 2, maxing out at 1Gb of memory. I trust this is enough... :-)
  57
  58    We hope that the area before the first window is large enough so that
  59    there will be no overlap at the top end (64Mb). We *must* locate the
  60    PCI cards' memory just below window 1, so that there's still the
  61    possibility of being able to access it via SPARSE space. This is
  62    important for cards such as the Matrox Millennium, whose Xserver
  63    wants to access memory-mapped registers in byte and short lengths.
  64
  65    Note that the XL is treated differently from the AVANTI, even though
  66    for most other things they are identical. It didn't seem reasonable to
  67    make the AVANTI support pay for the limitations of the XL. It is true,
  68    however, that an XL kernel will run on an AVANTI without problems.
  69
  70    %%% All of this should be obviated by the ability to route
  71    everything through the iommu.
  72 */
  73
  74 /*
  75  * 21071-DA Control and Status registers.
  76  * These are used for PCI memory access.
  77  */
  78 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  79 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  80 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  81 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  82 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
  83 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
  84
  85 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
  86 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
  87
  88 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
  89 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
  90
  91 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
  92 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
  93
  94 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
  95 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
  96 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
  97
  98 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
  99
 100 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
 101 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
 102 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
 103 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
 104 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
 105 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
 106 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
 107 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
 108
 109 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
 110 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
 111 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
 112 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
 113 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
 114 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
 115 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
 116 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
 117
 118 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
 119
 120
 121 /*
 122  * 21071-CA Control and Status registers.
 123  * These are used to program memory timing,
 124  *  configure memory and initialise the B-Cache.
 125  */
 126 #define APECS_MEM_GCR                   (IDENT_ADDR + 0x180000000UL)
 127 #define APECS_MEM_EDSR                  (IDENT_ADDR + 0x180000040UL)
 128 #define APECS_MEM_TAR                   (IDENT_ADDR + 0x180000060UL)
 129 #define APECS_MEM_ELAR                  (IDENT_ADDR + 0x180000080UL)
 130 #define APECS_MEM_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
 131 #define APECS_MEM_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
 132 #define APECS_MEM_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
 133 #define APECS_MEM_LDxHAR                (IDENT_ADDR + 0x180000100UL)
 134 #define APECS_MEM_GTR                   (IDENT_ADDR + 0x180000200UL)
 135 #define APECS_MEM_RTR                   (IDENT_ADDR + 0x180000220UL)
 136 #define APECS_MEM_VFPR                  (IDENT_ADDR + 0x180000240UL)
 137 #define APECS_MEM_PDLDR                 (IDENT_ADDR + 0x180000260UL)
 138 #define APECS_MEM_PDhDR                 (IDENT_ADDR + 0x180000280UL)
 139
 140 /* Bank x Base Address Register */
 141 #define APECS_MEM_B0BAR                 (IDENT_ADDR + 0x180000800UL)
 142 #define APECS_MEM_B1BAR                 (IDENT_ADDR + 0x180000820UL)
 143 #define APECS_MEM_B2BAR                 (IDENT_ADDR + 0x180000840UL)
 144 #define APECS_MEM_B3BAR                 (IDENT_ADDR + 0x180000860UL)
 145 #define APECS_MEM_B4BAR                 (IDENT_ADDR + 0x180000880UL)
 146 #define APECS_MEM_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
 147 #define APECS_MEM_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
 148 #define APECS_MEM_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
 149 #define APECS_MEM_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 150
 151 /* Bank x Configuration Register */
 152 #define APECS_MEM_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 153 #define APECS_MEM_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 154 #define APECS_MEM_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 155 #define APECS_MEM_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 156 #define APECS_MEM_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 157 #define APECS_MEM_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 158 #define APECS_MEM_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 159 #define APECS_MEM_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 160 #define APECS_MEM_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 161
 162 /* Bank x Timing Register A */
 163 #define APECS_MEM_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 164 #define APECS_MEM_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 165 #define APECS_MEM_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 166 #define APECS_MEM_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 167 #define APECS_MEM_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 168 #define APECS_MEM_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 169 #define APECS_MEM_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 170 #define APECS_MEM_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 171 #define APECS_MEM_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 172
 173 /* Bank x Timing Register B */
 174 #define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 175 #define APECS_MEM_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 176 #define APECS_MEM_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 177 #define APECS_MEM_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 178 #define APECS_MEM_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 179 #define APECS_MEM_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 180 #define APECS_MEM_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 181 #define APECS_MEM_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 182 #define APECS_MEM_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 183
 184
 185 /*
 186  * Memory spaces:
 187  */
 188 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 189 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 190 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 191 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 192 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 193
 194
 195 /*
 196  * Bit definitions for I/O Controller status register 0:
 197  */
 198 #define APECS_IOC_STAT0_CMD             0xf
 199 #define APECS_IOC_STAT0_ERR             (1<<4)
 200 #define APECS_IOC_STAT0_LOST            (1<<5)
 201 #define APECS_IOC_STAT0_THIT            (1<<6)
 202 #define APECS_IOC_STAT0_TREF            (1<<7)
 203 #define APECS_IOC_STAT0_CODE_SHIFT      8
 204 #define APECS_IOC_STAT0_CODE_MASK       0x7
 205 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 206 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 207
 208 #define APECS_HAE_ADDRESS               APECS_IOC_HAXR1
 209
 210
 211 /*
 212  * Data structure for handling APECS machine checks:
 213  */
 214
 215 struct el_apecs_mikasa_sysdata_mcheck
 216 {
 217         unsigned long coma_gcr;
 218         unsigned long coma_edsr;
 219         unsigned long coma_ter;
 220         unsigned long coma_elar;
 221         unsigned long coma_ehar;
 222         unsigned long coma_ldlr;
 223         unsigned long coma_ldhr;
 224         unsigned long coma_base0;
 225         unsigned long coma_base1;
 226         unsigned long coma_base2;
 227         unsigned long coma_base3;
 228         unsigned long coma_cnfg0;
 229         unsigned long coma_cnfg1;
 230         unsigned long coma_cnfg2;
 231         unsigned long coma_cnfg3;
 232         unsigned long epic_dcsr;
 233         unsigned long epic_pear;
 234         unsigned long epic_sear;
 235         unsigned long epic_tbr1;
 236         unsigned long epic_tbr2;
 237         unsigned long epic_pbr1;
 238         unsigned long epic_pbr2;
 239         unsigned long epic_pmr1;
 240         unsigned long epic_pmr2;
 241         unsigned long epic_harx1;
 242         unsigned long epic_harx2;
 243         unsigned long epic_pmlt;
 244         unsigned long epic_tag0;
 245         unsigned long epic_tag1;
 246         unsigned long epic_tag2;
 247         unsigned long epic_tag3;
 248         unsigned long epic_tag4;
 249         unsigned long epic_tag5;
 250         unsigned long epic_tag6;
 251         unsigned long epic_tag7;
 252         unsigned long epic_data0;
 253         unsigned long epic_data1;
 254         unsigned long epic_data2;
 255         unsigned long epic_data3;
 256         unsigned long epic_data4;
 257         unsigned long epic_data5;
 258         unsigned long epic_data6;
 259         unsigned long epic_data7;
 260
 261         unsigned long pceb_vid;
 262         unsigned long pceb_did;
 263         unsigned long pceb_revision;
 264         unsigned long pceb_command;
 265         unsigned long pceb_status;
 266         unsigned long pceb_latency;
 267         unsigned long pceb_control;
 268         unsigned long pceb_arbcon;
 269         unsigned long pceb_arbpri;
 270
 271         unsigned long esc_id;
 272         unsigned long esc_revision;
 273         unsigned long esc_int0;
 274         unsigned long esc_int1;
 275         unsigned long esc_elcr0;
 276         unsigned long esc_elcr1;
 277         unsigned long esc_last_eisa;
 278         unsigned long esc_nmi_stat;
 279
 280         unsigned long pci_ir;
 281         unsigned long pci_imr;
 282         unsigned long svr_mgr;
 283 };
 284
 285 /* This for the normal APECS machines.  */
 286 struct el_apecs_sysdata_mcheck
 287 {
 288         unsigned long coma_gcr;
 289         unsigned long coma_edsr;
 290         unsigned long coma_ter;
 291         unsigned long coma_elar;
 292         unsigned long coma_ehar;
 293         unsigned long coma_ldlr;
 294         unsigned long coma_ldhr;
 295         unsigned long coma_base0;
 296         unsigned long coma_base1;
 297         unsigned long coma_base2;
 298         unsigned long coma_cnfg0;
 299         unsigned long coma_cnfg1;
 300         unsigned long coma_cnfg2;
 301         unsigned long epic_dcsr;
 302         unsigned long epic_pear;
 303         unsigned long epic_sear;
 304         unsigned long epic_tbr1;
 305         unsigned long epic_tbr2;
 306         unsigned long epic_pbr1;
 307         unsigned long epic_pbr2;
 308         unsigned long epic_pmr1;
 309         unsigned long epic_pmr2;
 310         unsigned long epic_harx1;
 311         unsigned long epic_harx2;
 312         unsigned long epic_pmlt;
 313         unsigned long epic_tag0;
 314         unsigned long epic_tag1;
 315         unsigned long epic_tag2;
 316         unsigned long epic_tag3;
 317         unsigned long epic_tag4;
 318         unsigned long epic_tag5;
 319         unsigned long epic_tag6;
 320         unsigned long epic_tag7;
 321         unsigned long epic_data0;
 322         unsigned long epic_data1;
 323         unsigned long epic_data2;
 324         unsigned long epic_data3;
 325         unsigned long epic_data4;
 326         unsigned long epic_data5;
 327         unsigned long epic_data6;
 328         unsigned long epic_data7;
 329 };
 330
 331 struct el_apecs_procdata
 332 {
 333         unsigned long paltemp[32];  /* PAL TEMP REGS. */
 334         /* EV4-specific fields */
 335         unsigned long exc_addr;     /* Address of excepting instruction. */
 336         unsigned long exc_sum;      /* Summary of arithmetic traps. */
 337         unsigned long exc_mask;     /* Exception mask (from exc_sum). */
 338         unsigned long iccsr;        /* IBox hardware enables. */
 339         unsigned long pal_base;     /* Base address for PALcode. */
 340         unsigned long hier;         /* Hardware Interrupt Enable. */
 341         unsigned long hirr;         /* Hardware Interrupt Request. */
 342         unsigned long csr;          /* D-stream fault info. */
 343         unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */
 344         unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */
 345         unsigned long abox_ctl;     /* ABox Control Register. */
 346         unsigned long biu_stat;     /* BIU Status. */
 347         unsigned long biu_addr;     /* BUI Address. */
 348         unsigned long biu_ctl;      /* BIU Control. */
 349         unsigned long fill_syndrome;/* For correcting ECC errors. */
 350         unsigned long fill_addr;    /* Cache block which was being read */
 351         unsigned long va;           /* Effective VA of fault or miss. */
 352         unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/
 353 };
 354
 355
 356 #ifdef __KERNEL__
 357
 358 #ifndef __EXTERN_INLINE
 359 #define __EXTERN_INLINE extern inline
 360 #define __IO_EXTERN_INLINE
 361 #endif
 362
 363 /*
 364  * I/O functions:
 365  *
 366  * Unlike Jensen, the APECS machines have no concept of local
 367  * I/O---everything goes over the PCI bus.
 368  *
 369  * There is plenty room for optimization here.  In particular,
 370  * the Alpha's insb/insw/extb/extw should be useful in moving
 371  * data to/from the right byte-lanes.
 372  */
 373
 374 #define vip     volatile int __force *
 375 #define vuip    volatile unsigned int __force *
 376 #define vulp    volatile unsigned long __force *
 377
 378 #define APECS_SET_HAE                                           \
 379         do {                                                    \
 380                 if (addr >= (1UL << 24)) {                      \
 381                         unsigned long msb = addr & 0xf8000000;  \
 382                         addr -= msb;                            \
 383                         set_hae(msb);                           \
 384                 }                                               \
 385         } while (0)
 386
 387 __EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr)
 388 {
 389         unsigned long addr = (unsigned long) xaddr;
 390         unsigned long result, base_and_type;
 391
 392         if (addr >= APECS_DENSE_MEM) {
 393                 addr -= APECS_DENSE_MEM;
 394                 APECS_SET_HAE;
 395                 base_and_type = APECS_SPARSE_MEM + 0x00;
 396         } else {
 397                 addr -= APECS_IO;
 398                 base_and_type = APECS_IO + 0x00;
 399         }
 400
 401         result = *(vip) ((addr << 5) + base_and_type);
 402         return __kernel_extbl(result, addr & 3);
 403 }
 404
 405 __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
 406 {
 407         unsigned long addr = (unsigned long) xaddr;
 408         unsigned long w, base_and_type;
 409
 410         if (addr >= APECS_DENSE_MEM) {
 411                 addr -= APECS_DENSE_MEM;
 412                 APECS_SET_HAE;
 413                 base_and_type = APECS_SPARSE_MEM + 0x00;
 414         } else {
 415                 addr -= APECS_IO;
 416                 base_and_type = APECS_IO + 0x00;
 417         }
 418
 419         w = __kernel_insbl(b, addr & 3);
 420         *(vuip) ((addr << 5) + base_and_type) = w;
 421 }
 422
 423 __EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr)
 424 {
 425         unsigned long addr = (unsigned long) xaddr;
 426         unsigned long result, base_and_type;
 427
 428         if (addr >= APECS_DENSE_MEM) {
 429                 addr -= APECS_DENSE_MEM;
 430                 APECS_SET_HAE;
 431                 base_and_type = APECS_SPARSE_MEM + 0x08;
 432         } else {
 433                 addr -= APECS_IO;
 434                 base_and_type = APECS_IO + 0x08;
 435         }
 436
 437         result = *(vip) ((addr << 5) + base_and_type);
 438         return __kernel_extwl(result, addr & 3);
 439 }
 440
 441 __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
 442 {
 443         unsigned long addr = (unsigned long) xaddr;
 444         unsigned long w, base_and_type;
 445
 446         if (addr >= APECS_DENSE_MEM) {
 447                 addr -= APECS_DENSE_MEM;
 448                 APECS_SET_HAE;
 449                 base_and_type = APECS_SPARSE_MEM + 0x08;
 450         } else {
 451                 addr -= APECS_IO;
 452                 base_and_type = APECS_IO + 0x08;
 453         }
 454
 455         w = __kernel_inswl(b, addr & 3);
 456         *(vuip) ((addr << 5) + base_and_type) = w;
 457 }
 458
 459 __EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr)
 460 {
 461         unsigned long addr = (unsigned long) xaddr;
 462         if (addr < APECS_DENSE_MEM)
 463                 addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
 464         return *(vuip)addr;
 465 }
 466
 467 __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
 468 {
 469         unsigned long addr = (unsigned long) xaddr;
 470         if (addr < APECS_DENSE_MEM)
 471                 addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
 472         *(vuip)addr = b;
 473 }
 474
 475 __EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
 476 {
 477         return (void __iomem *)(addr + APECS_IO);
 478 }
 479
 480 __EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,
 481                                             unsigned long size)
 482 {
 483         return (void __iomem *)(addr + APECS_DENSE_MEM);
 484 }
 485
 486 __EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)
 487 {
 488         return addr >= IDENT_ADDR + 0x180000000UL;
 489 }
 490
 491 __EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)
 492 {
 493         return (unsigned long)addr >= APECS_DENSE_MEM;
 494 }
 495
 496 #undef APECS_SET_HAE
 497
 498 #undef vip
 499 #undef vuip
 500 #undef vulp
 501
 502 #undef __IO_PREFIX
 503 #define __IO_PREFIX             apecs
 504 #define apecs_trivial_io_bw     0
 505 #define apecs_trivial_io_lq     0
 506 #define apecs_trivial_rw_bw     2
 507 #define apecs_trivial_rw_lq     1
 508 #define apecs_trivial_iounmap   1
 509 #include <asm/io_trivial.h>
 510
 511 #ifdef __IO_EXTERN_INLINE
 512 #undef __EXTERN_INLINE
 513 #undef __IO_EXTERN_INLINE
 514 #endif
 515
 516 #endif /* __KERNEL__ */
 517
 518 #endif /* __ALPHA_APECS__H__ */