WIP FPC-III support
[linux/fpc-iii.git] / arch / arm / boot / dts / exynos5260.dtsi
blob973448c4ad930ae714e8fecb6bbec2fd2e94cc7f
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Samsung Exynos5260 SoC device tree source
4  *
5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6  *              http://www.samsung.com
7  */
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 / {
14         compatible = "samsung,exynos5260", "samsung,exynos5";
15         interrupt-parent = <&gic>;
16         #address-cells = <1>;
17         #size-cells = <1>;
19         aliases {
20                 i2c0 = &hsi2c_0;
21                 i2c1 = &hsi2c_1;
22                 i2c2 = &hsi2c_2;
23                 i2c3 = &hsi2c_3;
24                 pinctrl0 = &pinctrl_0;
25                 pinctrl1 = &pinctrl_1;
26                 pinctrl2 = &pinctrl_2;
27                 serial0 = &uart0;
28                 serial1 = &uart1;
29                 serial2 = &uart2;
30                 serial3 = &uart3;
31         };
33         cpus {
34                 #address-cells = <1>;
35                 #size-cells = <0>;
37                 cpu@0 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a15";
40                         reg = <0x0>;
41                         cci-control-port = <&cci_control1>;
42                 };
44                 cpu@1 {
45                         device_type = "cpu";
46                         compatible = "arm,cortex-a15";
47                         reg = <0x1>;
48                         cci-control-port = <&cci_control1>;
49                 };
51                 cpu@100 {
52                         device_type = "cpu";
53                         compatible = "arm,cortex-a7";
54                         reg = <0x100>;
55                         cci-control-port = <&cci_control0>;
56                 };
58                 cpu@101 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a7";
61                         reg = <0x101>;
62                         cci-control-port = <&cci_control0>;
63                 };
65                 cpu@102 {
66                         device_type = "cpu";
67                         compatible = "arm,cortex-a7";
68                         reg = <0x102>;
69                         cci-control-port = <&cci_control0>;
70                 };
72                 cpu@103 {
73                         device_type = "cpu";
74                         compatible = "arm,cortex-a7";
75                         reg = <0x103>;
76                         cci-control-port = <&cci_control0>;
77                 };
78         };
80         soc: soc {
81                 compatible = "simple-bus";
82                 #address-cells = <1>;
83                 #size-cells = <1>;
84                 ranges;
86                 clock_top: clock-controller@10010000 {
87                         compatible = "samsung,exynos5260-clock-top";
88                         reg = <0x10010000 0x10000>;
89                         #clock-cells = <1>;
90                 };
92                 clock_peri: clock-controller@10200000 {
93                         compatible = "samsung,exynos5260-clock-peri";
94                         reg = <0x10200000 0x10000>;
95                         #clock-cells = <1>;
96                 };
98                 clock_egl: clock-controller@10600000 {
99                         compatible = "samsung,exynos5260-clock-egl";
100                         reg = <0x10600000 0x10000>;
101                         #clock-cells = <1>;
102                 };
104                 clock_kfc: clock-controller@10700000 {
105                         compatible = "samsung,exynos5260-clock-kfc";
106                         reg = <0x10700000 0x10000>;
107                         #clock-cells = <1>;
108                 };
110                 clock_g2d: clock-controller@10a00000 {
111                         compatible = "samsung,exynos5260-clock-g2d";
112                         reg = <0x10A00000 0x10000>;
113                         #clock-cells = <1>;
114                 };
116                 clock_mif: clock-controller@10ce0000 {
117                         compatible = "samsung,exynos5260-clock-mif";
118                         reg = <0x10CE0000 0x10000>;
119                         #clock-cells = <1>;
120                 };
122                 clock_mfc: clock-controller@11090000 {
123                         compatible = "samsung,exynos5260-clock-mfc";
124                         reg = <0x11090000 0x10000>;
125                         #clock-cells = <1>;
126                 };
128                 clock_g3d: clock-controller@11830000 {
129                         compatible = "samsung,exynos5260-clock-g3d";
130                         reg = <0x11830000 0x10000>;
131                         #clock-cells = <1>;
132                 };
134                 clock_fsys: clock-controller@122e0000 {
135                         compatible = "samsung,exynos5260-clock-fsys";
136                         reg = <0x122E0000 0x10000>;
137                         #clock-cells = <1>;
138                 };
140                 clock_aud: clock-controller@128c0000 {
141                         compatible = "samsung,exynos5260-clock-aud";
142                         reg = <0x128C0000 0x10000>;
143                         #clock-cells = <1>;
144                 };
146                 clock_isp: clock-controller@133c0000 {
147                         compatible = "samsung,exynos5260-clock-isp";
148                         reg = <0x133C0000 0x10000>;
149                         #clock-cells = <1>;
150                 };
152                 clock_gscl: clock-controller@13f00000 {
153                         compatible = "samsung,exynos5260-clock-gscl";
154                         reg = <0x13F00000 0x10000>;
155                         #clock-cells = <1>;
156                 };
158                 clock_disp: clock-controller@14550000 {
159                         compatible = "samsung,exynos5260-clock-disp";
160                         reg = <0x14550000 0x10000>;
161                         #clock-cells = <1>;
162                 };
164                 gic: interrupt-controller@10481000 {
165                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
166                         #interrupt-cells = <3>;
167                         interrupt-controller;
168                         reg = <0x10481000 0x1000>,
169                                 <0x10482000 0x2000>,
170                                 <0x10484000 0x2000>,
171                                 <0x10486000 0x2000>;
172                         interrupts = <GIC_PPI 9
173                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
174                 };
176                 chipid: chipid@10000000 {
177                         compatible = "samsung,exynos4210-chipid";
178                         reg = <0x10000000 0x100>;
179                 };
181                 mct: timer@100b0000 {
182                         compatible = "samsung,exynos4210-mct";
183                         reg = <0x100B0000 0x1000>;
184                         clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
185                         clock-names = "fin_pll", "mct";
186                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
187                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
188                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
189                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
190                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
191                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
192                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
193                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
194                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
195                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
196                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
197                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
198                 };
200                 cci: cci@10f00000 {
201                         compatible = "arm,cci-400";
202                         #address-cells = <1>;
203                         #size-cells = <1>;
204                         reg = <0x10F00000 0x1000>;
205                         ranges = <0x0 0x10F00000 0x6000>;
207                         cci_control0: slave-if@4000 {
208                                 compatible = "arm,cci-400-ctrl-if";
209                                 interface-type = "ace";
210                                 reg = <0x4000 0x1000>;
211                         };
213                         cci_control1: slave-if@5000 {
214                                 compatible = "arm,cci-400-ctrl-if";
215                                 interface-type = "ace";
216                                 reg = <0x5000 0x1000>;
217                         };
218                 };
220                 pinctrl_0: pinctrl@11600000 {
221                         compatible = "samsung,exynos5260-pinctrl";
222                         reg = <0x11600000 0x1000>;
223                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
225                         wakeup-interrupt-controller {
226                                 compatible = "samsung,exynos4210-wakeup-eint";
227                                 interrupt-parent = <&gic>;
228                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
229                         };
230                 };
232                 pinctrl_1: pinctrl@12290000 {
233                         compatible = "samsung,exynos5260-pinctrl";
234                         reg = <0x12290000 0x1000>;
235                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
236                 };
238                 pinctrl_2: pinctrl@128b0000 {
239                         compatible = "samsung,exynos5260-pinctrl";
240                         reg = <0x128B0000 0x1000>;
241                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
242                 };
244                 pmu_system_controller: system-controller@10d50000 {
245                         compatible = "samsung,exynos5260-pmu", "syscon";
246                         reg = <0x10D50000 0x10000>;
247                 };
249                 uart0: serial@12c00000 {
250                         compatible = "samsung,exynos4210-uart";
251                         reg = <0x12C00000 0x100>;
252                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
253                         clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
254                         clock-names = "uart", "clk_uart_baud0";
255                         status = "disabled";
256                 };
258                 uart1: serial@12c10000 {
259                         compatible = "samsung,exynos4210-uart";
260                         reg = <0x12C10000 0x100>;
261                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
262                         clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
263                         clock-names = "uart", "clk_uart_baud0";
264                         status = "disabled";
265                 };
267                 uart2: serial@12c20000 {
268                         compatible = "samsung,exynos4210-uart";
269                         reg = <0x12C20000 0x100>;
270                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
271                         clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
272                         clock-names = "uart", "clk_uart_baud0";
273                         status = "disabled";
274                 };
276                 uart3: serial@12860000 {
277                         compatible = "samsung,exynos4210-uart";
278                         reg = <0x12860000 0x100>;
279                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
280                         clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
281                         clock-names = "uart", "clk_uart_baud0";
282                         status = "disabled";
283                 };
285                 mmc_0: mmc@12140000 {
286                         compatible = "samsung,exynos5250-dw-mshc";
287                         reg = <0x12140000 0x2000>;
288                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
289                         #address-cells = <1>;
290                         #size-cells = <0>;
291                         clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
292                         clock-names = "biu", "ciu";
293                         assigned-clocks =
294                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
295                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
296                                 <&clock_top TOP_SCLK_MMC0>;
297                         assigned-clock-parents =
298                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
299                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
300                         assigned-clock-rates = <0>, <0>, <800000000>;
301                         fifo-depth = <64>;
302                         status = "disabled";
303                 };
305                 mmc_1: mmc@12150000 {
306                         compatible = "samsung,exynos5250-dw-mshc";
307                         reg = <0x12150000 0x2000>;
308                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
309                         #address-cells = <1>;
310                         #size-cells = <0>;
311                         clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
312                         clock-names = "biu", "ciu";
313                         assigned-clocks =
314                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
315                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
316                                 <&clock_top TOP_SCLK_MMC1>;
317                         assigned-clock-parents =
318                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
319                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
320                         assigned-clock-rates = <0>, <0>, <800000000>;
321                         fifo-depth = <64>;
322                         status = "disabled";
323                 };
325                 mmc_2: mmc@12160000 {
326                         compatible = "samsung,exynos5250-dw-mshc";
327                         reg = <0x12160000 0x2000>;
328                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
329                         #address-cells = <1>;
330                         #size-cells = <0>;
331                         clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
332                         clock-names = "biu", "ciu";
333                         assigned-clocks =
334                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
335                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
336                                 <&clock_top TOP_SCLK_MMC2>;
337                         assigned-clock-parents =
338                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
339                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
340                         assigned-clock-rates = <0>, <0>, <800000000>;
341                         fifo-depth = <64>;
342                         status = "disabled";
343                 };
345                 hsi2c_0: hsi2c@12da0000 {
346                         compatible = "samsung,exynos5260-hsi2c";
347                         reg = <0x12DA0000 0x1000>;
348                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
349                         #address-cells = <1>;
350                         #size-cells = <0>;
351                         pinctrl-names = "default";
352                         pinctrl-0 = <&i2c0_hs_bus>;
353                         clocks = <&clock_peri PERI_CLK_HSIC0>;
354                         clock-names = "hsi2c";
355                         status = "disabled";
356                 };
358                 hsi2c_1: hsi2c@12db0000 {
359                         compatible = "samsung,exynos5260-hsi2c";
360                         reg = <0x12DB0000 0x1000>;
361                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
362                         #address-cells = <1>;
363                         #size-cells = <0>;
364                         pinctrl-names = "default";
365                         pinctrl-0 = <&i2c1_hs_bus>;
366                         clocks = <&clock_peri PERI_CLK_HSIC1>;
367                         clock-names = "hsi2c";
368                         status = "disabled";
369                 };
371                 hsi2c_2: hsi2c@12dc0000 {
372                         compatible = "samsung,exynos5260-hsi2c";
373                         reg = <0x12DC0000 0x1000>;
374                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
375                         #address-cells = <1>;
376                         #size-cells = <0>;
377                         pinctrl-names = "default";
378                         pinctrl-0 = <&i2c2_hs_bus>;
379                         clocks = <&clock_peri PERI_CLK_HSIC2>;
380                         clock-names = "hsi2c";
381                         status = "disabled";
382                 };
384                 hsi2c_3: hsi2c@12dd0000 {
385                         compatible = "samsung,exynos5260-hsi2c";
386                         reg = <0x12DD0000 0x1000>;
387                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
388                         #address-cells = <1>;
389                         #size-cells = <0>;
390                         pinctrl-names = "default";
391                         pinctrl-0 = <&i2c3_hs_bus>;
392                         clocks = <&clock_peri PERI_CLK_HSIC3>;
393                         clock-names = "hsi2c";
394                         status = "disabled";
395                 };
396         };
399 #include "exynos5260-pinctrl.dtsi"