arch/arm/boot/dts/rk3066a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3066a-cru.h>
  10 #include <dt-bindings/power/rk3066-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3066a";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1416000 1300000
  29                                 1200000 1175000
  30                                 1008000 1125000
  31                                 816000  1125000
  32                                 600000  1100000
  33                                 504000  1100000
  34                                 312000  1075000
  35                         >;
  36                         clock-latency = <40000>;
  37                         clocks = <&cru ARMCLK>;
  38                 };
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x1>;
  44                 };
  45         };
  46
  47         display-subsystem {
  48                 compatible = "rockchip,display-subsystem";
  49                 ports = <&vop0_out>, <&vop1_out>;
  50         };
  51
  52         sram: sram@10080000 {
  53                 compatible = "mmio-sram";
  54                 reg = <0x10080000 0x10000>;
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges = <0 0x10080000 0x10000>;
  58
  59                 smp-sram@0 {
  60                         compatible = "rockchip,rk3066-smp-sram";
  61                         reg = <0x0 0x50>;
  62                 };
  63         };
  64
  65         vop0: vop@1010c000 {
  66                 compatible = "rockchip,rk3066-vop";
  67                 reg = <0x1010c000 0x19c>;
  68                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&cru ACLK_LCDC0>,
  70                          <&cru DCLK_LCDC0>,
  71                          <&cru HCLK_LCDC0>;
  72                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  73                 power-domains = <&power RK3066_PD_VIO>;
  74                 resets = <&cru SRST_LCDC0_AXI>,
  75                          <&cru SRST_LCDC0_AHB>,
  76                          <&cru SRST_LCDC0_DCLK>;
  77                 reset-names = "axi", "ahb", "dclk";
  78                 status = "disabled";
  79
  80                 vop0_out: port {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83
  84                         vop0_out_hdmi: endpoint@0 {
  85                                 reg = <0>;
  86                                 remote-endpoint = <&hdmi_in_vop0>;
  87                         };
  88                 };
  89         };
  90
  91         vop1: vop@1010e000 {
  92                 compatible = "rockchip,rk3066-vop";
  93                 reg = <0x1010e000 0x19c>;
  94                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  95                 clocks = <&cru ACLK_LCDC1>,
  96                          <&cru DCLK_LCDC1>,
  97                          <&cru HCLK_LCDC1>;
  98                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  99                 power-domains = <&power RK3066_PD_VIO>;
 100                 resets = <&cru SRST_LCDC1_AXI>,
 101                          <&cru SRST_LCDC1_AHB>,
 102                          <&cru SRST_LCDC1_DCLK>;
 103                 reset-names = "axi", "ahb", "dclk";
 104                 status = "disabled";
 105
 106                 vop1_out: port {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109
 110                         vop1_out_hdmi: endpoint@0 {
 111                                 reg = <0>;
 112                                 remote-endpoint = <&hdmi_in_vop1>;
 113                         };
 114                 };
 115         };
 116
 117         hdmi: hdmi@10116000 {
 118                 compatible = "rockchip,rk3066-hdmi";
 119                 reg = <0x10116000 0x2000>;
 120                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 121                 clocks = <&cru HCLK_HDMI>;
 122                 clock-names = "hclk";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
 125                 power-domains = <&power RK3066_PD_VIO>;
 126                 rockchip,grf = <&grf>;
 127                 status = "disabled";
 128
 129                 ports {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132
 133                         hdmi_in: port@0 {
 134                                 reg = <0>;
 135                                 #address-cells = <1>;
 136                                 #size-cells = <0>;
 137
 138                                 hdmi_in_vop0: endpoint@0 {
 139                                         reg = <0>;
 140                                         remote-endpoint = <&vop0_out_hdmi>;
 141                                 };
 142
 143                                 hdmi_in_vop1: endpoint@1 {
 144                                         reg = <1>;
 145                                         remote-endpoint = <&vop1_out_hdmi>;
 146                                 };
 147                         };
 148
 149                         hdmi_out: port@1 {
 150                                 reg = <1>;
 151                         };
 152                 };
 153         };
 154
 155         i2s0: i2s@10118000 {
 156                 compatible = "rockchip,rk3066-i2s";
 157                 reg = <0x10118000 0x2000>;
 158                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 159                 pinctrl-names = "default";
 160                 pinctrl-0 = <&i2s0_bus>;
 161                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 162                 clock-names = "i2s_clk", "i2s_hclk";
 163                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
 164                 dma-names = "tx", "rx";
 165                 rockchip,playback-channels = <8>;
 166                 rockchip,capture-channels = <2>;
 167                 #sound-dai-cells = <0>;
 168                 status = "disabled";
 169         };
 170
 171         i2s1: i2s@1011a000 {
 172                 compatible = "rockchip,rk3066-i2s";
 173                 reg = <0x1011a000 0x2000>;
 174                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&i2s1_bus>;
 177                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 178                 clock-names = "i2s_clk", "i2s_hclk";
 179                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 180                 dma-names = "tx", "rx";
 181                 rockchip,playback-channels = <2>;
 182                 rockchip,capture-channels = <2>;
 183                 #sound-dai-cells = <0>;
 184                 status = "disabled";
 185         };
 186
 187         i2s2: i2s@1011c000 {
 188                 compatible = "rockchip,rk3066-i2s";
 189                 reg = <0x1011c000 0x2000>;
 190                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 191                 pinctrl-names = "default";
 192                 pinctrl-0 = <&i2s2_bus>;
 193                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 194                 clock-names = "i2s_clk", "i2s_hclk";
 195                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 196                 dma-names = "tx", "rx";
 197                 rockchip,playback-channels = <2>;
 198                 rockchip,capture-channels = <2>;
 199                 #sound-dai-cells = <0>;
 200                 status = "disabled";
 201         };
 202
 203         cru: clock-controller@20000000 {
 204                 compatible = "rockchip,rk3066a-cru";
 205                 reg = <0x20000000 0x1000>;
 206                 rockchip,grf = <&grf>;
 207
 208                 #clock-cells = <1>;
 209                 #reset-cells = <1>;
 210                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 211                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 212                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 213                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
 214                 assigned-clock-rates = <400000000>, <594000000>,
 215                                        <300000000>, <150000000>,
 216                                        <75000000>, <300000000>,
 217                                        <150000000>, <75000000>;
 218         };
 219
 220         timer@2000e000 {
 221                 compatible = "snps,dw-apb-timer-osc";
 222                 reg = <0x2000e000 0x100>;
 223                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 225                 clock-names = "timer", "pclk";
 226         };
 227
 228         efuse: efuse@20010000 {
 229                 compatible = "rockchip,rk3066a-efuse";
 230                 reg = <0x20010000 0x4000>;
 231                 #address-cells = <1>;
 232                 #size-cells = <1>;
 233                 clocks = <&cru PCLK_EFUSE>;
 234                 clock-names = "pclk_efuse";
 235
 236                 cpu_leakage: cpu_leakage@17 {
 237                         reg = <0x17 0x1>;
 238                 };
 239         };
 240
 241         timer@20038000 {
 242                 compatible = "snps,dw-apb-timer-osc";
 243                 reg = <0x20038000 0x100>;
 244                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 246                 clock-names = "timer", "pclk";
 247         };
 248
 249         timer@2003a000 {
 250                 compatible = "snps,dw-apb-timer-osc";
 251                 reg = <0x2003a000 0x100>;
 252                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 254                 clock-names = "timer", "pclk";
 255         };
 256
 257         tsadc: tsadc@20060000 {
 258                 compatible = "rockchip,rk3066-tsadc";
 259                 reg = <0x20060000 0x100>;
 260                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 261                 clock-names = "saradc", "apb_pclk";
 262                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 263                 #io-channel-cells = <1>;
 264                 resets = <&cru SRST_TSADC>;
 265                 reset-names = "saradc-apb";
 266                 status = "disabled";
 267         };
 268
 269         usbphy: phy {
 270                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 271                 rockchip,grf = <&grf>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 status = "disabled";
 275
 276                 usbphy0: usb-phy@17c {
 277                         #phy-cells = <0>;
 278                         reg = <0x17c>;
 279                         clocks = <&cru SCLK_OTGPHY0>;
 280                         clock-names = "phyclk";
 281                         #clock-cells = <0>;
 282                 };
 283
 284                 usbphy1: usb-phy@188 {
 285                         #phy-cells = <0>;
 286                         reg = <0x188>;
 287                         clocks = <&cru SCLK_OTGPHY1>;
 288                         clock-names = "phyclk";
 289                         #clock-cells = <0>;
 290                 };
 291         };
 292
 293         pinctrl: pinctrl {
 294                 compatible = "rockchip,rk3066a-pinctrl";
 295                 rockchip,grf = <&grf>;
 296                 #address-cells = <1>;
 297                 #size-cells = <1>;
 298                 ranges;
 299
 300                 gpio0: gpio0@20034000 {
 301                         compatible = "rockchip,gpio-bank";
 302                         reg = <0x20034000 0x100>;
 303                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&cru PCLK_GPIO0>;
 305
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308
 309                         interrupt-controller;
 310                         #interrupt-cells = <2>;
 311                 };
 312
 313                 gpio1: gpio1@2003c000 {
 314                         compatible = "rockchip,gpio-bank";
 315                         reg = <0x2003c000 0x100>;
 316                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&cru PCLK_GPIO1>;
 318
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                 };
 325
 326                 gpio2: gpio2@2003e000 {
 327                         compatible = "rockchip,gpio-bank";
 328                         reg = <0x2003e000 0x100>;
 329                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&cru PCLK_GPIO2>;
 331
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334
 335                         interrupt-controller;
 336                         #interrupt-cells = <2>;
 337                 };
 338
 339                 gpio3: gpio3@20080000 {
 340                         compatible = "rockchip,gpio-bank";
 341                         reg = <0x20080000 0x100>;
 342                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 343                         clocks = <&cru PCLK_GPIO3>;
 344
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347
 348                         interrupt-controller;
 349                         #interrupt-cells = <2>;
 350                 };
 351
 352                 gpio4: gpio4@20084000 {
 353                         compatible = "rockchip,gpio-bank";
 354                         reg = <0x20084000 0x100>;
 355                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 356                         clocks = <&cru PCLK_GPIO4>;
 357
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 gpio6: gpio6@2000a000 {
 366                         compatible = "rockchip,gpio-bank";
 367                         reg = <0x2000a000 0x100>;
 368                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&cru PCLK_GPIO6>;
 370
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373
 374                         interrupt-controller;
 375                         #interrupt-cells = <2>;
 376                 };
 377
 378                 pcfg_pull_default: pcfg_pull_default {
 379                         bias-pull-pin-default;
 380                 };
 381
 382                 pcfg_pull_none: pcfg_pull_none {
 383                         bias-disable;
 384                 };
 385
 386                 emac {
 387                         emac_xfer: emac-xfer {
 388                                 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
 389                                                 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
 390                                                 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
 391                                                 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
 392                                                 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
 393                                                 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
 394                                                 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
 395                                                 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
 396                         };
 397
 398                         emac_mdio: emac-mdio {
 399                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
 400                                                 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
 401                         };
 402                 };
 403
 404                 emmc {
 405                         emmc_clk: emmc-clk {
 406                                 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
 407                         };
 408
 409                         emmc_cmd: emmc-cmd {
 410                                 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
 411                         };
 412
 413                         emmc_rst: emmc-rst {
 414                                 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
 415                         };
 416
 417                         /*
 418                          * The data pins are shared between nandc and emmc and
 419                          * not accessible through pinctrl. Also they should've
 420                          * been already set correctly by firmware, as
 421                          * flash/emmc is the boot-device.
 422                          */
 423                 };
 424
 425                 hdmi {
 426                         hdmi_hpd: hdmi-hpd {
 427                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
 428                         };
 429
 430                         hdmii2c_xfer: hdmii2c-xfer {
 431                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
 432                                                 <0 RK_PA2 1 &pcfg_pull_none>;
 433                         };
 434                 };
 435
 436                 i2c0 {
 437                         i2c0_xfer: i2c0-xfer {
 438                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
 439                                                 <2 RK_PD5 1 &pcfg_pull_none>;
 440                         };
 441                 };
 442
 443                 i2c1 {
 444                         i2c1_xfer: i2c1-xfer {
 445                                 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
 446                                                 <2 RK_PD7 1 &pcfg_pull_none>;
 447                         };
 448                 };
 449
 450                 i2c2 {
 451                         i2c2_xfer: i2c2-xfer {
 452                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
 453                                                 <3 RK_PA1 1 &pcfg_pull_none>;
 454                         };
 455                 };
 456
 457                 i2c3 {
 458                         i2c3_xfer: i2c3-xfer {
 459                                 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
 460                                                 <3 RK_PA3 2 &pcfg_pull_none>;
 461                         };
 462                 };
 463
 464                 i2c4 {
 465                         i2c4_xfer: i2c4-xfer {
 466                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
 467                                                 <3 RK_PA5 1 &pcfg_pull_none>;
 468                         };
 469                 };
 470
 471                 pwm0 {
 472                         pwm0_out: pwm0-out {
 473                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
 474                         };
 475                 };
 476
 477                 pwm1 {
 478                         pwm1_out: pwm1-out {
 479                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
 480                         };
 481                 };
 482
 483                 pwm2 {
 484                         pwm2_out: pwm2-out {
 485                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
 486                         };
 487                 };
 488
 489                 pwm3 {
 490                         pwm3_out: pwm3-out {
 491                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
 492                         };
 493                 };
 494
 495                 spi0 {
 496                         spi0_clk: spi0-clk {
 497                                 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
 498                         };
 499                         spi0_cs0: spi0-cs0 {
 500                                 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
 501                         };
 502                         spi0_tx: spi0-tx {
 503                                 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
 504                         };
 505                         spi0_rx: spi0-rx {
 506                                 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
 507                         };
 508                         spi0_cs1: spi0-cs1 {
 509                                 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
 510                         };
 511                 };
 512
 513                 spi1 {
 514                         spi1_clk: spi1-clk {
 515                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
 516                         };
 517                         spi1_cs0: spi1-cs0 {
 518                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
 519                         };
 520                         spi1_rx: spi1-rx {
 521                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
 522                         };
 523                         spi1_tx: spi1-tx {
 524                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
 525                         };
 526                         spi1_cs1: spi1-cs1 {
 527                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
 528                         };
 529                 };
 530
 531                 uart0 {
 532                         uart0_xfer: uart0-xfer {
 533                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
 534                                                 <1 RK_PA1 1 &pcfg_pull_default>;
 535                         };
 536
 537                         uart0_cts: uart0-cts {
 538                                 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
 539                         };
 540
 541                         uart0_rts: uart0-rts {
 542                                 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
 543                         };
 544                 };
 545
 546                 uart1 {
 547                         uart1_xfer: uart1-xfer {
 548                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
 549                                                 <1 RK_PA5 1 &pcfg_pull_default>;
 550                         };
 551
 552                         uart1_cts: uart1-cts {
 553                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
 554                         };
 555
 556                         uart1_rts: uart1-rts {
 557                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
 558                         };
 559                 };
 560
 561                 uart2 {
 562                         uart2_xfer: uart2-xfer {
 563                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
 564                                                 <1 RK_PB1 1 &pcfg_pull_default>;
 565                         };
 566                         /* no rts / cts for uart2 */
 567                 };
 568
 569                 uart3 {
 570                         uart3_xfer: uart3-xfer {
 571                                 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
 572                                                 <3 RK_PD4 1 &pcfg_pull_default>;
 573                         };
 574
 575                         uart3_cts: uart3-cts {
 576                                 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
 577                         };
 578
 579                         uart3_rts: uart3-rts {
 580                                 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
 581                         };
 582                 };
 583
 584                 sd0 {
 585                         sd0_clk: sd0-clk {
 586                                 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
 587                         };
 588
 589                         sd0_cmd: sd0-cmd {
 590                                 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
 591                         };
 592
 593                         sd0_cd: sd0-cd {
 594                                 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
 595                         };
 596
 597                         sd0_wp: sd0-wp {
 598                                 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
 599                         };
 600
 601                         sd0_bus1: sd0-bus-width1 {
 602                                 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
 603                         };
 604
 605                         sd0_bus4: sd0-bus-width4 {
 606                                 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
 607                                                 <3 RK_PB3 1 &pcfg_pull_default>,
 608                                                 <3 RK_PB4 1 &pcfg_pull_default>,
 609                                                 <3 RK_PB5 1 &pcfg_pull_default>;
 610                         };
 611                 };
 612
 613                 sd1 {
 614                         sd1_clk: sd1-clk {
 615                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
 616                         };
 617
 618                         sd1_cmd: sd1-cmd {
 619                                 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
 620                         };
 621
 622                         sd1_cd: sd1-cd {
 623                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
 624                         };
 625
 626                         sd1_wp: sd1-wp {
 627                                 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
 628                         };
 629
 630                         sd1_bus1: sd1-bus-width1 {
 631                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
 632                         };
 633
 634                         sd1_bus4: sd1-bus-width4 {
 635                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
 636                                                 <3 RK_PC2 1 &pcfg_pull_default>,
 637                                                 <3 RK_PC3 1 &pcfg_pull_default>,
 638                                                 <3 RK_PC4 1 &pcfg_pull_default>;
 639                         };
 640                 };
 641
 642                 i2s0 {
 643                         i2s0_bus: i2s0-bus {
 644                                 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
 645                                                 <0 RK_PB0 1 &pcfg_pull_default>,
 646                                                 <0 RK_PB1 1 &pcfg_pull_default>,
 647                                                 <0 RK_PB2 1 &pcfg_pull_default>,
 648                                                 <0 RK_PB3 1 &pcfg_pull_default>,
 649                                                 <0 RK_PB4 1 &pcfg_pull_default>,
 650                                                 <0 RK_PB5 1 &pcfg_pull_default>,
 651                                                 <0 RK_PB6 1 &pcfg_pull_default>,
 652                                                 <0 RK_PB7 1 &pcfg_pull_default>;
 653                         };
 654                 };
 655
 656                 i2s1 {
 657                         i2s1_bus: i2s1-bus {
 658                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
 659                                                 <0 RK_PC1 1 &pcfg_pull_default>,
 660                                                 <0 RK_PC2 1 &pcfg_pull_default>,
 661                                                 <0 RK_PC3 1 &pcfg_pull_default>,
 662                                                 <0 RK_PC4 1 &pcfg_pull_default>,
 663                                                 <0 RK_PC5 1 &pcfg_pull_default>;
 664                         };
 665                 };
 666
 667                 i2s2 {
 668                         i2s2_bus: i2s2-bus {
 669                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
 670                                                 <0 RK_PD1 1 &pcfg_pull_default>,
 671                                                 <0 RK_PD2 1 &pcfg_pull_default>,
 672                                                 <0 RK_PD3 1 &pcfg_pull_default>,
 673                                                 <0 RK_PD4 1 &pcfg_pull_default>,
 674                                                 <0 RK_PD5 1 &pcfg_pull_default>;
 675                         };
 676                 };
 677         };
 678 };
 679
 680 &gpu {
 681         compatible = "rockchip,rk3066-mali", "arm,mali-400";
 682         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 683                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 684                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 685                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 686                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 687                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 688                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 689                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 690                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 691                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 692         interrupt-names = "gp",
 693                           "gpmmu",
 694                           "pp0",
 695                           "ppmmu0",
 696                           "pp1",
 697                           "ppmmu1",
 698                           "pp2",
 699                           "ppmmu2",
 700                           "pp3",
 701                           "ppmmu3";
 702         power-domains = <&power RK3066_PD_GPU>;
 703 };
 704
 705 &i2c0 {
 706         pinctrl-names = "default";
 707         pinctrl-0 = <&i2c0_xfer>;
 708 };
 709
 710 &i2c1 {
 711         pinctrl-names = "default";
 712         pinctrl-0 = <&i2c1_xfer>;
 713 };
 714
 715 &i2c2 {
 716         pinctrl-names = "default";
 717         pinctrl-0 = <&i2c2_xfer>;
 718 };
 719
 720 &i2c3 {
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&i2c3_xfer>;
 723 };
 724
 725 &i2c4 {
 726         pinctrl-names = "default";
 727         pinctrl-0 = <&i2c4_xfer>;
 728 };
 729
 730 &mmc0 {
 731         clock-frequency = <50000000>;
 732         dmas = <&dmac2 1>;
 733         dma-names = "rx-tx";
 734         max-frequency = <50000000>;
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 737 };
 738
 739 &mmc1 {
 740         dmas = <&dmac2 3>;
 741         dma-names = "rx-tx";
 742         pinctrl-names = "default";
 743         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 744 };
 745
 746 &emmc {
 747         dmas = <&dmac2 4>;
 748         dma-names = "rx-tx";
 749 };
 750
 751 &pmu {
 752         power: power-controller {
 753                 compatible = "rockchip,rk3066-power-controller";
 754                 #power-domain-cells = <1>;
 755                 #address-cells = <1>;
 756                 #size-cells = <0>;
 757
 758                 pd_vio@RK3066_PD_VIO {
 759                         reg = <RK3066_PD_VIO>;
 760                         clocks = <&cru ACLK_LCDC0>,
 761                                  <&cru ACLK_LCDC1>,
 762                                  <&cru DCLK_LCDC0>,
 763                                  <&cru DCLK_LCDC1>,
 764                                  <&cru HCLK_LCDC0>,
 765                                  <&cru HCLK_LCDC1>,
 766                                  <&cru SCLK_CIF1>,
 767                                  <&cru ACLK_CIF1>,
 768                                  <&cru HCLK_CIF1>,
 769                                  <&cru SCLK_CIF0>,
 770                                  <&cru ACLK_CIF0>,
 771                                  <&cru HCLK_CIF0>,
 772                                  <&cru HCLK_HDMI>,
 773                                  <&cru ACLK_IPP>,
 774                                  <&cru HCLK_IPP>,
 775                                  <&cru ACLK_RGA>,
 776                                  <&cru HCLK_RGA>;
 777                         pm_qos = <&qos_lcdc0>,
 778                                  <&qos_lcdc1>,
 779                                  <&qos_cif0>,
 780                                  <&qos_cif1>,
 781                                  <&qos_ipp>,
 782                                  <&qos_rga>;
 783                 };
 784
 785                 pd_video@RK3066_PD_VIDEO {
 786                         reg = <RK3066_PD_VIDEO>;
 787                         clocks = <&cru ACLK_VDPU>,
 788                                  <&cru ACLK_VEPU>,
 789                                  <&cru HCLK_VDPU>,
 790                                  <&cru HCLK_VEPU>;
 791                         pm_qos = <&qos_vpu>;
 792                 };
 793
 794                 pd_gpu@RK3066_PD_GPU {
 795                         reg = <RK3066_PD_GPU>;
 796                         clocks = <&cru ACLK_GPU>;
 797                         pm_qos = <&qos_gpu>;
 798                 };
 799         };
 800 };
 801
 802 &pwm0 {
 803         pinctrl-names = "default";
 804         pinctrl-0 = <&pwm0_out>;
 805 };
 806
 807 &pwm1 {
 808         pinctrl-names = "default";
 809         pinctrl-0 = <&pwm1_out>;
 810 };
 811
 812 &pwm2 {
 813         pinctrl-names = "default";
 814         pinctrl-0 = <&pwm2_out>;
 815 };
 816
 817 &pwm3 {
 818         pinctrl-names = "default";
 819         pinctrl-0 = <&pwm3_out>;
 820 };
 821
 822 &spi0 {
 823         pinctrl-names = "default";
 824         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 825 };
 826
 827 &spi1 {
 828         pinctrl-names = "default";
 829         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 830 };
 831
 832 &uart0 {
 833         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 834         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
 835         dma-names = "tx", "rx";
 836         pinctrl-names = "default";
 837         pinctrl-0 = <&uart0_xfer>;
 838 };
 839
 840 &uart1 {
 841         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 842         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
 843         dma-names = "tx", "rx";
 844         pinctrl-names = "default";
 845         pinctrl-0 = <&uart1_xfer>;
 846 };
 847
 848 &uart2 {
 849         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 850         dmas = <&dmac2 6>, <&dmac2 7>;
 851         dma-names = "tx", "rx";
 852         pinctrl-names = "default";
 853         pinctrl-0 = <&uart2_xfer>;
 854 };
 855
 856 &uart3 {
 857         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 858         dmas = <&dmac2 8>, <&dmac2 9>;
 859         dma-names = "tx", "rx";
 860         pinctrl-names = "default";
 861         pinctrl-0 = <&uart3_xfer>;
 862 };
 863
 864 &wdt {
 865         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 866 };
 867
 868 &emac {
 869         compatible = "rockchip,rk3066-emac";
 870 };