1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arch/mach-ixp4xx/vulcan-pci.c
5 * Vulcan board-level PCI initialization
7 * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
9 * based on ixdp425-pci.c:
10 * Copyright (C) 2002 Intel Corporation.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <asm/mach/pci.h>
18 #include <asm/mach-types.h>
22 /* PCI controller GPIO to IRQ pin mappings */
26 void __init
vulcan_pci_preinit(void)
28 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
30 * Cardbus bridge wants way more than the SoC can actually offer,
31 * and leaves the whole PCI bus in a mess. Artificially limit it
32 * to 8MB per region. Of course indirect mode doesn't have this
35 pci_cardbus_mem_size
= SZ_8M
;
36 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
37 (int)(pci_cardbus_mem_size
>> 20));
39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA
), IRQ_TYPE_LEVEL_LOW
);
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB
), IRQ_TYPE_LEVEL_LOW
);
44 static int __init
vulcan_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
47 return IXP4XX_GPIO_IRQ(INTA
);
50 return IXP4XX_GPIO_IRQ(INTB
);
55 struct hw_pci vulcan_pci __initdata
= {
58 .preinit
= vulcan_pci_preinit
,
59 .setup
= ixp4xx_setup
,
60 .map_irq
= vulcan_map_irq
,
63 int __init
vulcan_pci_init(void)
65 if (machine_is_arcom_vulcan())
66 pci_common_init(&vulcan_pci
);
70 subsys_initcall(vulcan_pci_init
);