| blob | 51cc30e84e26143005e13b8b4a9b7ab4e4ed888e |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
15 / {
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 chosen {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
25 simplefb_lcd: framebuffer-lcd {
26 compatible = "allwinner,simple-framebuffer",
27 "simple-framebuffer";
28 allwinner,pipeline = "mixer0-lcd0";
29 clocks = <&ccu CLK_TCON0>,
30 <&display_clocks CLK_MIXER0>;
31 status = "disabled";
32 };
34 simplefb_hdmi: framebuffer-hdmi {
35 compatible = "allwinner,simple-framebuffer",
36 "simple-framebuffer";
37 allwinner,pipeline = "mixer1-lcd1-hdmi";
38 clocks = <&display_clocks CLK_MIXER1>,
39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40 status = "disabled";
41 };
42 };
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 reg = <0>;
52 enable-method = "psci";
53 next-level-cache = <&L2>;
54 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 };
59 cpu1: cpu@1 {
60 compatible = "arm,cortex-a53";
61 device_type = "cpu";
62 reg = <1>;
63 enable-method = "psci";
64 next-level-cache = <&L2>;
65 clocks = <&ccu CLK_CPUX>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
68 };
70 cpu2: cpu@2 {
71 compatible = "arm,cortex-a53";
72 device_type = "cpu";
73 reg = <2>;
74 enable-method = "psci";
75 next-level-cache = <&L2>;
76 clocks = <&ccu CLK_CPUX>;
77 clock-names = "cpu";
78 #cooling-cells = <2>;
79 };
81 cpu3: cpu@3 {
82 compatible = "arm,cortex-a53";
83 device_type = "cpu";
84 reg = <3>;
85 enable-method = "psci";
86 next-level-cache = <&L2>;
87 clocks = <&ccu CLK_CPUX>;
88 clock-names = "cpu";
89 #cooling-cells = <2>;
90 };
92 L2: l2-cache {
93 compatible = "cache";
94 cache-level = <2>;
95 };
96 };
98 de: display-engine {
99 compatible = "allwinner,sun50i-a64-display-engine";
100 allwinner,pipelines = <&mixer0>,
101 <&mixer1>;
102 status = "disabled";
103 };
105 osc24M: osc24M_clk {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc24M";
110 };
112 osc32k: osc32k_clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "ext-osc32k";
117 };
119 pmu {
120 compatible = "arm,cortex-a53-pmu";
121 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126 };
128 psci {
129 compatible = "arm,psci-0.2";
130 method = "smc";
131 };
133 sound: sound {
134 compatible = "simple-audio-card";
135 simple-audio-card,name = "sun50i-a64-audio";
136 simple-audio-card,format = "i2s";
137 simple-audio-card,frame-master = <&cpudai>;
138 simple-audio-card,bitclock-master = <&cpudai>;
139 simple-audio-card,mclk-fs = <128>;
140 simple-audio-card,aux-devs = <&codec_analog>;
141 simple-audio-card,routing =
142 "Left DAC", "DACL",
143 "Right DAC", "DACR",
144 "ADCL", "Left ADC",
145 "ADCR", "Right ADC";
146 status = "disabled";
148 cpudai: simple-audio-card,cpu {
149 sound-dai = <&dai>;
150 };
152 link_codec: simple-audio-card,codec {
153 sound-dai = <&codec>;
154 };
155 };
157 timer {
158 compatible = "arm,armv8-timer";
159 allwinner,erratum-unknown1;
160 arm,no-tick-in-suspend;
161 interrupts = <GIC_PPI 13
162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
163 <GIC_PPI 14
164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165 <GIC_PPI 11
166 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 10
168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
169 };
171 thermal-zones {
172 cpu_thermal: cpu0-thermal {
173 /* milliseconds */
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
178 cooling-maps {
179 map0 {
180 trip = <&cpu_alert0>;
181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
184 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185 };
186 map1 {
187 trip = <&cpu_alert1>;
188 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
192 };
193 };
195 trips {
196 cpu_alert0: cpu_alert0 {
197 /* milliCelsius */
198 temperature = <75000>;
199 hysteresis = <2000>;
200 type = "passive";
201 };
203 cpu_alert1: cpu_alert1 {
204 /* milliCelsius */
205 temperature = <90000>;
206 hysteresis = <2000>;
207 type = "hot";
208 };
210 cpu_crit: cpu_crit {
211 /* milliCelsius */
212 temperature = <110000>;
213 hysteresis = <2000>;
214 type = "critical";
215 };
216 };
217 };
219 gpu0_thermal: gpu0-thermal {
220 /* milliseconds */
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
223 thermal-sensors = <&ths 1>;
224 };
226 gpu1_thermal: gpu1-thermal {
227 /* milliseconds */
228 polling-delay-passive = <0>;
229 polling-delay = <0>;
230 thermal-sensors = <&ths 2>;
231 };
232 };
234 soc {
235 compatible = "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges;
240 bus@1000000 {
241 compatible = "allwinner,sun50i-a64-de2";
242 reg = <0x1000000 0x400000>;
243 allwinner,sram = <&de2_sram 1>;
244 #address-cells = <1>;
245 #size-cells = <1>;
246 ranges = <0 0x1000000 0x400000>;
248 display_clocks: clock@0 {
249 compatible = "allwinner,sun50i-a64-de2-clk";
250 reg = <0x0 0x10000>;
251 clocks = <&ccu CLK_BUS_DE>,
252 <&ccu CLK_DE>;
253 clock-names = "bus",
254 "mod";
255 resets = <&ccu RST_BUS_DE>;
256 #clock-cells = <1>;
257 #reset-cells = <1>;
258 };
260 rotate: rotate@20000 {
261 compatible = "allwinner,sun50i-a64-de2-rotate",
262 "allwinner,sun8i-a83t-de2-rotate";
263 reg = <0x20000 0x10000>;
264 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&display_clocks CLK_BUS_ROT>,
266 <&display_clocks CLK_ROT>;
267 clock-names = "bus",
268 "mod";
269 resets = <&display_clocks RST_ROT>;
270 };
272 mixer0: mixer@100000 {
273 compatible = "allwinner,sun50i-a64-de2-mixer-0";
274 reg = <0x100000 0x100000>;
275 clocks = <&display_clocks CLK_BUS_MIXER0>,
276 <&display_clocks CLK_MIXER0>;
277 clock-names = "bus",
278 "mod";
279 resets = <&display_clocks RST_MIXER0>;
281 ports {
282 #address-cells = <1>;
283 #size-cells = <0>;
285 mixer0_out: port@1 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <1>;
290 mixer0_out_tcon0: endpoint@0 {
291 reg = <0>;
292 remote-endpoint = <&tcon0_in_mixer0>;
293 };
295 mixer0_out_tcon1: endpoint@1 {
296 reg = <1>;
297 remote-endpoint = <&tcon1_in_mixer0>;
298 };
299 };
300 };
301 };
303 mixer1: mixer@200000 {
304 compatible = "allwinner,sun50i-a64-de2-mixer-1";
305 reg = <0x200000 0x100000>;
306 clocks = <&display_clocks CLK_BUS_MIXER1>,
307 <&display_clocks CLK_MIXER1>;
308 clock-names = "bus",
309 "mod";
310 resets = <&display_clocks RST_MIXER1>;
312 ports {
313 #address-cells = <1>;
314 #size-cells = <0>;
316 mixer1_out: port@1 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <1>;
321 mixer1_out_tcon0: endpoint@0 {
322 reg = <0>;
323 remote-endpoint = <&tcon0_in_mixer1>;
324 };
326 mixer1_out_tcon1: endpoint@1 {
327 reg = <1>;
328 remote-endpoint = <&tcon1_in_mixer1>;
329 };
330 };
331 };
332 };
333 };
335 syscon: syscon@1c00000 {
336 compatible = "allwinner,sun50i-a64-system-control";
337 reg = <0x01c00000 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 ranges;
342 sram_c: sram@18000 {
343 compatible = "mmio-sram";
344 reg = <0x00018000 0x28000>;
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges = <0 0x00018000 0x28000>;
349 de2_sram: sram-section@0 {
350 compatible = "allwinner,sun50i-a64-sram-c";
351 reg = <0x0000 0x28000>;
352 };
353 };
355 sram_c1: sram@1d00000 {
356 compatible = "mmio-sram";
357 reg = <0x01d00000 0x40000>;
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0 0x01d00000 0x40000>;
362 ve_sram: sram-section@0 {
363 compatible = "allwinner,sun50i-a64-sram-c1",
364 "allwinner,sun4i-a10-sram-c1";
365 reg = <0x000000 0x40000>;
366 };
367 };
368 };
370 dma: dma-controller@1c02000 {
371 compatible = "allwinner,sun50i-a64-dma";
372 reg = <0x01c02000 0x1000>;
373 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&ccu CLK_BUS_DMA>;
375 dma-channels = <8>;
376 dma-requests = <27>;
377 resets = <&ccu RST_BUS_DMA>;
378 #dma-cells = <1>;
379 };
381 tcon0: lcd-controller@1c0c000 {
382 compatible = "allwinner,sun50i-a64-tcon-lcd",
383 "allwinner,sun8i-a83t-tcon-lcd";
384 reg = <0x01c0c000 0x1000>;
385 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
387 clock-names = "ahb", "tcon-ch0";
388 clock-output-names = "tcon-pixel-clock";
389 #clock-cells = <0>;
390 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
391 reset-names = "lcd", "lvds";
393 ports {
394 #address-cells = <1>;
395 #size-cells = <0>;
397 tcon0_in: port@0 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <0>;
402 tcon0_in_mixer0: endpoint@0 {
403 reg = <0>;
404 remote-endpoint = <&mixer0_out_tcon0>;
405 };
407 tcon0_in_mixer1: endpoint@1 {
408 reg = <1>;
409 remote-endpoint = <&mixer1_out_tcon0>;
410 };
411 };
413 tcon0_out: port@1 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 reg = <1>;
418 tcon0_out_dsi: endpoint@1 {
419 reg = <1>;
420 remote-endpoint = <&dsi_in_tcon0>;
421 allwinner,tcon-channel = <1>;
422 };
423 };
424 };
425 };
427 tcon1: lcd-controller@1c0d000 {
428 compatible = "allwinner,sun50i-a64-tcon-tv",
429 "allwinner,sun8i-a83t-tcon-tv";
430 reg = <0x01c0d000 0x1000>;
431 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
433 clock-names = "ahb", "tcon-ch1";
434 resets = <&ccu RST_BUS_TCON1>;
435 reset-names = "lcd";
437 ports {
438 #address-cells = <1>;
439 #size-cells = <0>;
441 tcon1_in: port@0 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0>;
446 tcon1_in_mixer0: endpoint@0 {
447 reg = <0>;
448 remote-endpoint = <&mixer0_out_tcon1>;
449 };
451 tcon1_in_mixer1: endpoint@1 {
452 reg = <1>;
453 remote-endpoint = <&mixer1_out_tcon1>;
454 };
455 };
457 tcon1_out: port@1 {
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <1>;
462 tcon1_out_hdmi: endpoint@1 {
463 reg = <1>;
464 remote-endpoint = <&hdmi_in_tcon1>;
465 };
466 };
467 };
468 };
470 video-codec@1c0e000 {
471 compatible = "allwinner,sun50i-a64-video-engine";
472 reg = <0x01c0e000 0x1000>;
473 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
474 <&ccu CLK_DRAM_VE>;
475 clock-names = "ahb", "mod", "ram";
476 resets = <&ccu RST_BUS_VE>;
477 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478 allwinner,sram = <&ve_sram 1>;
479 };
481 mmc0: mmc@1c0f000 {
482 compatible = "allwinner,sun50i-a64-mmc";
483 reg = <0x01c0f000 0x1000>;
484 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
485 clock-names = "ahb", "mmc";
486 resets = <&ccu RST_BUS_MMC0>;
487 reset-names = "ahb";
488 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
489 max-frequency = <150000000>;
490 status = "disabled";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 };
495 mmc1: mmc@1c10000 {
496 compatible = "allwinner,sun50i-a64-mmc";
497 reg = <0x01c10000 0x1000>;
498 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
499 clock-names = "ahb", "mmc";
500 resets = <&ccu RST_BUS_MMC1>;
501 reset-names = "ahb";
502 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
503 max-frequency = <150000000>;
504 status = "disabled";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 };
509 mmc2: mmc@1c11000 {
510 compatible = "allwinner,sun50i-a64-emmc";
511 reg = <0x01c11000 0x1000>;
512 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
513 clock-names = "ahb", "mmc";
514 resets = <&ccu RST_BUS_MMC2>;
515 reset-names = "ahb";
516 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
517 max-frequency = <200000000>;
518 status = "disabled";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 };
523 sid: eeprom@1c14000 {
524 compatible = "allwinner,sun50i-a64-sid";
525 reg = <0x1c14000 0x400>;
526 #address-cells = <1>;
527 #size-cells = <1>;
529 ths_calibration: thermal-sensor-calibration@34 {
530 reg = <0x34 0x8>;
531 };
532 };
534 crypto: crypto@1c15000 {
535 compatible = "allwinner,sun50i-a64-crypto";
536 reg = <0x01c15000 0x1000>;
537 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
539 clock-names = "bus", "mod";
540 resets = <&ccu RST_BUS_CE>;
541 };
543 msgbox: mailbox@1c17000 {
544 compatible = "allwinner,sun50i-a64-msgbox",
545 "allwinner,sun6i-a31-msgbox";
546 reg = <0x01c17000 0x1000>;
547 clocks = <&ccu CLK_BUS_MSGBOX>;
548 resets = <&ccu RST_BUS_MSGBOX>;
549 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
550 #mbox-cells = <1>;
551 };
553 usb_otg: usb@1c19000 {
554 compatible = "allwinner,sun8i-a33-musb";
555 reg = <0x01c19000 0x0400>;
556 clocks = <&ccu CLK_BUS_OTG>;
557 resets = <&ccu RST_BUS_OTG>;
558 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "mc";
560 phys = <&usbphy 0>;
561 phy-names = "usb";
562 extcon = <&usbphy 0>;
563 dr_mode = "otg";
564 status = "disabled";
565 };
567 usbphy: phy@1c19400 {
568 compatible = "allwinner,sun50i-a64-usb-phy";
569 reg = <0x01c19400 0x14>,
570 <0x01c1a800 0x4>,
571 <0x01c1b800 0x4>;
572 reg-names = "phy_ctrl",
573 "pmu0",
574 "pmu1";
575 clocks = <&ccu CLK_USB_PHY0>,
576 <&ccu CLK_USB_PHY1>;
577 clock-names = "usb0_phy",
578 "usb1_phy";
579 resets = <&ccu RST_USB_PHY0>,
580 <&ccu RST_USB_PHY1>;
581 reset-names = "usb0_reset",
582 "usb1_reset";
583 status = "disabled";
584 #phy-cells = <1>;
585 };
587 ehci0: usb@1c1a000 {
588 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
589 reg = <0x01c1a000 0x100>;
590 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ccu CLK_BUS_OHCI0>,
592 <&ccu CLK_BUS_EHCI0>,
593 <&ccu CLK_USB_OHCI0>;
594 resets = <&ccu RST_BUS_OHCI0>,
595 <&ccu RST_BUS_EHCI0>;
596 status = "disabled";
597 };
599 ohci0: usb@1c1a400 {
600 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
601 reg = <0x01c1a400 0x100>;
602 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ccu CLK_BUS_OHCI0>,
604 <&ccu CLK_USB_OHCI0>;
605 resets = <&ccu RST_BUS_OHCI0>;
606 status = "disabled";
607 };
609 ehci1: usb@1c1b000 {
610 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
611 reg = <0x01c1b000 0x100>;
612 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&ccu CLK_BUS_OHCI1>,
614 <&ccu CLK_BUS_EHCI1>,
615 <&ccu CLK_USB_OHCI1>;
616 resets = <&ccu RST_BUS_OHCI1>,
617 <&ccu RST_BUS_EHCI1>;
618 phys = <&usbphy 1>;
619 phy-names = "usb";
620 status = "disabled";
621 };
623 ohci1: usb@1c1b400 {
624 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
625 reg = <0x01c1b400 0x100>;
626 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&ccu CLK_BUS_OHCI1>,
628 <&ccu CLK_USB_OHCI1>;
629 resets = <&ccu RST_BUS_OHCI1>;
630 phys = <&usbphy 1>;
631 phy-names = "usb";
632 status = "disabled";
633 };
635 ccu: clock@1c20000 {
636 compatible = "allwinner,sun50i-a64-ccu";
637 reg = <0x01c20000 0x400>;
638 clocks = <&osc24M>, <&rtc 0>;
639 clock-names = "hosc", "losc";
640 #clock-cells = <1>;
641 #reset-cells = <1>;
642 };
644 pio: pinctrl@1c20800 {
645 compatible = "allwinner,sun50i-a64-pinctrl";
646 reg = <0x01c20800 0x400>;
647 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
651 clock-names = "apb", "hosc", "losc";
652 gpio-controller;
653 #gpio-cells = <3>;
654 interrupt-controller;
655 #interrupt-cells = <3>;
657 csi_pins: csi-pins {
658 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
659 "PE7", "PE8", "PE9", "PE10", "PE11";
660 function = "csi";
661 };
663 /omit-if-no-ref/
664 csi_mclk_pin: csi-mclk-pin {
665 pins = "PE1";
666 function = "csi";
667 };
669 i2c0_pins: i2c0-pins {
670 pins = "PH0", "PH1";
671 function = "i2c0";
672 };
674 i2c1_pins: i2c1-pins {
675 pins = "PH2", "PH3";
676 function = "i2c1";
677 };
679 i2c2_pins: i2c2-pins {
680 pins = "PE14", "PE15";
681 function = "i2c2";
682 };
684 /omit-if-no-ref/
685 lcd_rgb666_pins: lcd-rgb666-pins {
686 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
687 "PD5", "PD6", "PD7", "PD8", "PD9",
688 "PD10", "PD11", "PD12", "PD13",
689 "PD14", "PD15", "PD16", "PD17",
690 "PD18", "PD19", "PD20", "PD21";
691 function = "lcd0";
692 };
694 mmc0_pins: mmc0-pins {
695 pins = "PF0", "PF1", "PF2", "PF3",
696 "PF4", "PF5";
697 function = "mmc0";
698 drive-strength = <30>;
699 bias-pull-up;
700 };
702 mmc1_pins: mmc1-pins {
703 pins = "PG0", "PG1", "PG2", "PG3",
704 "PG4", "PG5";
705 function = "mmc1";
706 drive-strength = <30>;
707 bias-pull-up;
708 };
710 mmc2_pins: mmc2-pins {
711 pins = "PC5", "PC6", "PC8", "PC9",
712 "PC10","PC11", "PC12", "PC13",
713 "PC14", "PC15", "PC16";
714 function = "mmc2";
715 drive-strength = <30>;
716 bias-pull-up;
717 };
719 mmc2_ds_pin: mmc2-ds-pin {
720 pins = "PC1";
721 function = "mmc2";
722 drive-strength = <30>;
723 bias-pull-up;
724 };
726 pwm_pin: pwm-pin {
727 pins = "PD22";
728 function = "pwm";
729 };
731 rmii_pins: rmii-pins {
732 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
733 "PD18", "PD19", "PD20", "PD22", "PD23";
734 function = "emac";
735 drive-strength = <40>;
736 };
738 rgmii_pins: rgmii-pins {
739 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
740 "PD13", "PD15", "PD16", "PD17", "PD18",
741 "PD19", "PD20", "PD21", "PD22", "PD23";
742 function = "emac";
743 drive-strength = <40>;
744 };
746 spdif_tx_pin: spdif-tx-pin {
747 pins = "PH8";
748 function = "spdif";
749 };
751 spi0_pins: spi0-pins {
752 pins = "PC0", "PC1", "PC2", "PC3";
753 function = "spi0";
754 };
756 spi1_pins: spi1-pins {
757 pins = "PD0", "PD1", "PD2", "PD3";
758 function = "spi1";
759 };
761 uart0_pb_pins: uart0-pb-pins {
762 pins = "PB8", "PB9";
763 function = "uart0";
764 };
766 uart1_pins: uart1-pins {
767 pins = "PG6", "PG7";
768 function = "uart1";
769 };
771 uart1_rts_cts_pins: uart1-rts-cts-pins {
772 pins = "PG8", "PG9";
773 function = "uart1";
774 };
776 uart2_pins: uart2-pins {
777 pins = "PB0", "PB1";
778 function = "uart2";
779 };
781 uart3_pins: uart3-pins {
782 pins = "PD0", "PD1";
783 function = "uart3";
784 };
786 uart4_pins: uart4-pins {
787 pins = "PD2", "PD3";
788 function = "uart4";
789 };
791 uart4_rts_cts_pins: uart4-rts-cts-pins {
792 pins = "PD4", "PD5";
793 function = "uart4";
794 };
795 };
797 spdif: spdif@1c21000 {
798 #sound-dai-cells = <0>;
799 compatible = "allwinner,sun50i-a64-spdif",
800 "allwinner,sun8i-h3-spdif";
801 reg = <0x01c21000 0x400>;
802 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
804 resets = <&ccu RST_BUS_SPDIF>;
805 clock-names = "apb", "spdif";
806 dmas = <&dma 2>;
807 dma-names = "tx";
808 pinctrl-names = "default";
809 pinctrl-0 = <&spdif_tx_pin>;
810 status = "disabled";
811 };
813 lradc: lradc@1c21800 {
814 compatible = "allwinner,sun50i-a64-lradc",
815 "allwinner,sun8i-a83t-r-lradc";
816 reg = <0x01c21800 0x400>;
817 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
818 status = "disabled";
819 };
821 i2s0: i2s@1c22000 {
822 #sound-dai-cells = <0>;
823 compatible = "allwinner,sun50i-a64-i2s",
824 "allwinner,sun8i-h3-i2s";
825 reg = <0x01c22000 0x400>;
826 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
828 clock-names = "apb", "mod";
829 resets = <&ccu RST_BUS_I2S0>;
830 dma-names = "rx", "tx";
831 dmas = <&dma 3>, <&dma 3>;
832 status = "disabled";
833 };
835 i2s1: i2s@1c22400 {
836 #sound-dai-cells = <0>;
837 compatible = "allwinner,sun50i-a64-i2s",
838 "allwinner,sun8i-h3-i2s";
839 reg = <0x01c22400 0x400>;
840 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
842 clock-names = "apb", "mod";
843 resets = <&ccu RST_BUS_I2S1>;
844 dma-names = "rx", "tx";
845 dmas = <&dma 4>, <&dma 4>;
846 status = "disabled";
847 };
849 i2s2: i2s@1c22800 {
850 #sound-dai-cells = <0>;
851 compatible = "allwinner,sun50i-a64-i2s",
852 "allwinner,sun8i-h3-i2s";
853 reg = <0x01c22800 0x400>;
854 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
856 clock-names = "apb", "mod";
857 resets = <&ccu RST_BUS_I2S2>;
858 dma-names = "rx", "tx";
859 dmas = <&dma 27>, <&dma 27>;
860 status = "disabled";
861 };
863 dai: dai@1c22c00 {
864 #sound-dai-cells = <0>;
865 compatible = "allwinner,sun50i-a64-codec-i2s";
866 reg = <0x01c22c00 0x200>;
867 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
869 clock-names = "apb", "mod";
870 resets = <&ccu RST_BUS_CODEC>;
871 dmas = <&dma 15>, <&dma 15>;
872 dma-names = "rx", "tx";
873 status = "disabled";
874 };
876 codec: codec@1c22e00 {
877 #sound-dai-cells = <0>;
878 compatible = "allwinner,sun50i-a64-codec",
879 "allwinner,sun8i-a33-codec";
880 reg = <0x01c22e00 0x600>;
881 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
883 clock-names = "bus", "mod";
884 status = "disabled";
885 };
887 ths: thermal-sensor@1c25000 {
888 compatible = "allwinner,sun50i-a64-ths";
889 reg = <0x01c25000 0x100>;
890 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
891 clock-names = "bus", "mod";
892 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
893 resets = <&ccu RST_BUS_THS>;
894 nvmem-cells = <&ths_calibration>;
895 nvmem-cell-names = "calibration";
896 #thermal-sensor-cells = <1>;
897 };
899 uart0: serial@1c28000 {
900 compatible = "snps,dw-apb-uart";
901 reg = <0x01c28000 0x400>;
902 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
903 reg-shift = <2>;
904 reg-io-width = <4>;
905 clocks = <&ccu CLK_BUS_UART0>;
906 resets = <&ccu RST_BUS_UART0>;
907 status = "disabled";
908 };
910 uart1: serial@1c28400 {
911 compatible = "snps,dw-apb-uart";
912 reg = <0x01c28400 0x400>;
913 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
914 reg-shift = <2>;
915 reg-io-width = <4>;
916 clocks = <&ccu CLK_BUS_UART1>;
917 resets = <&ccu RST_BUS_UART1>;
918 status = "disabled";
919 };
921 uart2: serial@1c28800 {
922 compatible = "snps,dw-apb-uart";
923 reg = <0x01c28800 0x400>;
924 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
925 reg-shift = <2>;
926 reg-io-width = <4>;
927 clocks = <&ccu CLK_BUS_UART2>;
928 resets = <&ccu RST_BUS_UART2>;
929 status = "disabled";
930 };
932 uart3: serial@1c28c00 {
933 compatible = "snps,dw-apb-uart";
934 reg = <0x01c28c00 0x400>;
935 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
936 reg-shift = <2>;
937 reg-io-width = <4>;
938 clocks = <&ccu CLK_BUS_UART3>;
939 resets = <&ccu RST_BUS_UART3>;
940 status = "disabled";
941 };
943 uart4: serial@1c29000 {
944 compatible = "snps,dw-apb-uart";
945 reg = <0x01c29000 0x400>;
946 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
947 reg-shift = <2>;
948 reg-io-width = <4>;
949 clocks = <&ccu CLK_BUS_UART4>;
950 resets = <&ccu RST_BUS_UART4>;
951 status = "disabled";
952 };
954 i2c0: i2c@1c2ac00 {
955 compatible = "allwinner,sun6i-a31-i2c";
956 reg = <0x01c2ac00 0x400>;
957 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&ccu CLK_BUS_I2C0>;
959 resets = <&ccu RST_BUS_I2C0>;
960 pinctrl-names = "default";
961 pinctrl-0 = <&i2c0_pins>;
962 status = "disabled";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 };
967 i2c1: i2c@1c2b000 {
968 compatible = "allwinner,sun6i-a31-i2c";
969 reg = <0x01c2b000 0x400>;
970 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&ccu CLK_BUS_I2C1>;
972 resets = <&ccu RST_BUS_I2C1>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&i2c1_pins>;
975 status = "disabled";
976 #address-cells = <1>;
977 #size-cells = <0>;
978 };
980 i2c2: i2c@1c2b400 {
981 compatible = "allwinner,sun6i-a31-i2c";
982 reg = <0x01c2b400 0x400>;
983 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&ccu CLK_BUS_I2C2>;
985 resets = <&ccu RST_BUS_I2C2>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&i2c2_pins>;
988 status = "disabled";
989 #address-cells = <1>;
990 #size-cells = <0>;
991 };
993 spi0: spi@1c68000 {
994 compatible = "allwinner,sun8i-h3-spi";
995 reg = <0x01c68000 0x1000>;
996 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
998 clock-names = "ahb", "mod";
999 dmas = <&dma 23>, <&dma 23>;
1000 dma-names = "rx", "tx";
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&spi0_pins>;
1003 resets = <&ccu RST_BUS_SPI0>;
1004 status = "disabled";
1005 num-cs = <1>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 };
1010 spi1: spi@1c69000 {
1011 compatible = "allwinner,sun8i-h3-spi";
1012 reg = <0x01c69000 0x1000>;
1013 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1015 clock-names = "ahb", "mod";
1016 dmas = <&dma 24>, <&dma 24>;
1017 dma-names = "rx", "tx";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&spi1_pins>;
1020 resets = <&ccu RST_BUS_SPI1>;
1021 status = "disabled";
1022 num-cs = <1>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 };
1027 emac: ethernet@1c30000 {
1028 compatible = "allwinner,sun50i-a64-emac";
1029 syscon = <&syscon>;
1030 reg = <0x01c30000 0x10000>;
1031 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1032 interrupt-names = "macirq";
1033 resets = <&ccu RST_BUS_EMAC>;
1034 reset-names = "stmmaceth";
1035 clocks = <&ccu CLK_BUS_EMAC>;
1036 clock-names = "stmmaceth";
1037 status = "disabled";
1039 mdio: mdio {
1040 compatible = "snps,dwmac-mdio";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 };
1044 };
1046 mali: gpu@1c40000 {
1047 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1048 reg = <0x01c40000 0x10000>;
1049 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1053 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1056 interrupt-names = "gp",
1057 "gpmmu",
1058 "pp0",
1059 "ppmmu0",
1060 "pp1",
1061 "ppmmu1",
1062 "pmu";
1063 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1064 clock-names = "bus", "core";
1065 resets = <&ccu RST_BUS_GPU>;
1066 };
1068 gic: interrupt-controller@1c81000 {
1069 compatible = "arm,gic-400";
1070 reg = <0x01c81000 0x1000>,
1071 <0x01c82000 0x2000>,
1072 <0x01c84000 0x2000>,
1073 <0x01c86000 0x2000>;
1074 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1075 interrupt-controller;
1076 #interrupt-cells = <3>;
1077 };
1079 pwm: pwm@1c21400 {
1080 compatible = "allwinner,sun50i-a64-pwm",
1081 "allwinner,sun5i-a13-pwm";
1082 reg = <0x01c21400 0x400>;
1083 clocks = <&osc24M>;
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&pwm_pin>;
1086 #pwm-cells = <3>;
1087 status = "disabled";
1088 };
1090 mbus: dram-controller@1c62000 {
1091 compatible = "allwinner,sun50i-a64-mbus";
1092 reg = <0x01c62000 0x1000>;
1093 clocks = <&ccu 112>;
1094 #address-cells = <1>;
1095 #size-cells = <1>;
1096 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1097 #interconnect-cells = <1>;
1098 };
1100 csi: csi@1cb0000 {
1101 compatible = "allwinner,sun50i-a64-csi";
1102 reg = <0x01cb0000 0x1000>;
1103 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&ccu CLK_BUS_CSI>,
1105 <&ccu CLK_CSI_SCLK>,
1106 <&ccu CLK_DRAM_CSI>;
1107 clock-names = "bus", "mod", "ram";
1108 resets = <&ccu RST_BUS_CSI>;
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&csi_pins>;
1111 status = "disabled";
1112 };
1114 dsi: dsi@1ca0000 {
1115 compatible = "allwinner,sun50i-a64-mipi-dsi";
1116 reg = <0x01ca0000 0x1000>;
1117 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1119 resets = <&ccu RST_BUS_MIPI_DSI>;
1120 phys = <&dphy>;
1121 phy-names = "dphy";
1122 status = "disabled";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1126 port {
1127 dsi_in_tcon0: endpoint {
1128 remote-endpoint = <&tcon0_out_dsi>;
1129 };
1130 };
1131 };
1133 dphy: d-phy@1ca1000 {
1134 compatible = "allwinner,sun50i-a64-mipi-dphy",
1135 "allwinner,sun6i-a31-mipi-dphy";
1136 reg = <0x01ca1000 0x1000>;
1137 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1138 <&ccu CLK_DSI_DPHY>;
1139 clock-names = "bus", "mod";
1140 resets = <&ccu RST_BUS_MIPI_DSI>;
1141 status = "disabled";
1142 #phy-cells = <0>;
1143 };
1145 deinterlace: deinterlace@1e00000 {
1146 compatible = "allwinner,sun50i-a64-deinterlace",
1147 "allwinner,sun8i-h3-deinterlace";
1148 reg = <0x01e00000 0x20000>;
1149 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1150 <&ccu CLK_DEINTERLACE>,
1151 <&ccu CLK_DRAM_DEINTERLACE>;
1152 clock-names = "bus", "mod", "ram";
1153 resets = <&ccu RST_BUS_DEINTERLACE>;
1154 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1155 interconnects = <&mbus 9>;
1156 interconnect-names = "dma-mem";
1157 };
1159 hdmi: hdmi@1ee0000 {
1160 compatible = "allwinner,sun50i-a64-dw-hdmi",
1161 "allwinner,sun8i-a83t-dw-hdmi";
1162 reg = <0x01ee0000 0x10000>;
1163 reg-io-width = <1>;
1164 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1166 <&ccu CLK_HDMI>;
1167 clock-names = "iahb", "isfr", "tmds";
1168 resets = <&ccu RST_BUS_HDMI1>;
1169 reset-names = "ctrl";
1170 phys = <&hdmi_phy>;
1171 phy-names = "phy";
1172 status = "disabled";
1174 ports {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1178 hdmi_in: port@0 {
1179 reg = <0>;
1181 hdmi_in_tcon1: endpoint {
1182 remote-endpoint = <&tcon1_out_hdmi>;
1183 };
1184 };
1186 hdmi_out: port@1 {
1187 reg = <1>;
1188 };
1189 };
1190 };
1192 hdmi_phy: hdmi-phy@1ef0000 {
1193 compatible = "allwinner,sun50i-a64-hdmi-phy";
1194 reg = <0x01ef0000 0x10000>;
1195 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1196 <&ccu CLK_PLL_VIDEO0>;
1197 clock-names = "bus", "mod", "pll-0";
1198 resets = <&ccu RST_BUS_HDMI0>;
1199 reset-names = "phy";
1200 #phy-cells = <0>;
1201 };
1203 rtc: rtc@1f00000 {
1204 compatible = "allwinner,sun50i-a64-rtc",
1205 "allwinner,sun8i-h3-rtc";
1206 reg = <0x01f00000 0x400>;
1207 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1209 clock-output-names = "osc32k", "osc32k-out", "iosc";
1210 clocks = <&osc32k>;
1211 #clock-cells = <1>;
1212 };
1214 r_intc: interrupt-controller@1f00c00 {
1215 compatible = "allwinner,sun50i-a64-r-intc",
1216 "allwinner,sun6i-a31-r-intc";
1217 interrupt-controller;
1218 #interrupt-cells = <2>;
1219 reg = <0x01f00c00 0x400>;
1220 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1221 };
1223 r_ccu: clock@1f01400 {
1224 compatible = "allwinner,sun50i-a64-r-ccu";
1225 reg = <0x01f01400 0x100>;
1226 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1227 <&ccu CLK_PLL_PERIPH0>;
1228 clock-names = "hosc", "losc", "iosc", "pll-periph";
1229 #clock-cells = <1>;
1230 #reset-cells = <1>;
1231 };
1233 codec_analog: codec-analog@1f015c0 {
1234 compatible = "allwinner,sun50i-a64-codec-analog";
1235 reg = <0x01f015c0 0x4>;
1236 status = "disabled";
1237 };
1239 r_i2c: i2c@1f02400 {
1240 compatible = "allwinner,sun50i-a64-i2c",
1241 "allwinner,sun6i-a31-i2c";
1242 reg = <0x01f02400 0x400>;
1243 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&r_ccu CLK_APB0_I2C>;
1245 resets = <&r_ccu RST_APB0_I2C>;
1246 status = "disabled";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1249 };
1251 r_ir: ir@1f02000 {
1252 compatible = "allwinner,sun50i-a64-ir",
1253 "allwinner,sun6i-a31-ir";
1254 reg = <0x01f02000 0x400>;
1255 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1256 clock-names = "apb", "ir";
1257 resets = <&r_ccu RST_APB0_IR>;
1258 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&r_ir_rx_pin>;
1261 status = "disabled";
1262 };
1264 r_pwm: pwm@1f03800 {
1265 compatible = "allwinner,sun50i-a64-pwm",
1266 "allwinner,sun5i-a13-pwm";
1267 reg = <0x01f03800 0x400>;
1268 clocks = <&osc24M>;
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&r_pwm_pin>;
1271 #pwm-cells = <3>;
1272 status = "disabled";
1273 };
1275 r_pio: pinctrl@1f02c00 {
1276 compatible = "allwinner,sun50i-a64-r-pinctrl";
1277 reg = <0x01f02c00 0x400>;
1278 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1280 clock-names = "apb", "hosc", "losc";
1281 gpio-controller;
1282 #gpio-cells = <3>;
1283 interrupt-controller;
1284 #interrupt-cells = <3>;
1286 r_i2c_pl89_pins: r-i2c-pl89-pins {
1287 pins = "PL8", "PL9";
1288 function = "s_i2c";
1289 };
1291 r_ir_rx_pin: r-ir-rx-pin {
1292 pins = "PL11";
1293 function = "s_cir_rx";
1294 };
1296 r_pwm_pin: r-pwm-pin {
1297 pins = "PL10";
1298 function = "s_pwm";
1299 };
1301 r_rsb_pins: r-rsb-pins {
1302 pins = "PL0", "PL1";
1303 function = "s_rsb";
1304 };
1305 };
1307 r_rsb: rsb@1f03400 {
1308 compatible = "allwinner,sun8i-a23-rsb";
1309 reg = <0x01f03400 0x400>;
1310 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&r_ccu 6>;
1312 clock-frequency = <3000000>;
1313 resets = <&r_ccu 2>;
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&r_rsb_pins>;
1316 status = "disabled";
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 };
1321 wdt0: watchdog@1c20ca0 {
1322 compatible = "allwinner,sun50i-a64-wdt",
1323 "allwinner,sun6i-a31-wdt";
1324 reg = <0x01c20ca0 0x20>;
1325 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&osc24M>;
1327 };
1328 };
1329 };