arch/arm64/boot/dts/amlogic/meson-a1.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/gpio/meson-a1-gpio.h>
   9
  10 / {
  11         compatible = "amlogic,a1";
  12
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a35";
  24                         reg = <0x0 0x0>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a35";
  32                         reg = <0x0 0x1>;
  33                         enable-method = "psci";
  34                         next-level-cache = <&l2>;
  35                 };
  36
  37                 l2: l2-cache0 {
  38                         compatible = "cache";
  39                 };
  40         };
  41
  42         psci {
  43                 compatible = "arm,psci-1.0";
  44                 method = "smc";
  45         };
  46
  47         reserved-memory {
  48                 #address-cells = <2>;
  49                 #size-cells = <2>;
  50                 ranges;
  51
  52                 linux,cma {
  53                         compatible = "shared-dma-pool";
  54                         reusable;
  55                         size = <0x0 0x800000>;
  56                         alignment = <0x0 0x400000>;
  57                         linux,cma-default;
  58                 };
  59         };
  60
  61         sm: secure-monitor {
  62                 compatible = "amlogic,meson-gxbb-sm";
  63
  64                 pwrc: power-controller {
  65                         compatible = "amlogic,meson-a1-pwrc";
  66                         #power-domain-cells = <1>;
  67                         status = "okay";
  68                 };
  69         };
  70
  71         soc {
  72                 compatible = "simple-bus";
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 apb: bus@fe000000 {
  78                         compatible = "simple-bus";
  79                         reg = <0x0 0xfe000000 0x0 0x1000000>;
  80                         #address-cells = <2>;
  81                         #size-cells = <2>;
  82                         ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
  83
  84
  85                         reset: reset-controller@0 {
  86                                 compatible = "amlogic,meson-a1-reset";
  87                                 reg = <0x0 0x0 0x0 0x8c>;
  88                                 #reset-cells = <1>;
  89                         };
  90
  91                         periphs_pinctrl: pinctrl@0400 {
  92                                 compatible = "amlogic,meson-a1-periphs-pinctrl";
  93                                 #address-cells = <2>;
  94                                 #size-cells = <2>;
  95                                 ranges;
  96
  97                                 gpio: bank@0400 {
  98                                         reg = <0x0 0x0400 0x0 0x003c>,
  99                                               <0x0 0x0480 0x0 0x0118>;
 100                                         reg-names = "mux", "gpio";
 101                                         gpio-controller;
 102                                         #gpio-cells = <2>;
 103                                         gpio-ranges = <&periphs_pinctrl 0 0 62>;
 104                                 };
 105
 106                         };
 107
 108                         uart_AO: serial@1c00 {
 109                                 compatible = "amlogic,meson-gx-uart",
 110                                              "amlogic,meson-ao-uart";
 111                                 reg = <0x0 0x1c00 0x0 0x18>;
 112                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
 113                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 114                                 clock-names = "xtal", "pclk", "baud";
 115                                 status = "disabled";
 116                         };
 117
 118                         uart_AO_B: serial@2000 {
 119                                 compatible = "amlogic,meson-gx-uart",
 120                                              "amlogic,meson-ao-uart";
 121                                 reg = <0x0 0x2000 0x0 0x18>;
 122                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 123                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 124                                 clock-names = "xtal", "pclk", "baud";
 125                                 status = "disabled";
 126                         };
 127                 };
 128
 129                 gic: interrupt-controller@ff901000 {
 130                         compatible = "arm,gic-400";
 131                         reg = <0x0 0xff901000 0x0 0x1000>,
 132                               <0x0 0xff902000 0x0 0x2000>,
 133                               <0x0 0xff904000 0x0 0x2000>,
 134                               <0x0 0xff906000 0x0 0x2000>;
 135                         interrupt-controller;
 136                         interrupts = <GIC_PPI 9
 137                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 138                         #interrupt-cells = <3>;
 139                         #address-cells = <0>;
 140                 };
 141         };
 142
 143         timer {
 144                 compatible = "arm,armv8-timer";
 145                 interrupts = <GIC_PPI 13
 146                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 147                              <GIC_PPI 14
 148                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 149                              <GIC_PPI 11
 150                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 151                              <GIC_PPI 10
 152                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 153         };
 154
 155         xtal: xtal-clk {
 156                 compatible = "fixed-clock";
 157                 clock-frequency = <24000000>;
 158                 clock-output-names = "xtal";
 159                 #clock-cells = <0>;
 160         };
 161 };