| blob | 3746f23dc3df4cd746d6ad94adf63fb8d8665d11 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
14 / {
15 compatible = "rockchip,rk3368";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 ethernet0 = &gmac;
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 serial3 = &uart3;
32 serial4 = &uart4;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 spi2 = &spi2;
36 };
38 cpus {
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
42 cpu-map {
43 cluster0 {
44 core0 {
45 cpu = <&cpu_b0>;
46 };
47 core1 {
48 cpu = <&cpu_b1>;
49 };
50 core2 {
51 cpu = <&cpu_b2>;
52 };
53 core3 {
54 cpu = <&cpu_b3>;
55 };
56 };
58 cluster1 {
59 core0 {
60 cpu = <&cpu_l0>;
61 };
62 core1 {
63 cpu = <&cpu_l1>;
64 };
65 core2 {
66 cpu = <&cpu_l2>;
67 };
68 core3 {
69 cpu = <&cpu_l3>;
70 };
71 };
72 };
74 cpu_l0: cpu@0 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x0 0x0>;
78 enable-method = "psci";
79 #cooling-cells = <2>; /* min followed by max */
80 };
82 cpu_l1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53";
85 reg = <0x0 0x1>;
86 enable-method = "psci";
87 #cooling-cells = <2>; /* min followed by max */
88 };
90 cpu_l2: cpu@2 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53";
93 reg = <0x0 0x2>;
94 enable-method = "psci";
95 #cooling-cells = <2>; /* min followed by max */
96 };
98 cpu_l3: cpu@3 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53";
101 reg = <0x0 0x3>;
102 enable-method = "psci";
103 #cooling-cells = <2>; /* min followed by max */
104 };
106 cpu_b0: cpu@100 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53";
109 reg = <0x0 0x100>;
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
112 };
114 cpu_b1: cpu@101 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a53";
117 reg = <0x0 0x101>;
118 enable-method = "psci";
119 #cooling-cells = <2>; /* min followed by max */
120 };
122 cpu_b2: cpu@102 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a53";
125 reg = <0x0 0x102>;
126 enable-method = "psci";
127 #cooling-cells = <2>; /* min followed by max */
128 };
130 cpu_b3: cpu@103 {
131 device_type = "cpu";
132 compatible = "arm,cortex-a53";
133 reg = <0x0 0x103>;
134 enable-method = "psci";
135 #cooling-cells = <2>; /* min followed by max */
136 };
137 };
139 amba: bus {
140 compatible = "simple-bus";
141 #address-cells = <2>;
142 #size-cells = <2>;
143 ranges;
145 dmac_peri: dma-controller@ff250000 {
146 compatible = "arm,pl330", "arm,primecell";
147 reg = <0x0 0xff250000 0x0 0x4000>;
148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
150 #dma-cells = <1>;
151 arm,pl330-broken-no-flushp;
152 arm,pl330-periph-burst;
153 clocks = <&cru ACLK_DMAC_PERI>;
154 clock-names = "apb_pclk";
155 };
157 dmac_bus: dma-controller@ff600000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0x0 0xff600000 0x0 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>;
163 arm,pl330-broken-no-flushp;
164 arm,pl330-periph-burst;
165 clocks = <&cru ACLK_DMAC_BUS>;
166 clock-names = "apb_pclk";
167 };
168 };
170 arm-pmu {
171 compatible = "arm,armv8-pmuv3";
172 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
181 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
182 <&cpu_b2>, <&cpu_b3>;
183 };
185 psci {
186 compatible = "arm,psci-0.2";
187 method = "smc";
188 };
190 timer {
191 compatible = "arm,armv8-timer";
192 interrupts = <GIC_PPI 13
193 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 14
195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
196 <GIC_PPI 11
197 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 10
199 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
200 };
202 xin24m: oscillator {
203 compatible = "fixed-clock";
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
206 #clock-cells = <0>;
207 };
209 sdmmc: mmc@ff0c0000 {
210 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
211 reg = <0x0 0xff0c0000 0x0 0x4000>;
212 max-frequency = <150000000>;
213 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
214 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
215 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
216 fifo-depth = <0x100>;
217 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
218 resets = <&cru SRST_MMC0>;
219 reset-names = "reset";
220 status = "disabled";
221 };
223 sdio0: mmc@ff0d0000 {
224 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
225 reg = <0x0 0xff0d0000 0x0 0x4000>;
226 max-frequency = <150000000>;
227 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
228 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
230 fifo-depth = <0x100>;
231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
232 resets = <&cru SRST_SDIO0>;
233 reset-names = "reset";
234 status = "disabled";
235 };
237 emmc: mmc@ff0f0000 {
238 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
239 reg = <0x0 0xff0f0000 0x0 0x4000>;
240 max-frequency = <150000000>;
241 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
242 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
244 fifo-depth = <0x100>;
245 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
246 resets = <&cru SRST_EMMC>;
247 reset-names = "reset";
248 status = "disabled";
249 };
251 saradc: saradc@ff100000 {
252 compatible = "rockchip,saradc";
253 reg = <0x0 0xff100000 0x0 0x100>;
254 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
255 #io-channel-cells = <1>;
256 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
257 clock-names = "saradc", "apb_pclk";
258 resets = <&cru SRST_SARADC>;
259 reset-names = "saradc-apb";
260 status = "disabled";
261 };
263 spi0: spi@ff110000 {
264 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
265 reg = <0x0 0xff110000 0x0 0x1000>;
266 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
267 clock-names = "spiclk", "apb_pclk";
268 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 status = "disabled";
274 };
276 spi1: spi@ff120000 {
277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
278 reg = <0x0 0xff120000 0x0 0x1000>;
279 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
280 clock-names = "spiclk", "apb_pclk";
281 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 status = "disabled";
287 };
289 spi2: spi@ff130000 {
290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
291 reg = <0x0 0xff130000 0x0 0x1000>;
292 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
293 clock-names = "spiclk", "apb_pclk";
294 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
302 i2c2: i2c@ff140000 {
303 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
304 reg = <0x0 0xff140000 0x0 0x1000>;
305 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 clock-names = "i2c";
309 clocks = <&cru PCLK_I2C2>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c2_xfer>;
312 status = "disabled";
313 };
315 i2c3: i2c@ff150000 {
316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
317 reg = <0x0 0xff150000 0x0 0x1000>;
318 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 clock-names = "i2c";
322 clocks = <&cru PCLK_I2C3>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&i2c3_xfer>;
325 status = "disabled";
326 };
328 i2c4: i2c@ff160000 {
329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
330 reg = <0x0 0xff160000 0x0 0x1000>;
331 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 clock-names = "i2c";
335 clocks = <&cru PCLK_I2C4>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c4_xfer>;
338 status = "disabled";
339 };
341 i2c5: i2c@ff170000 {
342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
343 reg = <0x0 0xff170000 0x0 0x1000>;
344 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 clock-names = "i2c";
348 clocks = <&cru PCLK_I2C5>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&i2c5_xfer>;
351 status = "disabled";
352 };
354 uart0: serial@ff180000 {
355 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
356 reg = <0x0 0xff180000 0x0 0x100>;
357 clock-frequency = <24000000>;
358 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
359 clock-names = "baudclk", "apb_pclk";
360 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
361 reg-shift = <2>;
362 reg-io-width = <4>;
363 status = "disabled";
364 };
366 uart1: serial@ff190000 {
367 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
368 reg = <0x0 0xff190000 0x0 0x100>;
369 clock-frequency = <24000000>;
370 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
371 clock-names = "baudclk", "apb_pclk";
372 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
373 reg-shift = <2>;
374 reg-io-width = <4>;
375 status = "disabled";
376 };
378 uart3: serial@ff1b0000 {
379 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
380 reg = <0x0 0xff1b0000 0x0 0x100>;
381 clock-frequency = <24000000>;
382 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
383 clock-names = "baudclk", "apb_pclk";
384 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
385 reg-shift = <2>;
386 reg-io-width = <4>;
387 status = "disabled";
388 };
390 uart4: serial@ff1c0000 {
391 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
392 reg = <0x0 0xff1c0000 0x0 0x100>;
393 clock-frequency = <24000000>;
394 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
395 clock-names = "baudclk", "apb_pclk";
396 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
397 reg-shift = <2>;
398 reg-io-width = <4>;
399 status = "disabled";
400 };
402 thermal-zones {
403 cpu {
404 polling-delay-passive = <100>; /* milliseconds */
405 polling-delay = <5000>; /* milliseconds */
407 thermal-sensors = <&tsadc 0>;
409 trips {
410 cpu_alert0: cpu_alert0 {
411 temperature = <75000>; /* millicelsius */
412 hysteresis = <2000>; /* millicelsius */
413 type = "passive";
414 };
415 cpu_alert1: cpu_alert1 {
416 temperature = <80000>; /* millicelsius */
417 hysteresis = <2000>; /* millicelsius */
418 type = "passive";
419 };
420 cpu_crit: cpu_crit {
421 temperature = <95000>; /* millicelsius */
422 hysteresis = <2000>; /* millicelsius */
423 type = "critical";
424 };
425 };
427 cooling-maps {
428 map0 {
429 trip = <&cpu_alert0>;
430 cooling-device =
431 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
432 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
433 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
434 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
435 };
436 map1 {
437 trip = <&cpu_alert1>;
438 cooling-device =
439 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
440 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
441 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
442 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
443 };
444 };
445 };
447 gpu {
448 polling-delay-passive = <100>; /* milliseconds */
449 polling-delay = <5000>; /* milliseconds */
451 thermal-sensors = <&tsadc 1>;
453 trips {
454 gpu_alert0: gpu_alert0 {
455 temperature = <80000>; /* millicelsius */
456 hysteresis = <2000>; /* millicelsius */
457 type = "passive";
458 };
459 gpu_crit: gpu_crit {
460 temperature = <115000>; /* millicelsius */
461 hysteresis = <2000>; /* millicelsius */
462 type = "critical";
463 };
464 };
466 cooling-maps {
467 map0 {
468 trip = <&gpu_alert0>;
469 cooling-device =
470 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
471 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
472 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
473 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
474 };
475 };
476 };
477 };
479 tsadc: tsadc@ff280000 {
480 compatible = "rockchip,rk3368-tsadc";
481 reg = <0x0 0xff280000 0x0 0x100>;
482 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
484 clock-names = "tsadc", "apb_pclk";
485 resets = <&cru SRST_TSADC>;
486 reset-names = "tsadc-apb";
487 pinctrl-names = "init", "default", "sleep";
488 pinctrl-0 = <&otp_pin>;
489 pinctrl-1 = <&otp_out>;
490 pinctrl-2 = <&otp_pin>;
491 #thermal-sensor-cells = <1>;
492 rockchip,hw-tshut-temp = <95000>;
493 status = "disabled";
494 };
496 gmac: ethernet@ff290000 {
497 compatible = "rockchip,rk3368-gmac";
498 reg = <0x0 0xff290000 0x0 0x10000>;
499 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
500 interrupt-names = "macirq";
501 rockchip,grf = <&grf>;
502 clocks = <&cru SCLK_MAC>,
503 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
504 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
505 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
506 clock-names = "stmmaceth",
507 "mac_clk_rx", "mac_clk_tx",
508 "clk_mac_ref", "clk_mac_refout",
509 "aclk_mac", "pclk_mac";
510 status = "disabled";
511 };
513 usb_host0_ehci: usb@ff500000 {
514 compatible = "generic-ehci";
515 reg = <0x0 0xff500000 0x0 0x100>;
516 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru HCLK_HOST0>;
518 status = "disabled";
519 };
521 usb_otg: usb@ff580000 {
522 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
523 "snps,dwc2";
524 reg = <0x0 0xff580000 0x0 0x40000>;
525 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru HCLK_OTG0>;
527 clock-names = "otg";
528 dr_mode = "otg";
529 g-np-tx-fifo-size = <16>;
530 g-rx-fifo-size = <275>;
531 g-tx-fifo-size = <256 128 128 64 64 32>;
532 status = "disabled";
533 };
535 i2c0: i2c@ff650000 {
536 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
537 reg = <0x0 0xff650000 0x0 0x1000>;
538 clocks = <&cru PCLK_I2C0>;
539 clock-names = "i2c";
540 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c0_xfer>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 status = "disabled";
546 };
548 i2c1: i2c@ff660000 {
549 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
550 reg = <0x0 0xff660000 0x0 0x1000>;
551 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 clock-names = "i2c";
555 clocks = <&cru PCLK_I2C1>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c1_xfer>;
558 status = "disabled";
559 };
561 pwm0: pwm@ff680000 {
562 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
563 reg = <0x0 0xff680000 0x0 0x10>;
564 #pwm-cells = <3>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm0_pin>;
567 clocks = <&cru PCLK_PWM1>;
568 clock-names = "pwm";
569 status = "disabled";
570 };
572 pwm1: pwm@ff680010 {
573 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
574 reg = <0x0 0xff680010 0x0 0x10>;
575 #pwm-cells = <3>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm1_pin>;
578 clocks = <&cru PCLK_PWM1>;
579 clock-names = "pwm";
580 status = "disabled";
581 };
583 pwm2: pwm@ff680020 {
584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
585 reg = <0x0 0xff680020 0x0 0x10>;
586 #pwm-cells = <3>;
587 clocks = <&cru PCLK_PWM1>;
588 clock-names = "pwm";
589 status = "disabled";
590 };
592 pwm3: pwm@ff680030 {
593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
594 reg = <0x0 0xff680030 0x0 0x10>;
595 #pwm-cells = <3>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&pwm3_pin>;
598 clocks = <&cru PCLK_PWM1>;
599 clock-names = "pwm";
600 status = "disabled";
601 };
603 uart2: serial@ff690000 {
604 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
605 reg = <0x0 0xff690000 0x0 0x100>;
606 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
607 clock-names = "baudclk", "apb_pclk";
608 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&uart2_xfer>;
611 reg-shift = <2>;
612 reg-io-width = <4>;
613 status = "disabled";
614 };
616 mbox: mbox@ff6b0000 {
617 compatible = "rockchip,rk3368-mailbox";
618 reg = <0x0 0xff6b0000 0x0 0x1000>;
619 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&cru PCLK_MAILBOX>;
624 clock-names = "pclk_mailbox";
625 #mbox-cells = <1>;
626 status = "disabled";
627 };
629 pmugrf: syscon@ff738000 {
630 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
631 reg = <0x0 0xff738000 0x0 0x1000>;
633 pmu_io_domains: io-domains {
634 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
635 status = "disabled";
636 };
638 reboot-mode {
639 compatible = "syscon-reboot-mode";
640 offset = <0x200>;
641 mode-normal = <BOOT_NORMAL>;
642 mode-recovery = <BOOT_RECOVERY>;
643 mode-bootloader = <BOOT_FASTBOOT>;
644 mode-loader = <BOOT_BL_DOWNLOAD>;
645 };
646 };
648 cru: clock-controller@ff760000 {
649 compatible = "rockchip,rk3368-cru";
650 reg = <0x0 0xff760000 0x0 0x1000>;
651 rockchip,grf = <&grf>;
652 #clock-cells = <1>;
653 #reset-cells = <1>;
654 };
656 grf: syscon@ff770000 {
657 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
658 reg = <0x0 0xff770000 0x0 0x1000>;
660 io_domains: io-domains {
661 compatible = "rockchip,rk3368-io-voltage-domain";
662 status = "disabled";
663 };
664 };
666 wdt: watchdog@ff800000 {
667 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
668 reg = <0x0 0xff800000 0x0 0x100>;
669 clocks = <&cru PCLK_WDT>;
670 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
671 status = "disabled";
672 };
674 timer@ff810000 {
675 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
676 reg = <0x0 0xff810000 0x0 0x20>;
677 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
678 };
680 spdif: spdif@ff880000 {
681 compatible = "rockchip,rk3368-spdif";
682 reg = <0x0 0xff880000 0x0 0x1000>;
683 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
685 clock-names = "mclk", "hclk";
686 dmas = <&dmac_bus 3>;
687 dma-names = "tx";
688 pinctrl-names = "default";
689 pinctrl-0 = <&spdif_tx>;
690 status = "disabled";
691 };
693 i2s_2ch: i2s-2ch@ff890000 {
694 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
695 reg = <0x0 0xff890000 0x0 0x1000>;
696 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
697 clock-names = "i2s_clk", "i2s_hclk";
698 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
699 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
700 dma-names = "tx", "rx";
701 status = "disabled";
702 };
704 i2s_8ch: i2s-8ch@ff898000 {
705 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
706 reg = <0x0 0xff898000 0x0 0x1000>;
707 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
708 clock-names = "i2s_clk", "i2s_hclk";
709 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
710 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
711 dma-names = "tx", "rx";
712 pinctrl-names = "default";
713 pinctrl-0 = <&i2s_8ch_bus>;
714 status = "disabled";
715 };
717 iep_mmu: iommu@ff900800 {
718 compatible = "rockchip,iommu";
719 reg = <0x0 0xff900800 0x0 0x100>;
720 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
721 interrupt-names = "iep_mmu";
722 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
723 clock-names = "aclk", "iface";
724 #iommu-cells = <0>;
725 status = "disabled";
726 };
728 isp_mmu: iommu@ff914000 {
729 compatible = "rockchip,iommu";
730 reg = <0x0 0xff914000 0x0 0x100>,
731 <0x0 0xff915000 0x0 0x100>;
732 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
733 interrupt-names = "isp_mmu";
734 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
735 clock-names = "aclk", "iface";
736 #iommu-cells = <0>;
737 rockchip,disable-mmu-reset;
738 status = "disabled";
739 };
741 vop_mmu: iommu@ff930300 {
742 compatible = "rockchip,iommu";
743 reg = <0x0 0xff930300 0x0 0x100>;
744 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "vop_mmu";
746 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
747 clock-names = "aclk", "iface";
748 #iommu-cells = <0>;
749 status = "disabled";
750 };
752 hevc_mmu: iommu@ff9a0440 {
753 compatible = "rockchip,iommu";
754 reg = <0x0 0xff9a0440 0x0 0x40>,
755 <0x0 0xff9a0480 0x0 0x40>;
756 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "hevc_mmu";
758 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
759 clock-names = "aclk", "iface";
760 #iommu-cells = <0>;
761 status = "disabled";
762 };
764 vpu_mmu: iommu@ff9a0800 {
765 compatible = "rockchip,iommu";
766 reg = <0x0 0xff9a0800 0x0 0x100>;
767 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
769 interrupt-names = "vepu_mmu", "vdpu_mmu";
770 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
771 clock-names = "aclk", "iface";
772 #iommu-cells = <0>;
773 status = "disabled";
774 };
776 efuse256: efuse@ffb00000 {
777 compatible = "rockchip,rk3368-efuse";
778 reg = <0x0 0xffb00000 0x0 0x20>;
779 #address-cells = <1>;
780 #size-cells = <1>;
781 clocks = <&cru PCLK_EFUSE256>;
782 clock-names = "pclk_efuse";
784 cpu_leakage: cpu-leakage@17 {
785 reg = <0x17 0x1>;
786 };
787 temp_adjust: temp-adjust@1f {
788 reg = <0x1f 0x1>;
789 };
790 };
792 gic: interrupt-controller@ffb71000 {
793 compatible = "arm,gic-400";
794 interrupt-controller;
795 #interrupt-cells = <3>;
796 #address-cells = <0>;
798 reg = <0x0 0xffb71000 0x0 0x1000>,
799 <0x0 0xffb72000 0x0 0x2000>,
800 <0x0 0xffb74000 0x0 0x2000>,
801 <0x0 0xffb76000 0x0 0x2000>;
802 interrupts = <GIC_PPI 9
803 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
804 };
806 pinctrl: pinctrl {
807 compatible = "rockchip,rk3368-pinctrl";
808 rockchip,grf = <&grf>;
809 rockchip,pmu = <&pmugrf>;
810 #address-cells = <0x2>;
811 #size-cells = <0x2>;
812 ranges;
814 gpio0: gpio0@ff750000 {
815 compatible = "rockchip,gpio-bank";
816 reg = <0x0 0xff750000 0x0 0x100>;
817 clocks = <&cru PCLK_GPIO0>;
818 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
820 gpio-controller;
821 #gpio-cells = <0x2>;
823 interrupt-controller;
824 #interrupt-cells = <0x2>;
825 };
827 gpio1: gpio1@ff780000 {
828 compatible = "rockchip,gpio-bank";
829 reg = <0x0 0xff780000 0x0 0x100>;
830 clocks = <&cru PCLK_GPIO1>;
831 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
833 gpio-controller;
834 #gpio-cells = <0x2>;
836 interrupt-controller;
837 #interrupt-cells = <0x2>;
838 };
840 gpio2: gpio2@ff790000 {
841 compatible = "rockchip,gpio-bank";
842 reg = <0x0 0xff790000 0x0 0x100>;
843 clocks = <&cru PCLK_GPIO2>;
844 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
846 gpio-controller;
847 #gpio-cells = <0x2>;
849 interrupt-controller;
850 #interrupt-cells = <0x2>;
851 };
853 gpio3: gpio3@ff7a0000 {
854 compatible = "rockchip,gpio-bank";
855 reg = <0x0 0xff7a0000 0x0 0x100>;
856 clocks = <&cru PCLK_GPIO3>;
857 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
859 gpio-controller;
860 #gpio-cells = <0x2>;
862 interrupt-controller;
863 #interrupt-cells = <0x2>;
864 };
866 pcfg_pull_up: pcfg-pull-up {
867 bias-pull-up;
868 };
870 pcfg_pull_down: pcfg-pull-down {
871 bias-pull-down;
872 };
874 pcfg_pull_none: pcfg-pull-none {
875 bias-disable;
876 };
878 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
879 bias-disable;
880 drive-strength = <12>;
881 };
883 emmc {
884 emmc_clk: emmc-clk {
885 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
886 };
888 emmc_cmd: emmc-cmd {
889 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
890 };
892 emmc_pwr: emmc-pwr {
893 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
894 };
896 emmc_bus1: emmc-bus1 {
897 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
898 };
900 emmc_bus4: emmc-bus4 {
901 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
902 <1 RK_PC3 2 &pcfg_pull_up>,
903 <1 RK_PC4 2 &pcfg_pull_up>,
904 <1 RK_PC5 2 &pcfg_pull_up>;
905 };
907 emmc_bus8: emmc-bus8 {
908 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
909 <1 RK_PC3 2 &pcfg_pull_up>,
910 <1 RK_PC4 2 &pcfg_pull_up>,
911 <1 RK_PC5 2 &pcfg_pull_up>,
912 <1 RK_PC6 2 &pcfg_pull_up>,
913 <1 RK_PC7 2 &pcfg_pull_up>,
914 <1 RK_PD0 2 &pcfg_pull_up>,
915 <1 RK_PD1 2 &pcfg_pull_up>;
916 };
917 };
919 gmac {
920 rgmii_pins: rgmii-pins {
921 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
922 <3 RK_PD0 1 &pcfg_pull_none>,
923 <3 RK_PC3 1 &pcfg_pull_none>,
924 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
925 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
926 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
927 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
928 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
929 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
930 <3 RK_PB7 1 &pcfg_pull_none>,
931 <3 RK_PC0 1 &pcfg_pull_none>,
932 <3 RK_PC1 1 &pcfg_pull_none>,
933 <3 RK_PC2 1 &pcfg_pull_none>,
934 <3 RK_PD1 1 &pcfg_pull_none>,
935 <3 RK_PC4 1 &pcfg_pull_none>;
936 };
938 rmii_pins: rmii-pins {
939 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
940 <3 RK_PD0 1 &pcfg_pull_none>,
941 <3 RK_PC3 1 &pcfg_pull_none>,
942 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
943 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
944 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
945 <3 RK_PB7 1 &pcfg_pull_none>,
946 <3 RK_PC0 1 &pcfg_pull_none>,
947 <3 RK_PC4 1 &pcfg_pull_none>,
948 <3 RK_PC5 1 &pcfg_pull_none>;
949 };
950 };
952 i2c0 {
953 i2c0_xfer: i2c0-xfer {
954 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
955 <0 RK_PA7 1 &pcfg_pull_none>;
956 };
957 };
959 i2c1 {
960 i2c1_xfer: i2c1-xfer {
961 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
962 <2 RK_PC6 1 &pcfg_pull_none>;
963 };
964 };
966 i2c2 {
967 i2c2_xfer: i2c2-xfer {
968 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
969 <3 RK_PD7 2 &pcfg_pull_none>;
970 };
971 };
973 i2c3 {
974 i2c3_xfer: i2c3-xfer {
975 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
976 <1 RK_PC1 1 &pcfg_pull_none>;
977 };
978 };
980 i2c4 {
981 i2c4_xfer: i2c4-xfer {
982 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
983 <3 RK_PD1 2 &pcfg_pull_none>;
984 };
985 };
987 i2c5 {
988 i2c5_xfer: i2c5-xfer {
989 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
990 <3 RK_PD3 2 &pcfg_pull_none>;
991 };
992 };
994 i2s {
995 i2s_8ch_bus: i2s-8ch-bus {
996 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
997 <2 RK_PB5 1 &pcfg_pull_none>,
998 <2 RK_PB6 1 &pcfg_pull_none>,
999 <2 RK_PB7 1 &pcfg_pull_none>,
1000 <2 RK_PC0 1 &pcfg_pull_none>,
1001 <2 RK_PC1 1 &pcfg_pull_none>,
1002 <2 RK_PC2 1 &pcfg_pull_none>,
1003 <2 RK_PC3 1 &pcfg_pull_none>,
1004 <2 RK_PC4 1 &pcfg_pull_none>;
1005 };
1006 };
1008 pwm0 {
1009 pwm0_pin: pwm0-pin {
1010 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1011 };
1012 };
1014 pwm1 {
1015 pwm1_pin: pwm1-pin {
1016 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1017 };
1018 };
1020 pwm3 {
1021 pwm3_pin: pwm3-pin {
1022 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1023 };
1024 };
1026 sdio0 {
1027 sdio0_bus1: sdio0-bus1 {
1028 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1029 };
1031 sdio0_bus4: sdio0-bus4 {
1032 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1033 <2 RK_PD5 1 &pcfg_pull_up>,
1034 <2 RK_PD6 1 &pcfg_pull_up>,
1035 <2 RK_PD7 1 &pcfg_pull_up>;
1036 };
1038 sdio0_cmd: sdio0-cmd {
1039 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1040 };
1042 sdio0_clk: sdio0-clk {
1043 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1044 };
1046 sdio0_cd: sdio0-cd {
1047 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1048 };
1050 sdio0_wp: sdio0-wp {
1051 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1052 };
1054 sdio0_pwr: sdio0-pwr {
1055 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1056 };
1058 sdio0_bkpwr: sdio0-bkpwr {
1059 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1060 };
1062 sdio0_int: sdio0-int {
1063 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1064 };
1065 };
1067 sdmmc {
1068 sdmmc_clk: sdmmc-clk {
1069 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1070 };
1072 sdmmc_cmd: sdmmc-cmd {
1073 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1074 };
1076 sdmmc_cd: sdmmc-cd {
1077 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1078 };
1080 sdmmc_bus1: sdmmc-bus1 {
1081 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1082 };
1084 sdmmc_bus4: sdmmc-bus4 {
1085 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1086 <2 RK_PA6 1 &pcfg_pull_up>,
1087 <2 RK_PA7 1 &pcfg_pull_up>,
1088 <2 RK_PB0 1 &pcfg_pull_up>;
1089 };
1090 };
1092 spdif {
1093 spdif_tx: spdif-tx {
1094 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1095 };
1096 };
1098 spi0 {
1099 spi0_clk: spi0-clk {
1100 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1101 };
1102 spi0_cs0: spi0-cs0 {
1103 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1104 };
1105 spi0_cs1: spi0-cs1 {
1106 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1107 };
1108 spi0_tx: spi0-tx {
1109 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1110 };
1111 spi0_rx: spi0-rx {
1112 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1113 };
1114 };
1116 spi1 {
1117 spi1_clk: spi1-clk {
1118 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1119 };
1120 spi1_cs0: spi1-cs0 {
1121 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1122 };
1123 spi1_cs1: spi1-cs1 {
1124 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1125 };
1126 spi1_rx: spi1-rx {
1127 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1128 };
1129 spi1_tx: spi1-tx {
1130 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1131 };
1132 };
1134 spi2 {
1135 spi2_clk: spi2-clk {
1136 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1137 };
1138 spi2_cs0: spi2-cs0 {
1139 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1140 };
1141 spi2_rx: spi2-rx {
1142 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1143 };
1144 spi2_tx: spi2-tx {
1145 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1146 };
1147 };
1149 tsadc {
1150 otp_pin: otp-pin {
1151 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1152 };
1154 otp_out: otp-out {
1155 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1156 };
1157 };
1159 uart0 {
1160 uart0_xfer: uart0-xfer {
1161 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1162 <2 RK_PD1 1 &pcfg_pull_none>;
1163 };
1165 uart0_cts: uart0-cts {
1166 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1167 };
1169 uart0_rts: uart0-rts {
1170 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1171 };
1172 };
1174 uart1 {
1175 uart1_xfer: uart1-xfer {
1176 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1177 <0 RK_PC5 3 &pcfg_pull_none>;
1178 };
1180 uart1_cts: uart1-cts {
1181 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1182 };
1184 uart1_rts: uart1-rts {
1185 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1186 };
1187 };
1189 uart2 {
1190 uart2_xfer: uart2-xfer {
1191 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1192 <2 RK_PA5 2 &pcfg_pull_none>;
1193 };
1194 /* no rts / cts for uart2 */
1195 };
1197 uart3 {
1198 uart3_xfer: uart3-xfer {
1199 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1200 <3 RK_PD6 3 &pcfg_pull_none>;
1201 };
1203 uart3_cts: uart3-cts {
1204 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1205 };
1207 uart3_rts: uart3-rts {
1208 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1209 };
1210 };
1212 uart4 {
1213 uart4_xfer: uart4-xfer {
1214 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1215 <0 RK_PD2 3 &pcfg_pull_none>;
1216 };
1218 uart4_cts: uart4-cts {
1219 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1220 };
1222 uart4_rts: uart4-rts {
1223 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1224 };
1225 };
1226 };
1227 };