1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
7 #include <linux/kvm_host.h>
8 #include <linux/preempt.h>
9 #include <linux/export.h>
10 #include <linux/sched.h>
11 #include <linux/spinlock.h>
12 #include <linux/init.h>
13 #include <linux/memblock.h>
14 #include <linux/sizes.h>
15 #include <linux/cma.h>
16 #include <linux/bitops.h>
18 #include <asm/asm-prototypes.h>
19 #include <asm/cputable.h>
20 #include <asm/kvm_ppc.h>
21 #include <asm/kvm_book3s.h>
22 #include <asm/archrandom.h>
25 #include <asm/dbell.h>
26 #include <asm/cputhreads.h>
31 #define KVM_CMA_CHUNK_ORDER 18
33 #include "book3s_xics.h"
34 #include "book3s_xive.h"
37 * The XIVE module will populate these when it loads
39 unsigned long (*__xive_vm_h_xirr
)(struct kvm_vcpu
*vcpu
);
40 unsigned long (*__xive_vm_h_ipoll
)(struct kvm_vcpu
*vcpu
, unsigned long server
);
41 int (*__xive_vm_h_ipi
)(struct kvm_vcpu
*vcpu
, unsigned long server
,
43 int (*__xive_vm_h_cppr
)(struct kvm_vcpu
*vcpu
, unsigned long cppr
);
44 int (*__xive_vm_h_eoi
)(struct kvm_vcpu
*vcpu
, unsigned long xirr
);
45 EXPORT_SYMBOL_GPL(__xive_vm_h_xirr
);
46 EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll
);
47 EXPORT_SYMBOL_GPL(__xive_vm_h_ipi
);
48 EXPORT_SYMBOL_GPL(__xive_vm_h_cppr
);
49 EXPORT_SYMBOL_GPL(__xive_vm_h_eoi
);
52 * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206)
53 * should be power of 2.
55 #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */
57 * By default we reserve 5% of memory for hash pagetable allocation.
59 static unsigned long kvm_cma_resv_ratio
= 5;
61 static struct cma
*kvm_cma
;
63 static int __init
early_parse_kvm_cma_resv(char *p
)
65 pr_debug("%s(%s)\n", __func__
, p
);
68 return kstrtoul(p
, 0, &kvm_cma_resv_ratio
);
70 early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv
);
72 struct page
*kvm_alloc_hpt_cma(unsigned long nr_pages
)
74 VM_BUG_ON(order_base_2(nr_pages
) < KVM_CMA_CHUNK_ORDER
- PAGE_SHIFT
);
76 return cma_alloc(kvm_cma
, nr_pages
, order_base_2(HPT_ALIGN_PAGES
),
79 EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma
);
81 void kvm_free_hpt_cma(struct page
*page
, unsigned long nr_pages
)
83 cma_release(kvm_cma
, page
, nr_pages
);
85 EXPORT_SYMBOL_GPL(kvm_free_hpt_cma
);
88 * kvm_cma_reserve() - reserve area for kvm hash pagetable
90 * This function reserves memory from early allocator. It should be
91 * called by arch specific code once the memblock allocator
92 * has been activated and all other subsystems have already allocated/reserved
95 void __init
kvm_cma_reserve(void)
97 unsigned long align_size
;
98 phys_addr_t selected_size
;
101 * We need CMA reservation only when we are in HV mode
103 if (!cpu_has_feature(CPU_FTR_HVMODE
))
106 selected_size
= PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio
/ 100);
108 pr_info("%s: reserving %ld MiB for global area\n", __func__
,
109 (unsigned long)selected_size
/ SZ_1M
);
110 align_size
= HPT_ALIGN_PAGES
<< PAGE_SHIFT
;
111 cma_declare_contiguous(0, selected_size
, 0, align_size
,
112 KVM_CMA_CHUNK_ORDER
- PAGE_SHIFT
, false, "kvm_cma",
118 * Real-mode H_CONFER implementation.
119 * We check if we are the only vcpu out of this virtual core
120 * still running in the guest and not ceded. If so, we pop up
121 * to the virtual-mode implementation; if not, just return to
124 long int kvmppc_rm_h_confer(struct kvm_vcpu
*vcpu
, int target
,
125 unsigned int yield_count
)
127 struct kvmppc_vcore
*vc
= local_paca
->kvm_hstate
.kvm_vcore
;
128 int ptid
= local_paca
->kvm_hstate
.ptid
;
131 int threads_conferring
;
132 u64 stop
= get_tb() + 10 * tb_ticks_per_usec
;
133 int rv
= H_SUCCESS
; /* => don't yield */
135 set_bit(ptid
, &vc
->conferring_threads
);
136 while ((get_tb() < stop
) && !VCORE_IS_EXITING(vc
)) {
137 threads_running
= VCORE_ENTRY_MAP(vc
);
138 threads_ceded
= vc
->napping_threads
;
139 threads_conferring
= vc
->conferring_threads
;
140 if ((threads_ceded
| threads_conferring
) == threads_running
) {
141 rv
= H_TOO_HARD
; /* => do yield */
145 clear_bit(ptid
, &vc
->conferring_threads
);
150 * When running HV mode KVM we need to block certain operations while KVM VMs
151 * exist in the system. We use a counter of VMs to track this.
153 * One of the operations we need to block is onlining of secondaries, so we
154 * protect hv_vm_count with get/put_online_cpus().
156 static atomic_t hv_vm_count
;
158 void kvm_hv_vm_activated(void)
161 atomic_inc(&hv_vm_count
);
164 EXPORT_SYMBOL_GPL(kvm_hv_vm_activated
);
166 void kvm_hv_vm_deactivated(void)
169 atomic_dec(&hv_vm_count
);
172 EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated
);
174 bool kvm_hv_mode_active(void)
176 return atomic_read(&hv_vm_count
) != 0;
179 extern int hcall_real_table
[], hcall_real_table_end
[];
181 int kvmppc_hcall_impl_hv_realmode(unsigned long cmd
)
184 if (cmd
< hcall_real_table_end
- hcall_real_table
&&
185 hcall_real_table
[cmd
])
190 EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode
);
192 int kvmppc_hwrng_present(void)
194 return powernv_hwrng_present();
196 EXPORT_SYMBOL_GPL(kvmppc_hwrng_present
);
198 long kvmppc_h_random(struct kvm_vcpu
*vcpu
)
202 /* Only need to do the expensive mfmsr() on radix */
203 if (kvm_is_radix(vcpu
->kvm
) && (mfmsr() & MSR_IR
))
204 r
= powernv_get_random_long(&vcpu
->arch
.regs
.gpr
[4]);
206 r
= powernv_get_random_real_mode(&vcpu
->arch
.regs
.gpr
[4]);
214 * Send an interrupt or message to another CPU.
215 * The caller needs to include any barrier needed to order writes
216 * to memory vs. the IPI/message.
218 void kvmhv_rm_send_ipi(int cpu
)
220 void __iomem
*xics_phys
;
221 unsigned long msg
= PPC_DBELL_TYPE(PPC_DBELL_SERVER
);
223 /* For a nested hypervisor, use the XICS via hcall */
224 if (kvmhv_on_pseries()) {
225 unsigned long retbuf
[PLPAR_HCALL_BUFSIZE
];
227 plpar_hcall_raw(H_IPI
, retbuf
, get_hard_smp_processor_id(cpu
),
232 /* On POWER9 we can use msgsnd for any destination cpu. */
233 if (cpu_has_feature(CPU_FTR_ARCH_300
)) {
234 msg
|= get_hard_smp_processor_id(cpu
);
235 __asm__
__volatile__ (PPC_MSGSND(%0) : : "r" (msg
));
239 /* On POWER8 for IPIs to threads in the same core, use msgsnd. */
240 if (cpu_has_feature(CPU_FTR_ARCH_207S
) &&
241 cpu_first_thread_sibling(cpu
) ==
242 cpu_first_thread_sibling(raw_smp_processor_id())) {
243 msg
|= cpu_thread_in_core(cpu
);
244 __asm__
__volatile__ (PPC_MSGSND(%0) : : "r" (msg
));
248 /* We should never reach this */
249 if (WARN_ON_ONCE(xics_on_xive()))
252 /* Else poke the target with an IPI */
253 xics_phys
= paca_ptrs
[cpu
]->kvm_hstate
.xics_phys
;
255 __raw_rm_writeb(IPI_PRIORITY
, xics_phys
+ XICS_MFRR
);
257 opal_int_set_mfrr(get_hard_smp_processor_id(cpu
), IPI_PRIORITY
);
261 * The following functions are called from the assembly code
262 * in book3s_hv_rmhandlers.S.
264 static void kvmhv_interrupt_vcore(struct kvmppc_vcore
*vc
, int active
)
268 /* Order setting of exit map vs. msgsnd/IPI */
270 for (; active
; active
>>= 1, ++cpu
)
272 kvmhv_rm_send_ipi(cpu
);
275 void kvmhv_commence_exit(int trap
)
277 struct kvmppc_vcore
*vc
= local_paca
->kvm_hstate
.kvm_vcore
;
278 int ptid
= local_paca
->kvm_hstate
.ptid
;
279 struct kvm_split_mode
*sip
= local_paca
->kvm_hstate
.kvm_split_mode
;
283 /* Set our bit in the threads-exiting-guest map in the 0xff00
284 bits of vcore->entry_exit_map */
287 ee
= vc
->entry_exit_map
;
288 } while (cmpxchg(&vc
->entry_exit_map
, ee
, ee
| me
) != ee
);
290 /* Are we the first here? */
295 * Trigger the other threads in this vcore to exit the guest.
296 * If this is a hypervisor decrementer interrupt then they
297 * will be already on their way out of the guest.
299 if (trap
!= BOOK3S_INTERRUPT_HV_DECREMENTER
)
300 kvmhv_interrupt_vcore(vc
, ee
& ~(1 << ptid
));
303 * If we are doing dynamic micro-threading, interrupt the other
304 * subcores to pull them out of their guests too.
309 for (i
= 0; i
< MAX_SUBCORES
; ++i
) {
314 ee
= vc
->entry_exit_map
;
315 /* Already asked to exit? */
318 } while (cmpxchg(&vc
->entry_exit_map
, ee
,
319 ee
| VCORE_EXIT_REQ
) != ee
);
321 kvmhv_interrupt_vcore(vc
, ee
);
325 * On POWER9 when running a HPT guest on a radix host (sip != NULL),
326 * we have to interrupt inactive CPU threads to get them to
327 * restore the host LPCR value.
330 if (cmpxchg(&sip
->do_restore
, 0, 1) == 0) {
331 vc
= local_paca
->kvm_hstate
.kvm_vcore
;
332 cpu0
= vc
->pcpu
+ ptid
- local_paca
->kvm_hstate
.tid
;
333 for (t
= 1; t
< threads_per_core
; ++t
) {
335 kvmhv_rm_send_ipi(cpu0
+ t
);
341 struct kvmppc_host_rm_ops
*kvmppc_host_rm_ops_hv
;
342 EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv
);
344 #ifdef CONFIG_KVM_XICS
345 static struct kvmppc_irq_map
*get_irqmap(struct kvmppc_passthru_irqmap
*pimap
,
351 * We access the mapped array here without a lock. That
352 * is safe because we never reduce the number of entries
353 * in the array and we never change the v_hwirq field of
354 * an entry once it is set.
356 * We have also carefully ordered the stores in the writer
357 * and the loads here in the reader, so that if we find a matching
358 * hwirq here, the associated GSI and irq_desc fields are valid.
360 for (i
= 0; i
< pimap
->n_mapped
; i
++) {
361 if (xisr
== pimap
->mapped
[i
].r_hwirq
) {
363 * Order subsequent reads in the caller to serialize
367 return &pimap
->mapped
[i
];
374 * If we have an interrupt that's not an IPI, check if we have a
375 * passthrough adapter and if so, check if this external interrupt
376 * is for the adapter.
377 * We will attempt to deliver the IRQ directly to the target VCPU's
378 * ICP, the virtual ICP (based on affinity - the xive value in ICS).
380 * If the delivery fails or if this is not for a passthrough adapter,
381 * return to the host to handle this interrupt. We earlier
382 * saved a copy of the XIRR in the PACA, it will be picked up by
383 * the host ICP driver.
385 static int kvmppc_check_passthru(u32 xisr
, __be32 xirr
, bool *again
)
387 struct kvmppc_passthru_irqmap
*pimap
;
388 struct kvmppc_irq_map
*irq_map
;
389 struct kvm_vcpu
*vcpu
;
391 vcpu
= local_paca
->kvm_hstate
.kvm_vcpu
;
394 pimap
= kvmppc_get_passthru_irqmap(vcpu
->kvm
);
397 irq_map
= get_irqmap(pimap
, xisr
);
401 /* We're handling this interrupt, generic code doesn't need to */
402 local_paca
->kvm_hstate
.saved_xirr
= 0;
404 return kvmppc_deliver_irq_passthru(vcpu
, xirr
, irq_map
, pimap
, again
);
408 static inline int kvmppc_check_passthru(u32 xisr
, __be32 xirr
, bool *again
)
415 * Determine what sort of external interrupt is pending (if any).
417 * 0 if no interrupt is pending
418 * 1 if an interrupt is pending that needs to be handled by the host
419 * 2 Passthrough that needs completion in the host
420 * -1 if there was a guest wakeup IPI (which has now been cleared)
421 * -2 if there is PCI passthrough external interrupt that was handled
423 static long kvmppc_read_one_intr(bool *again
);
425 long kvmppc_read_intr(void)
436 rc
= kvmppc_read_one_intr(&again
);
437 if (rc
&& (ret
== 0 || rc
> ret
))
443 static long kvmppc_read_one_intr(bool *again
)
445 void __iomem
*xics_phys
;
455 /* see if a host IPI is pending */
456 host_ipi
= local_paca
->kvm_hstate
.host_ipi
;
460 /* Now read the interrupt from the ICP */
461 if (kvmhv_on_pseries()) {
462 unsigned long retbuf
[PLPAR_HCALL_BUFSIZE
];
464 rc
= plpar_hcall_raw(H_XIRR
, retbuf
, 0xFF);
465 xirr
= cpu_to_be32(retbuf
[0]);
467 xics_phys
= local_paca
->kvm_hstate
.xics_phys
;
470 rc
= opal_int_get_xirr(&xirr
, false);
472 xirr
= __raw_rm_readl(xics_phys
+ XICS_XIRR
);
478 * Save XIRR for later. Since we get control in reverse endian
479 * on LE systems, save it byte reversed and fetch it back in
480 * host endian. Note that xirr is the value read from the
481 * XIRR register, while h_xirr is the host endian version.
483 h_xirr
= be32_to_cpu(xirr
);
484 local_paca
->kvm_hstate
.saved_xirr
= h_xirr
;
485 xisr
= h_xirr
& 0xffffff;
487 * Ensure that the store/load complete to guarantee all side
488 * effects of loading from XIRR has completed
492 /* if nothing pending in the ICP */
496 /* We found something in the ICP...
498 * If it is an IPI, clear the MFRR and EOI it.
500 if (xisr
== XICS_IPI
) {
502 if (kvmhv_on_pseries()) {
503 unsigned long retbuf
[PLPAR_HCALL_BUFSIZE
];
505 plpar_hcall_raw(H_IPI
, retbuf
,
506 hard_smp_processor_id(), 0xff);
507 plpar_hcall_raw(H_EOI
, retbuf
, h_xirr
);
508 } else if (xics_phys
) {
509 __raw_rm_writeb(0xff, xics_phys
+ XICS_MFRR
);
510 __raw_rm_writel(xirr
, xics_phys
+ XICS_XIRR
);
512 opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
513 rc
= opal_int_eoi(h_xirr
);
515 /* If rc > 0, there is another interrupt pending */
519 * Need to ensure side effects of above stores
520 * complete before proceeding.
525 * We need to re-check host IPI now in case it got set in the
526 * meantime. If it's clear, we bounce the interrupt to the
529 host_ipi
= local_paca
->kvm_hstate
.host_ipi
;
530 if (unlikely(host_ipi
!= 0)) {
531 /* We raced with the host,
532 * we need to resend that IPI, bummer
534 if (kvmhv_on_pseries()) {
535 unsigned long retbuf
[PLPAR_HCALL_BUFSIZE
];
537 plpar_hcall_raw(H_IPI
, retbuf
,
538 hard_smp_processor_id(),
540 } else if (xics_phys
)
541 __raw_rm_writeb(IPI_PRIORITY
,
542 xics_phys
+ XICS_MFRR
);
544 opal_int_set_mfrr(hard_smp_processor_id(),
546 /* Let side effects complete */
551 /* OK, it's an IPI for us */
552 local_paca
->kvm_hstate
.saved_xirr
= 0;
556 return kvmppc_check_passthru(xisr
, xirr
, again
);
559 #ifdef CONFIG_KVM_XICS
560 static inline bool is_rm(void)
562 return !(mfmsr() & MSR_DR
);
565 unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu
*vcpu
)
567 if (!kvmppc_xics_enabled(vcpu
))
569 if (xics_on_xive()) {
571 return xive_rm_h_xirr(vcpu
);
572 if (unlikely(!__xive_vm_h_xirr
))
573 return H_NOT_AVAILABLE
;
574 return __xive_vm_h_xirr(vcpu
);
576 return xics_rm_h_xirr(vcpu
);
579 unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu
*vcpu
)
581 if (!kvmppc_xics_enabled(vcpu
))
583 vcpu
->arch
.regs
.gpr
[5] = get_tb();
584 if (xics_on_xive()) {
586 return xive_rm_h_xirr(vcpu
);
587 if (unlikely(!__xive_vm_h_xirr
))
588 return H_NOT_AVAILABLE
;
589 return __xive_vm_h_xirr(vcpu
);
591 return xics_rm_h_xirr(vcpu
);
594 unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu
*vcpu
, unsigned long server
)
596 if (!kvmppc_xics_enabled(vcpu
))
598 if (xics_on_xive()) {
600 return xive_rm_h_ipoll(vcpu
, server
);
601 if (unlikely(!__xive_vm_h_ipoll
))
602 return H_NOT_AVAILABLE
;
603 return __xive_vm_h_ipoll(vcpu
, server
);
608 int kvmppc_rm_h_ipi(struct kvm_vcpu
*vcpu
, unsigned long server
,
611 if (!kvmppc_xics_enabled(vcpu
))
613 if (xics_on_xive()) {
615 return xive_rm_h_ipi(vcpu
, server
, mfrr
);
616 if (unlikely(!__xive_vm_h_ipi
))
617 return H_NOT_AVAILABLE
;
618 return __xive_vm_h_ipi(vcpu
, server
, mfrr
);
620 return xics_rm_h_ipi(vcpu
, server
, mfrr
);
623 int kvmppc_rm_h_cppr(struct kvm_vcpu
*vcpu
, unsigned long cppr
)
625 if (!kvmppc_xics_enabled(vcpu
))
627 if (xics_on_xive()) {
629 return xive_rm_h_cppr(vcpu
, cppr
);
630 if (unlikely(!__xive_vm_h_cppr
))
631 return H_NOT_AVAILABLE
;
632 return __xive_vm_h_cppr(vcpu
, cppr
);
634 return xics_rm_h_cppr(vcpu
, cppr
);
637 int kvmppc_rm_h_eoi(struct kvm_vcpu
*vcpu
, unsigned long xirr
)
639 if (!kvmppc_xics_enabled(vcpu
))
641 if (xics_on_xive()) {
643 return xive_rm_h_eoi(vcpu
, xirr
);
644 if (unlikely(!__xive_vm_h_eoi
))
645 return H_NOT_AVAILABLE
;
646 return __xive_vm_h_eoi(vcpu
, xirr
);
648 return xics_rm_h_eoi(vcpu
, xirr
);
650 #endif /* CONFIG_KVM_XICS */
652 void kvmppc_bad_interrupt(struct pt_regs
*regs
)
655 * 100 could happen at any time, 200 can happen due to invalid real
656 * address access for example (or any time due to a hardware problem).
658 if (TRAP(regs
) == 0x100) {
659 get_paca()->in_nmi
++;
660 system_reset_exception(regs
);
661 get_paca()->in_nmi
--;
662 } else if (TRAP(regs
) == 0x200) {
663 machine_check_exception(regs
);
665 die("Bad interrupt in KVM entry/exit code", regs
, SIGABRT
);
667 panic("Bad KVM trap");
671 * Functions used to switch LPCR HR and UPRT bits on all threads
672 * when entering and exiting HPT guests on a radix host.
675 #define PHASE_REALMODE 1 /* in real mode */
676 #define PHASE_SET_LPCR 2 /* have set LPCR */
677 #define PHASE_OUT_OF_GUEST 4 /* have finished executing in guest */
678 #define PHASE_RESET_LPCR 8 /* have reset LPCR to host value */
680 #define ALL(p) (((p) << 24) | ((p) << 16) | ((p) << 8) | (p))
682 static void wait_for_sync(struct kvm_split_mode
*sip
, int phase
)
684 int thr
= local_paca
->kvm_hstate
.tid
;
686 sip
->lpcr_sync
.phase
[thr
] |= phase
;
688 while ((sip
->lpcr_sync
.allphases
& phase
) != phase
) {
695 void kvmhv_p9_set_lpcr(struct kvm_split_mode
*sip
)
698 unsigned long rb
, set
;
700 /* wait for every other thread to get to real mode */
701 wait_for_sync(sip
, PHASE_REALMODE
);
703 /* Set LPCR and LPIDR */
704 mtspr(SPRN_LPCR
, sip
->lpcr_req
);
705 mtspr(SPRN_LPID
, sip
->lpidr_req
);
709 * P10 will flush all the congruence class with a single tlbiel
711 if (cpu_has_feature(CPU_FTR_ARCH_31
))
714 num_sets
= POWER9_TLB_SETS_RADIX
;
716 /* Invalidate the TLB on thread 0 */
717 if (local_paca
->kvm_hstate
.tid
== 0) {
719 asm volatile("ptesync" : : : "memory");
720 for (set
= 0; set
< num_sets
; ++set
) {
721 rb
= TLBIEL_INVAL_SET_LPID
+
722 (set
<< TLBIEL_INVAL_SET_SHIFT
);
723 asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : :
726 asm volatile("ptesync" : : : "memory");
729 /* indicate that we have done so and wait for others */
730 wait_for_sync(sip
, PHASE_SET_LPCR
);
731 /* order read of sip->lpcr_sync.allphases vs. sip->do_set */
736 * Called when a thread that has been in the guest needs
737 * to reload the host LPCR value - but only on POWER9 when
738 * running a HPT guest on a radix host.
740 void kvmhv_p9_restore_lpcr(struct kvm_split_mode
*sip
)
742 /* we're out of the guest... */
743 wait_for_sync(sip
, PHASE_OUT_OF_GUEST
);
746 mtspr(SPRN_LPCR
, sip
->host_lpcr
);
749 if (local_paca
->kvm_hstate
.tid
== 0) {
751 smp_wmb(); /* order store of do_restore vs. phase */
754 wait_for_sync(sip
, PHASE_RESET_LPCR
);
756 local_paca
->kvm_hstate
.kvm_split_mode
= NULL
;
759 static void kvmppc_end_cede(struct kvm_vcpu
*vcpu
)
761 vcpu
->arch
.ceded
= 0;
762 if (vcpu
->arch
.timer_running
) {
763 hrtimer_try_to_cancel(&vcpu
->arch
.dec_timer
);
764 vcpu
->arch
.timer_running
= 0;
768 void kvmppc_set_msr_hv(struct kvm_vcpu
*vcpu
, u64 msr
)
771 * Check for illegal transactional state bit combination
772 * and if we find it, force the TS field to a safe state.
774 if ((msr
& MSR_TS_MASK
) == MSR_TS_MASK
)
776 vcpu
->arch
.shregs
.msr
= msr
;
777 kvmppc_end_cede(vcpu
);
779 EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv
);
781 static void inject_interrupt(struct kvm_vcpu
*vcpu
, int vec
, u64 srr1_flags
)
783 unsigned long msr
, pc
, new_msr
, new_pc
;
785 msr
= kvmppc_get_msr(vcpu
);
786 pc
= kvmppc_get_pc(vcpu
);
787 new_msr
= vcpu
->arch
.intr_msr
;
790 /* If transactional, change to suspend mode on IRQ delivery */
791 if (MSR_TM_TRANSACTIONAL(msr
))
794 new_msr
|= msr
& MSR_TS_MASK
;
797 * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and
798 * applicable. AIL=2 is not supported.
800 * AIL does not apply to SRESET, MCE, or HMI (which is never
801 * delivered to the guest), and does not apply if IR=0 or DR=0.
803 if (vec
!= BOOK3S_INTERRUPT_SYSTEM_RESET
&&
804 vec
!= BOOK3S_INTERRUPT_MACHINE_CHECK
&&
805 (vcpu
->arch
.vcore
->lpcr
& LPCR_AIL
) == LPCR_AIL_3
&&
806 (msr
& (MSR_IR
|MSR_DR
)) == (MSR_IR
|MSR_DR
) ) {
807 new_msr
|= MSR_IR
| MSR_DR
;
808 new_pc
+= 0xC000000000004000ULL
;
811 kvmppc_set_srr0(vcpu
, pc
);
812 kvmppc_set_srr1(vcpu
, (msr
& SRR1_MSR_BITS
) | srr1_flags
);
813 kvmppc_set_pc(vcpu
, new_pc
);
814 vcpu
->arch
.shregs
.msr
= new_msr
;
817 void kvmppc_inject_interrupt_hv(struct kvm_vcpu
*vcpu
, int vec
, u64 srr1_flags
)
819 inject_interrupt(vcpu
, vec
, srr1_flags
);
820 kvmppc_end_cede(vcpu
);
822 EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv
);
825 * Is there a PRIV_DOORBELL pending for the guest (on POWER9)?
826 * Can we inject a Decrementer or a External interrupt?
828 void kvmppc_guest_entry_inject_int(struct kvm_vcpu
*vcpu
)
833 /* Insert EXTERNAL bit into LPCR at the MER bit position */
834 ext
= (vcpu
->arch
.pending_exceptions
>> BOOK3S_IRQPRIO_EXTERNAL
) & 1;
835 lpcr
= mfspr(SPRN_LPCR
);
836 lpcr
|= ext
<< LPCR_MER_SH
;
837 mtspr(SPRN_LPCR
, lpcr
);
840 if (vcpu
->arch
.shregs
.msr
& MSR_EE
) {
842 inject_interrupt(vcpu
, BOOK3S_INTERRUPT_EXTERNAL
, 0);
844 long int dec
= mfspr(SPRN_DEC
);
845 if (!(lpcr
& LPCR_LD
))
848 inject_interrupt(vcpu
,
849 BOOK3S_INTERRUPT_DECREMENTER
, 0);
853 if (vcpu
->arch
.doorbell_request
) {
854 mtspr(SPRN_DPDES
, 1);
855 vcpu
->arch
.vcore
->dpdes
= 1;
857 vcpu
->arch
.doorbell_request
= 0;
861 static void flush_guest_tlb(struct kvm
*kvm
)
863 unsigned long rb
, set
;
865 rb
= PPC_BIT(52); /* IS = 2 */
866 if (kvm_is_radix(kvm
)) {
867 /* R=1 PRS=1 RIC=2 */
868 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
869 : : "r" (rb
), "i" (1), "i" (1), "i" (2),
871 for (set
= 1; set
< kvm
->arch
.tlb_sets
; ++set
) {
872 rb
+= PPC_BIT(51); /* increment set number */
873 /* R=1 PRS=1 RIC=0 */
874 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
875 : : "r" (rb
), "i" (1), "i" (1), "i" (0),
878 asm volatile("ptesync": : :"memory");
879 asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST
: : :"memory");
881 for (set
= 0; set
< kvm
->arch
.tlb_sets
; ++set
) {
882 /* R=0 PRS=0 RIC=0 */
883 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
884 : : "r" (rb
), "i" (0), "i" (0), "i" (0),
886 rb
+= PPC_BIT(51); /* increment set number */
888 asm volatile("ptesync": : :"memory");
889 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT
: : :"memory");
893 void kvmppc_check_need_tlb_flush(struct kvm
*kvm
, int pcpu
,
894 struct kvm_nested_guest
*nested
)
896 cpumask_t
*need_tlb_flush
;
899 * On POWER9, individual threads can come in here, but the
900 * TLB is shared between the 4 threads in a core, hence
901 * invalidating on one thread invalidates for all.
902 * Thus we make all 4 threads use the same bit.
904 if (cpu_has_feature(CPU_FTR_ARCH_300
))
905 pcpu
= cpu_first_thread_sibling(pcpu
);
908 need_tlb_flush
= &nested
->need_tlb_flush
;
910 need_tlb_flush
= &kvm
->arch
.need_tlb_flush
;
912 if (cpumask_test_cpu(pcpu
, need_tlb_flush
)) {
913 flush_guest_tlb(kvm
);
915 /* Clear the bit after the TLB flush */
916 cpumask_clear_cpu(pcpu
, need_tlb_flush
);
919 EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush
);