arch/powerpc/perf/e6500-pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Performance counter support for e6500 family processors.
   4  *
   5  * Author: Priyanka Jain, Priyanka.Jain@freescale.com
   6  * Based on e500-pmu.c
   7  * Copyright 2013 Freescale Semiconductor, Inc.
   8  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   9  */
  10
  11 #include <linux/string.h>
  12 #include <linux/perf_event.h>
  13 #include <asm/reg.h>
  14 #include <asm/cputable.h>
  15
  16 /*
  17  * Map of generic hardware event types to hardware events
  18  * Zero if unsupported
  19  */
  20 static int e6500_generic_events[] = {
  21         [PERF_COUNT_HW_CPU_CYCLES] = 1,
  22         [PERF_COUNT_HW_INSTRUCTIONS] = 2,
  23         [PERF_COUNT_HW_CACHE_MISSES] = 221,
  24         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
  25         [PERF_COUNT_HW_BRANCH_MISSES] = 15,
  26 };
  27
  28 #define C(x)    PERF_COUNT_HW_CACHE_##x
  29
  30 /*
  31  * Table of generalized cache-related events.
  32  * 0 means not supported, -1 means nonsensical, other values
  33  * are event codes.
  34  */
  35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
  36         [C(L1D)] = {
  37                                 /*RESULT_ACCESS         RESULT_MISS */
  38                 [C(OP_READ)] = {        27,             222     },
  39                 [C(OP_WRITE)] = {       28,             223     },
  40                 [C(OP_PREFETCH)] = {    29,             0       },
  41         },
  42         [C(L1I)] = {
  43                                 /*RESULT_ACCESS         RESULT_MISS */
  44                 [C(OP_READ)] = {        2,              254     },
  45                 [C(OP_WRITE)] = {       -1,             -1      },
  46                 [C(OP_PREFETCH)] = {    37,             0       },
  47         },
  48         /*
  49          * Assuming LL means L2, it's not a good match for this model.
  50          * It does not have separate read/write events (but it does have
  51          * separate instruction/data events).
  52          */
  53         [C(LL)] = {
  54                                 /*RESULT_ACCESS         RESULT_MISS */
  55                 [C(OP_READ)] = {        0,              0       },
  56                 [C(OP_WRITE)] = {       0,              0       },
  57                 [C(OP_PREFETCH)] = {    0,              0       },
  58         },
  59         /*
  60          * There are data/instruction MMU misses, but that's a miss on
  61          * the chip's internal level-one TLB which is probably not
  62          * what the user wants.  Instead, unified level-two TLB misses
  63          * are reported here.
  64          */
  65         [C(DTLB)] = {
  66                                 /*RESULT_ACCESS         RESULT_MISS */
  67                 [C(OP_READ)] = {        26,             66      },
  68                 [C(OP_WRITE)] = {       -1,             -1      },
  69                 [C(OP_PREFETCH)] = {    -1,             -1      },
  70         },
  71         [C(BPU)] = {
  72                                 /*RESULT_ACCESS         RESULT_MISS */
  73                 [C(OP_READ)] = {        12,             15      },
  74                 [C(OP_WRITE)] = {       -1,             -1      },
  75                 [C(OP_PREFETCH)] = {    -1,             -1      },
  76         },
  77         [C(NODE)] = {
  78                                 /* RESULT_ACCESS        RESULT_MISS */
  79                 [C(OP_READ)] = {        -1,             -1      },
  80                 [C(OP_WRITE)] = {       -1,             -1      },
  81                 [C(OP_PREFETCH)] = {    -1,             -1      },
  82         },
  83 };
  84
  85 static int num_events = 512;
  86
  87 /* Upper half of event id is PMLCb, for threshold events */
  88 static u64 e6500_xlate_event(u64 event_id)
  89 {
  90         u32 event_low = (u32)event_id;
  91         if (event_low >= num_events ||
  92                 (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)))
  93                 return 0;
  94
  95         return FSL_EMB_EVENT_VALID;
  96 }
  97
  98 static struct fsl_emb_pmu e6500_pmu = {
  99         .name                   = "e6500 family",
 100         .n_counter              = 6,
 101         .n_restricted           = 0,
 102         .xlate_event            = e6500_xlate_event,
 103         .n_generic              = ARRAY_SIZE(e6500_generic_events),
 104         .generic_events         = e6500_generic_events,
 105         .cache_events           = &e6500_cache_events,
 106 };
 107
 108 static int init_e6500_pmu(void)
 109 {
 110         if (!cur_cpu_spec->oprofile_cpu_type ||
 111                 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e6500"))
 112                 return -ENODEV;
 113
 114         return register_fsl_emb_pmu(&e6500_pmu);
 115 }
 116
 117 early_initcall(init_e6500_pmu);