1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2007 Alan Stern
5 * Copyright (C) 2009 IBM Corporation
6 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
8 * Authors: Alan Stern <stern@rowland.harvard.edu>
9 * K.Prasad <prasad@linux.vnet.ibm.com>
10 * Frederic Weisbecker <fweisbec@gmail.com>
14 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
15 * using the CPU's debug registers.
18 #include <linux/perf_event.h>
19 #include <linux/hw_breakpoint.h>
20 #include <linux/irqflags.h>
21 #include <linux/notifier.h>
22 #include <linux/kallsyms.h>
23 #include <linux/kprobes.h>
24 #include <linux/percpu.h>
25 #include <linux/kdebug.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/sched.h>
29 #include <linux/smp.h>
31 #include <asm/hw_breakpoint.h>
32 #include <asm/processor.h>
33 #include <asm/debugreg.h>
36 #include <asm/tlbflush.h>
38 /* Per cpu debug control register value */
39 DEFINE_PER_CPU(unsigned long, cpu_dr7
);
40 EXPORT_PER_CPU_SYMBOL(cpu_dr7
);
42 /* Per cpu debug address registers values */
43 static DEFINE_PER_CPU(unsigned long, cpu_debugreg
[HBP_NUM
]);
46 * Stores the breakpoints currently in use on each breakpoint address
47 * register for each cpus
49 static DEFINE_PER_CPU(struct perf_event
*, bp_per_reg
[HBP_NUM
]);
52 static inline unsigned long
53 __encode_dr7(int drnum
, unsigned int len
, unsigned int type
)
55 unsigned long bp_info
;
57 bp_info
= (len
| type
) & 0xf;
58 bp_info
<<= (DR_CONTROL_SHIFT
+ drnum
* DR_CONTROL_SIZE
);
59 bp_info
|= (DR_GLOBAL_ENABLE
<< (drnum
* DR_ENABLE_SIZE
));
65 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
66 * as stored in debug register 7.
68 unsigned long encode_dr7(int drnum
, unsigned int len
, unsigned int type
)
70 return __encode_dr7(drnum
, len
, type
) | DR_GLOBAL_SLOWDOWN
;
74 * Decode the length and type bits for a particular breakpoint as
75 * stored in debug register 7. Return the "enabled" status.
77 int decode_dr7(unsigned long dr7
, int bpnum
, unsigned *len
, unsigned *type
)
79 int bp_info
= dr7
>> (DR_CONTROL_SHIFT
+ bpnum
* DR_CONTROL_SIZE
);
81 *len
= (bp_info
& 0xc) | 0x40;
82 *type
= (bp_info
& 0x3) | 0x80;
84 return (dr7
>> (bpnum
* DR_ENABLE_SIZE
)) & 0x3;
88 * Install a perf counter breakpoint.
90 * We seek a free debug address register and use it for this
91 * breakpoint. Eventually we enable it in the debug control register.
93 * Atomic: we hold the counter->ctx->lock and we only handle variables
94 * and registers local to this cpu.
96 int arch_install_hw_breakpoint(struct perf_event
*bp
)
98 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
102 lockdep_assert_irqs_disabled();
104 for (i
= 0; i
< HBP_NUM
; i
++) {
105 struct perf_event
**slot
= this_cpu_ptr(&bp_per_reg
[i
]);
113 if (WARN_ONCE(i
== HBP_NUM
, "Can't find any breakpoint slot"))
116 set_debugreg(info
->address
, i
);
117 __this_cpu_write(cpu_debugreg
[i
], info
->address
);
119 dr7
= this_cpu_ptr(&cpu_dr7
);
120 *dr7
|= encode_dr7(i
, info
->len
, info
->type
);
123 * Ensure we first write cpu_dr7 before we set the DR7 register.
124 * This ensures an NMI never see cpu_dr7 0 when DR7 is not.
128 set_debugreg(*dr7
, 7);
130 set_dr_addr_mask(info
->mask
, i
);
136 * Uninstall the breakpoint contained in the given counter.
138 * First we search the debug address register it uses and then we disable
141 * Atomic: we hold the counter->ctx->lock and we only handle variables
142 * and registers local to this cpu.
144 void arch_uninstall_hw_breakpoint(struct perf_event
*bp
)
146 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
150 lockdep_assert_irqs_disabled();
152 for (i
= 0; i
< HBP_NUM
; i
++) {
153 struct perf_event
**slot
= this_cpu_ptr(&bp_per_reg
[i
]);
161 if (WARN_ONCE(i
== HBP_NUM
, "Can't find any breakpoint slot"))
164 dr7
= this_cpu_read(cpu_dr7
);
165 dr7
&= ~__encode_dr7(i
, info
->len
, info
->type
);
167 set_debugreg(dr7
, 7);
169 set_dr_addr_mask(0, i
);
172 * Ensure the write to cpu_dr7 is after we've set the DR7 register.
173 * This ensures an NMI never see cpu_dr7 0 when DR7 is not.
177 this_cpu_write(cpu_dr7
, dr7
);
180 static int arch_bp_generic_len(int x86_len
)
183 case X86_BREAKPOINT_LEN_1
:
184 return HW_BREAKPOINT_LEN_1
;
185 case X86_BREAKPOINT_LEN_2
:
186 return HW_BREAKPOINT_LEN_2
;
187 case X86_BREAKPOINT_LEN_4
:
188 return HW_BREAKPOINT_LEN_4
;
190 case X86_BREAKPOINT_LEN_8
:
191 return HW_BREAKPOINT_LEN_8
;
198 int arch_bp_generic_fields(int x86_len
, int x86_type
,
199 int *gen_len
, int *gen_type
)
205 case X86_BREAKPOINT_EXECUTE
:
206 if (x86_len
!= X86_BREAKPOINT_LEN_X
)
209 *gen_type
= HW_BREAKPOINT_X
;
210 *gen_len
= sizeof(long);
212 case X86_BREAKPOINT_WRITE
:
213 *gen_type
= HW_BREAKPOINT_W
;
215 case X86_BREAKPOINT_RW
:
216 *gen_type
= HW_BREAKPOINT_W
| HW_BREAKPOINT_R
;
223 len
= arch_bp_generic_len(x86_len
);
232 * Check for virtual address in kernel space.
234 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint
*hw
)
240 len
= arch_bp_generic_len(hw
->len
);
241 WARN_ON_ONCE(len
< 0);
244 * We don't need to worry about va + len - 1 overflowing:
245 * we already require that va is aligned to a multiple of len.
247 return (va
>= TASK_SIZE_MAX
) || ((va
+ len
- 1) >= TASK_SIZE_MAX
);
251 * Checks whether the range [addr, end], overlaps the area [base, base + size).
253 static inline bool within_area(unsigned long addr
, unsigned long end
,
254 unsigned long base
, unsigned long size
)
256 return end
>= base
&& addr
< (base
+ size
);
260 * Checks whether the range from addr to end, inclusive, overlaps the fixed
261 * mapped CPU entry area range or other ranges used for CPU entry.
263 static inline bool within_cpu_entry(unsigned long addr
, unsigned long end
)
267 /* CPU entry erea is always used for CPU entry */
268 if (within_area(addr
, end
, CPU_ENTRY_AREA_BASE
,
269 CPU_ENTRY_AREA_TOTAL_SIZE
))
272 for_each_possible_cpu(cpu
) {
273 /* The original rw GDT is being used after load_direct_gdt() */
274 if (within_area(addr
, end
, (unsigned long)get_cpu_gdt_rw(cpu
),
279 * cpu_tss_rw is not directly referenced by hardware, but
280 * cpu_tss_rw is also used in CPU entry code,
282 if (within_area(addr
, end
,
283 (unsigned long)&per_cpu(cpu_tss_rw
, cpu
),
284 sizeof(struct tss_struct
)))
288 * cpu_tlbstate.user_pcid_flush_mask is used for CPU entry.
289 * If a data breakpoint on it, it will cause an unwanted #DB.
290 * Protect the full cpu_tlbstate structure to be sure.
292 if (within_area(addr
, end
,
293 (unsigned long)&per_cpu(cpu_tlbstate
, cpu
),
294 sizeof(struct tlb_state
)))
301 static int arch_build_bp_info(struct perf_event
*bp
,
302 const struct perf_event_attr
*attr
,
303 struct arch_hw_breakpoint
*hw
)
305 unsigned long bp_end
;
307 bp_end
= attr
->bp_addr
+ attr
->bp_len
- 1;
308 if (bp_end
< attr
->bp_addr
)
312 * Prevent any breakpoint of any type that overlaps the CPU
313 * entry area and data. This protects the IST stacks and also
314 * reduces the chance that we ever find out what happens if
315 * there's a data breakpoint on the GDT, IDT, or TSS.
317 if (within_cpu_entry(attr
->bp_addr
, bp_end
))
320 hw
->address
= attr
->bp_addr
;
324 switch (attr
->bp_type
) {
325 case HW_BREAKPOINT_W
:
326 hw
->type
= X86_BREAKPOINT_WRITE
;
328 case HW_BREAKPOINT_W
| HW_BREAKPOINT_R
:
329 hw
->type
= X86_BREAKPOINT_RW
;
331 case HW_BREAKPOINT_X
:
333 * We don't allow kernel breakpoints in places that are not
334 * acceptable for kprobes. On non-kprobes kernels, we don't
335 * allow kernel breakpoints at all.
337 if (attr
->bp_addr
>= TASK_SIZE_MAX
) {
338 if (within_kprobe_blacklist(attr
->bp_addr
))
342 hw
->type
= X86_BREAKPOINT_EXECUTE
;
344 * x86 inst breakpoints need to have a specific undefined len.
345 * But we still need to check userspace is not trying to setup
346 * an unsupported length, to get a range breakpoint for example.
348 if (attr
->bp_len
== sizeof(long)) {
349 hw
->len
= X86_BREAKPOINT_LEN_X
;
358 switch (attr
->bp_len
) {
359 case HW_BREAKPOINT_LEN_1
:
360 hw
->len
= X86_BREAKPOINT_LEN_1
;
362 case HW_BREAKPOINT_LEN_2
:
363 hw
->len
= X86_BREAKPOINT_LEN_2
;
365 case HW_BREAKPOINT_LEN_4
:
366 hw
->len
= X86_BREAKPOINT_LEN_4
;
369 case HW_BREAKPOINT_LEN_8
:
370 hw
->len
= X86_BREAKPOINT_LEN_8
;
374 /* AMD range breakpoint */
375 if (!is_power_of_2(attr
->bp_len
))
377 if (attr
->bp_addr
& (attr
->bp_len
- 1))
380 if (!boot_cpu_has(X86_FEATURE_BPEXT
))
384 * It's impossible to use a range breakpoint to fake out
385 * user vs kernel detection because bp_len - 1 can't
386 * have the high bit set. If we ever allow range instruction
387 * breakpoints, then we'll have to check for kprobe-blacklisted
388 * addresses anywhere in the range.
390 hw
->mask
= attr
->bp_len
- 1;
391 hw
->len
= X86_BREAKPOINT_LEN_1
;
398 * Validate the arch-specific HW Breakpoint register settings
400 int hw_breakpoint_arch_parse(struct perf_event
*bp
,
401 const struct perf_event_attr
*attr
,
402 struct arch_hw_breakpoint
*hw
)
408 ret
= arch_build_bp_info(bp
, attr
, hw
);
413 case X86_BREAKPOINT_LEN_1
:
418 case X86_BREAKPOINT_LEN_2
:
421 case X86_BREAKPOINT_LEN_4
:
425 case X86_BREAKPOINT_LEN_8
:
435 * Check that the low-order bits of the address are appropriate
436 * for the alignment implied by len.
438 if (hw
->address
& align
)
445 * Release the user breakpoints used by ptrace
447 void flush_ptrace_hw_breakpoint(struct task_struct
*tsk
)
450 struct thread_struct
*t
= &tsk
->thread
;
452 for (i
= 0; i
< HBP_NUM
; i
++) {
453 unregister_hw_breakpoint(t
->ptrace_bps
[i
]);
454 t
->ptrace_bps
[i
] = NULL
;
461 void hw_breakpoint_restore(void)
463 set_debugreg(__this_cpu_read(cpu_debugreg
[0]), 0);
464 set_debugreg(__this_cpu_read(cpu_debugreg
[1]), 1);
465 set_debugreg(__this_cpu_read(cpu_debugreg
[2]), 2);
466 set_debugreg(__this_cpu_read(cpu_debugreg
[3]), 3);
467 set_debugreg(DR6_RESERVED
, 6);
468 set_debugreg(__this_cpu_read(cpu_dr7
), 7);
470 EXPORT_SYMBOL_GPL(hw_breakpoint_restore
);
473 * Handle debug exception notifications.
475 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
477 * NOTIFY_DONE returned if one of the following conditions is true.
478 * i) When the causative address is from user-space and the exception
479 * is a valid one, i.e. not triggered as a result of lazy debug register
481 * ii) When there are more bits than trap<n> set in DR6 register (such
482 * as BD, BS or BT) indicating that more than one debug condition is
483 * met and requires some more action in do_debug().
485 * NOTIFY_STOP returned for all other cases
488 static int hw_breakpoint_handler(struct die_args
*args
)
490 int i
, rc
= NOTIFY_STOP
;
491 struct perf_event
*bp
;
492 unsigned long *dr6_p
;
495 /* The DR6 value is pointed by args->err */
496 dr6_p
= (unsigned long *)ERR_PTR(args
->err
);
499 /* If it's a single step, TRAP bits are random */
503 /* Do an early return if no trap bits are set in DR6 */
504 if ((dr6
& DR_TRAP_BITS
) == 0)
507 /* Handle all the breakpoints that were triggered */
508 for (i
= 0; i
< HBP_NUM
; ++i
) {
509 if (likely(!(dr6
& (DR_TRAP0
<< i
))))
513 * The counter may be concurrently released but that can only
514 * occur from a call_rcu() path. We can then safely fetch
515 * the breakpoint, use its callback, touch its counter
516 * while we are in an rcu_read_lock() path.
520 bp
= this_cpu_read(bp_per_reg
[i
]);
522 * Reset the 'i'th TRAP bit in dr6 to denote completion of
525 (*dr6_p
) &= ~(DR_TRAP0
<< i
);
527 * bp can be NULL due to lazy debug register switching
528 * or due to concurrent perf counter removing.
535 perf_bp_event(bp
, args
->regs
);
538 * Set up resume flag to avoid breakpoint recursion when
539 * returning back to origin.
541 if (bp
->hw
.info
.type
== X86_BREAKPOINT_EXECUTE
)
542 args
->regs
->flags
|= X86_EFLAGS_RF
;
547 * Further processing in do_debug() is needed for a) user-space
548 * breakpoints (to generate signals) and b) when the system has
549 * taken exception due to multiple causes
551 if ((current
->thread
.virtual_dr6
& DR_TRAP_BITS
) ||
552 (dr6
& (~DR_TRAP_BITS
)))
559 * Handle debug exception notifications.
561 int hw_breakpoint_exceptions_notify(
562 struct notifier_block
*unused
, unsigned long val
, void *data
)
564 if (val
!= DIE_DEBUG
)
567 return hw_breakpoint_handler(data
);
570 void hw_breakpoint_pmu_read(struct perf_event
*bp
)